KR20140110992A - Digital hybrid mode power amplifier system - Google Patents

Abstract

A RF-digital hybrid mode power amplifier system for achieving high efficiency and high linearity in a broadband communication system is disclosed. The present invention is based on a method of adaptive digital predistortion that linearizes a power amplifier in the RF domain. Power amplifier characteristics such as variations in the linearity of the amplifier output signal and asymmetric distortion are monitored by a narrowband feedback path and controlled by an adaptive algorithm in the digital module. Therefore, the present invention can compensate for non-linearities as well as memory effects of power amplifier systems and also improve performance in terms of power added efficiency, adjacent channel leakage equipment, and maximum power to average power ratio. This specification allows the power amplifier system to support field reconfigurable and multiple modulation schemes (modulation agnostic), multiple carriers and multiple channels. As a result, this digital hybrid mode power amplifier system is particularly well suited for wireless transmission systems such as base stations, repeaters, and indoor signal coverage systems where baseband IQ signal information is not readily available.

Description

[0001] DIGITAL HYBRID MODE POWER AMPLIFIER SYSTEM [0002]

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates generally to wireless communication systems that employ complex modulation techniques. More particularly, the present invention relates to a power amplifier system for wireless communication.

[Related Application]

This application is a contiunation-in-part of U.S. Patent Application Serial No. 12 / 021,241, filed January 28, 2008, entitled Power Amplifier Time-Delay Invariant Predistortion Methods and Apparatus, Serial No. 11 / 799,239, filed on April 30, 2007 entitled High Efficiency Linearization Power Amplifier For Wireless Communication, which application is also referred to as System and Method for Digital Memorized Predistortion for Wireless Communication No. 11 / 262,079, filed October 27, 2005, which is also a continuation-in-part of U.S. Patent Application Serial No. 10 / 262,079 entitled System and Method for Digital Memorized Predistortion for Wireless Communication, (Now U.S. Patent No. 6,985,704), all of which are incorporated herein by reference. This application claims priority from U.S. Patent Application Serial No. 11 / 961,969, filed December 20, 2007, entitled A Method for Baseband Predistortion Linearization in Multi-Channel Wideband Communication Systems. The present application claims the benefit of US Patent Application Serial No. 60 / 925,603, filed April 23, 2007, the disclosure of which is hereby incorporated by reference herein in its entirety, except Dali Yang, and claims the benefit of An Efficient Peak Cancellation Method for Reducing the Peak- Priority is claimed on U.S. Provisional Patent Application Serial No. 61 / 041,164, filed on March 31, 2008, entitled Power Ratio in Wideband Communication Systems, and also entitled Baseband Derived RF Digital Predistortion, Priority is claimed of U.S. Provisional Patent Application Serial No. 61 / 012,416, filed on April 23, 2007, and also assigned to U.S. Provisional Patent Application Serial No. 60 / 925,577 entitled N-Way Doherty Distributed Power Amplifier . This application is also related to U.S. Patent Application Serial No. 11 / 962,025, filed December 20, 2007, entitled Power Amplifier Predistortion Methods and Apparatus, on Aug. 30, 2007 entitled Analog Power Amplifier Predistortion Methods and Apparatus Filed U.S. Provisional Patent Application Serial No. 60 / 969,127, and United States Patent Application Serial No. 60 / 969,131 entitled Power Amplifier Predistortion Methods and Apparatus Using Envelope and Phase Detector. All of the above applications are incorporated herein by reference.

A wideband mobile communication system using complex modulation techniques such as wideband code division access (WCDMA) and orthogonal frequency division multiplexing (OFDM) has a large peak-to-average power ratio (PAPR) Thus requiring a highly linear power amplifier for its RF transmission. Conventional feedforward linear power amplifiers (FFLPAs) have been widely used due to their excellent linear performance despite poor power efficiency.

Conventional FFLPAs are based primarily on the principles of error subtraction and power-matching using dedicated hardware circuits to achieve nonlinear correction for PA. These approaches must use auxiliary PAs and complex hardware circuits to accurately match the transmit power balance, time delays and errors generated by the main PA. After a perfect match is obtained, the non-linear distortion errors from the main PA can then be canceled by the distortion errors from the auxiliary PA. Due to the complexity of nonlinear predistortion circuits, especially with many variables and parameters, FFLPAs require significant fine tuning and other corrective efforts. In addition, since perfect alignment of the main PA signal and the auxiliary PA signal is critical, such conventional FFLPA schemes are also vulnerable to fluctuating environmental conditions, such as temperature and humidity changes. As a result, conventional predistortion schemes are costly to implement and limited in their predistortion accuracy and stability in commercial wireless communication environments.

In order to overcome the inferior efficiency of FFPLA, digital baseband predistortion (PD) has been demonstrated with advances in digital signal processing (DSP) technology. A Doherty power amplifier (DPA) was also applied to these linearization systems to improve power efficiency. However, there is still a need for higher performance of power amplifiers, such as greater linearity and better efficiency with less costly architectures.

Conventional DSP-based PD schemes use a digital microprocessor to calculate, calculate and correct the non-linearity of the PA: they perform fast tracking and adjustment of signals in the PA system. However, conventional DSP-based PD schemes are challenged by variations in the linearity performance of the amplifier due to asymmetric distortion of the PA's output signal resulting from environmental changes such as temperature and memory effects. All such variations and distortions must be compensated. Because conventional PD algorithms are based on wideband feedback signals, they require a high-speed, high-speed analog-to-digital converter (ADC) that is power-intensive to capture the necessary information, . Time synchronization is also inevitable to capture the error signal between the reference signal and the distorted signal. This time matching process may result in small synchronization errors that may further affect the linearization performance of conventional PD schemes.

In addition, conventional PD schemes require coded in-phase (I) and quadrature-phase (Q) channel signals within the baseband as required ideal or reference signals. As a result, conventional PD schemes are often standard or modulation specific and must be precisely matched to each baseband system. Therefore, in order to deploy conventional PD schemes to base stations, the PD engines must be inserted within the baseband architecture of the base stations. Once the PD scheme is set up for a particular base station design, it is often not reconfigurable and therefore not upgradeable for future changes in standard or modulation. In addition, since conventional PD approaches require baseband IQ signal sources to operate, they may be used as baseband IQ signal sources, such as repeater and indoor signal coverage subsystems, It is not applicable to certain RF systems not equipped with

SUMMARY OF THE INVENTION [

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a high performance and cost effective method for power amplifier systems with high linearity and high efficiency for broadband communication system applications. This specification allows the power amplifier system to support field reconfigurable and multiple modulation schemes (modulation agnostic), multiple carriers and multiple channels.

To achieve these objects, in accordance with the present invention, this technique is generally based on a method of adaptive digital predistortion that linearizes a power amplifier in the RF domain. Various embodiments of the present invention are disclosed. In one embodiment, a combination of crest factor reduction, PD, power efficiency rise techniques is used as well as a simple algorithm with spectral monitoring within the PA system. In another embodiment, an analog quadrature modulator compensation scheme is also used to enhance performance.

Some embodiments of the present invention are capable of monitoring variations in power amplifier characteristics and self-adjusting by a self-adaptation algorithm. One such self-regulation algorithm that is currently being disclosed is a multi-directional search (MDS) algorithm implemented in the digital domain.

Applications of the present invention are suitable for use with all wireless base stations, access points, mobile equipment and wireless terminals, portable wireless devices, and other wireless communication systems such as microwave and satellite communications.

Annex I is a catalog of terms used here, including acronyms.

Further objects and advantages of the present invention can be more fully understood by reading the following detailed description together with the accompanying drawings.
1 is a block diagram illustrating a basic form of a digital hybrid mode power amplifier system.
2 is a block diagram illustrating a simple digital hybrid mode power amplifier system in accordance with an embodiment of the present invention.
3 is a block diagram illustrating a polynomial based predistortion in the digital hybrid mode power amplifier system of the present invention.
4 is a flowchart of a multi-directional search algorithm applied for self-adaptive predistortion in the digital hybrid mode power amplifier system of the present invention.
5 is a block diagram illustrating a digital hybrid mode power amplifier system implemented with an optional or alternative multi-channel digital input, DQM and UPC based clipping restoration path according to another embodiment of the present invention.
6 is a block diagram illustrating a digital hybrid mode power amplifier system implemented with DQM according to another embodiment of the present invention.
7 is a block diagram illustrating a digital hybrid mode power amplifier system implemented with AQM according to another embodiment of the present invention.
8 is a block diagram illustrating a digital hybrid mode power amplifier system implemented with a DUPC and UPC based clipping error restoration path according to another embodiment of the present invention.
9 is a block diagram illustrating a digital hybrid mode power amplifier system implemented with AQM and AQM based clipping error recovery paths in accordance with another embodiment of the present invention.
10 is a block diagram showing an analog quadrature modulator compensation structure.

The present invention is a novel RF-in / RF-out (PA) system using an adaptive digital predistortion algorithm. The present invention is a hybrid system of digital and analog modules. The interaction of the digital and analog modules of the hybrid system linearizes the spectral regrowth while maintaining or increasing the wide bandwidth and enhances the power efficiency of the PA. Therefore, the present invention achieves higher efficiency and higher linearity for wideband complex modulated carriers.

1 is a high-level block diagram illustrating a basic system architecture that may, at least in some embodiments, be considered to include digital and analog modules and feedback paths. The digital module is a digital predistortion controller 14 that includes a PD algorithm, other auxiliary DSP algorithms, and associated digital circuits. The analog module is a main analog amplifier 12, other auxiliary analog circuits such as DPA, and related peripheral analog circuits of the overall system. The present invention takes the RF modulated signal 10 as its input and provides a substantially identical but amplified RF signal 13 as its output and is therefore a RF-input / RF- , A plug-and-play type system. The feedback path essentially provides a representation of the output signal to the predistortion controller 14. The present invention is sometimes referred to below as a digital hybrid mode power amplifier (DHMPA).

2 is a block diagram illustrating a simple digital hybrid mode power amplifier system in accordance with an embodiment of the present invention. The embodiment of FIG. 2 is similar to the embodiment of FIG. 2 except that (i) the RF modulated signal 10, V _RF, passes only downconverter 20, (ii) a digital multiplier 31 is used instead of analog multipliers, The predistorted signal, V _p, is upconverted to the IF band and then converted to an analog IF signal by the DAC 30, and finally supplied to the mixer 311 before being provided as an input to the PA 12 for wireless transmission. , Which is similar to the architecture disclosed in U.S. Patent Application Serial No. 11 / 799,239, which is incorporated herein by reference, except that it is modulated by the V _in RF signal.

5-9 are block diagrams illustrating more complex embodiments of the DHMPA system in which similar elements are indicated with similar numbers. The five embodiments of FIGS. 5-9 illustrate that in one digital processor, the PD by the adaptive algorithm leads to a reduction of the distortion rate (e.g., < RTI ID = 0.0 > crest factor reduction (CFR). A digital processor can take almost any form; For convenience, an FPGA implementation is shown as an example, but a general purpose processor may also be acceptable in many embodiments. The CFRs implemented in the digital modules of the embodiments are described in U.S. Patent Application No. 10 / 021,995, filed March 31, 2008, entitled " An Efficient Peak Cancellation Method For Reducing The Peak-To-Average Power Ratio In Wideband Communication Systems " Is based on the scaled iterative pulse cancellation presented in the application US61 / 041,164. CFR is included to enhance performance and is therefore optional. The CFR can be removed from the embodiments without affecting the overall functionality.

5 is a block diagram illustrating a DHMPA system ("FIG. 5 system") in accordance with an embodiment of the present invention. 5 system has a dual mode RF 500 and / or multiple carrier digital signal 505 at its input and an RF signal at its output 510. Dual mode signal input allows maximum flexibility: RF-input ("RF-input mode") or baseband digital-input ("baseband-input mode"). The system of FIG. 5 includes three important parts: a reconfigurable digital (hereinafter referred to as "FPGA-based digital") module 515, a power amplifier module 520, and a feedback path 525.

The FPGA-based digital portion may include a digital processor 530 (e.g., an FPGA), digital-to-analog converters 535 (DACs), analog to digital converters 540 (ADCs), and phase- loop (545). Since the Figure 5 system has dual mode inputs, the digital processor has two signal processing paths. For the RF signal input path, the digital processor implements a digital quadrature demodulator (DQDM), a CFR, a PD, and a digital quadrature modulator (DQM). For the baseband digital input path, a digital up-converter (DUC), CFR, PD, and DQM are implemented.

The RF-input mode of the FIG. 5 system implements the ADC 540 prior to the downconverter (DNC) 550 and the FPGA prior to the FPGA-based digital portion. The analog downconverted signal is provided to the FPAG based digital module and is converted to a digital signal by the ADC 540. The digitally converted signal is demodulated by the DQDM to produce both real and imaginary signals, and then the PARR of that signal is reduced by the CFR. The peak-reduced signal is predistorted to linearize the amplifier, passed through DQM to produce a real signal, and then converted to an intermediate frequency (IF) analog signal by the DAC in the FPGA-based digital portion. However, implementing DQDM and DQM in FPAG is not required in all embodiments. 7 and 9, if the modulator and demodulator are not used, the two ADCs 700 and 705 prior to the FPGA and the two ADCs 700 and 705 behind the FPGA feeding the AQM module 720, DACs 710 and 715 can be used to generate real and imaginary signals, respectively ("AQM implementation"). The embodiment of FIG. 9 is similar to the addition of the clipping error recovery path indicated by the DACs 900 and 905 with the second AQM logic 910, which feeds the RF output signal in a manner similar to that shown in FIG. Which is different from the embodiment of Fig.

The baseband-input mode of FIG. 5 operates somewhat differently from the RF-input mode. Digital data streams from multiple channels as I-Q signals enter the FPGA-based digital module and are digitally upconverted to digital IF signals by the DUC. From this point on, the baseband-input mode and the RF-input mode proceed in the same way. These IF signals then pass through the CFR block to reduce the PARR of the signal. This PARR suppressed signal is digitally predistorted to compensate for the nonlinear distortion of the power amplifier in advance.

In either input mode, memory effects due to active heating, bias network, and frequency dependence of the active device are likewise compensated by an adaptive algorithm in the PD. The PD's coefficients are adapted by narrow band feedback using a simple power detector in the feedback portion as opposed to prior art predistortion techniques using broadband feedback requiring very fast ADCs. The predistorted signal passes through DQM to produce a real signal and is then converted to an IF analog signal by DAC 535 as shown. As described above, the DQM need not be implemented at all in the FPGA, or in all embodiments. If DQM is not used in the FPGA, the AQM implementation can be implemented with two DACs, each generating real and imaginary signals. The gate bias voltage 550 of the power amplifier is determined by the adaptive algorithm and then adjusted via the DACs 535 to stabilize the linearity variation due to the temperature change of the power amplifier. The PLL first finds the channel positions and then sweeps the local oscillation signal for the feedback portion to detect the adjacent channel power level or adjacent channel power ratio (ACPR).

The power amplifier portion may be a UPC, or FPGA-based digital module for a real signal (such as that shown in the embodiments shown in Figures 5,6 and 8), a high power amplifier with multi-stage drive amplifiers, And AQM for real and complex signals (as shown in the embodiments shown in Figs. 7 and 9) from a temperature sensor. The predistorted baseband signals are upconverted by the UPC 555 and then amplified by the PA 560. In order to improve the efficiency performance of the DHMPA system, according to an embodiment, an EF (Envelope Elimination and Restoration), an Envelope Tracking (ET), an Envelope Following (EF) Linear amplification using Nonlinear Components (LINC) may be used. These power efficiency schemes can be mixed and matched and are an optional feature of the basic DHMPA system. One such Doherty power amplifier technique is disclosed in commonly assigned US patent application US 60 / 925,577, filed April 23, 2007, entitled N-Way Doherty Distributed Power Amplifier, incorporated herein by reference. To stabilize the linearity performance of the amplifier, the temperature of the amplifier is monitored by a temperature sensor and then the gate bias of the amplifier is controlled by the FPGA-based digital portion.

The feedback portion includes a directional coupler, a mixer, a low pass filter (LPF), gain amplifiers, and a band pass filter (BPF), detectors (DETs). Depending on the embodiment, these analog components may be mixed and matched with other analog components. A portion of the RF output signal of the amplifier is sampled by a directional coupler and then down-converted to an IF analog signal by a local oscillator signal in the mixer. The IF analog signal passes through a BPF (e.g., a surface acoustic wave filter) capable of capturing LPF, gain amplifiers, and different frequency portions of out-of-band distortions. The output of the BPF is provided to the detectors and then provided to the ADCs of the FPGA-based digital module to determine the dynamic parameters of the PD according to the asymmetric distortions and output power levels due to the memory effect. The temperature is also detected by the DET 580 to calculate the variation in linearity and then adjust the gate bias voltage of the PA. More details of the PD algorithm and the self-adaptive feedback algorithm can be seen from FIG. 3, which shows a polynomial-based predistortion algorithm, and a multi-way search algorithm, which may be used in some embodiments of the present invention, It can be seen from FIG.

In the case of stringent EVM requirements for broadband wireless access such as WiMAX or other OFDM-based schemes (EVM <2.5%), CFRs in the FPGA-based digital portion can only achieve a small reduction in PARR to meet stringent EVM specifications have. Under normal circumstances, this means that the CFR's ability to enhance power efficiency is limited. In some embodiments of the present invention, a new technique is included to compensate for in-band distortions from the CFR using the "clipping error recovery path" 590 and thus maximize the DHMPA system power efficiency in those stringent EVM environments . As described above, the clipping error recovery path has an additional DAC 520 in the FPGA-based digital portion and an extra UPC in the power amplifier portion (see Figures 5 and 8). The clipping error recovery path may allow compensation of in-band distortions resulting from the CFR at the output of the power amplifier. In addition, any delay mismatch between the primary path and the clipping error recovery path can be aligned using the digital delay in the FPGA.

Figure 6 is a block diagram illustrating a DHMPA system ("Figure 6 system") implemented with DQM in accordance with another embodiment of the present invention. It is identical to the FIG. 5 system except that it does not have a baseband-input mode and a clipping error recovery path.

Figure 7 is a block diagram illustrating a DHMPA system ("Figure 7 system") implemented with an AQM in accordance with another embodiment of the present invention. The system of Figure 7 is similar to the system of Figure 6 except that it has the AQM implementation option described above. Also, the digital processor of the system of FIG. 7 implements analog quadrature demodulator corrector (AQDMC), CFR, PD, and analog quadrature modulator corrector (AQMC).

7 system, the RF input signal is first downconverted to baseband digital signals and then upconverted to IF signals (-7.5 MHz, -2.5 MHz, 2.5 MHz, 7.5 MHz). If the system of FIG. 7 has a baseband-input mode, the digital data streams from the multiple channels are converted into digital IF signals (-7.5 MHz, -2.5 MHz, 2.5 MHz, 7.5 MHz) As shown in FIG. The CFR will then decrease the PAPR. The peak reduced signal is predistorted to linearize the DPA and passes through the two DACs for the real and imaginary signals and finally through the AQM.

10 is a block diagram showing an analog quadrature modulator compensation structure. The input signal is an input separated into an in-phase component X _I and a quadrature component X _Q. The analog quadrature modulator compensation scheme includes four real-valued filters {g11, g12, g21, g22} and two DC offset compensation parameters c1, c2. The DC offsets in AQM will be compensated by parameters c1, c2. The frequency dependence of the AQM will be compensated by the filters {g11, g12, g21, g22}. The order of real filters depends on the level of compensation required. The output signals Y _I and Y _Q will be provided to the in-phase and quadrature ports of the AQM.

The configuration of the power amplifier portion and feedback portion of the system of Figure 7 is the same as that of Figure 6 system.

Figure 8 is a block diagram illustrating a DHMPA system ("Figure 8 system") implemented with a DUC and clipping error recovery path in accordance with another embodiment of the present invention. The system of Figure 8 is similar to the system of Figure 6 except that it has a clipping error recovery path. In addition, the digital processor of the Fig. 8 system implemented a digital downconverter (DDC), CFR, PD, and DUC.

In the Fig. 8 system, the DNC frequency converts the RF signal to a low IF signal. The IF signal is then provided to the ADC, which is then downconverted to the baseband digitally and then the CFR and PD are performed. The output of the PD is the baseband signal, which will then be digitally upconverted to the IF frequency and provided to the DAC. The output of the DAC is then further frequency converted to an RF frequency via the UPC. The configuration of the power amplifier portion and feedback portion of the system of Figure 8 is the same as that of Figure 5 system.

9 is a block diagram illustrating a DHMPA system ("Figure 9 system") implemented to have AQM and AQM based clipping error recovery paths in accordance with another embodiment of the present invention. The system of Figure 9 is identical to the system of Figure 7 except that it has a clipping error recovery path. The clipping error recovery path of the Figure 9 system has two DACs in the FPGA-based digital portion and AQM in the power amplifier portion instead of UPC (see Figures 5 and 8).

3 is a block diagram illustrating the predistortion (PD) portion of the DHMPA system of the present invention. The PD in the present invention generally uses an adaptive LUT-based digital predistortion system. More specifically, the PD shown in the embodiments disclosed in FIG. 3 and FIGS. 5 to 9 is an adaptation presented in U.S. Patent Application Serial No. 11 / 961,969 entitled A Method for Baseband Predistortion Linearization in Multi-Channel Wideband Communication Systems And is processed by a digital processor by an algorithm. The PD for the DHMPA system of FIG. 3 has a plurality of finite impulse response (FIR) filters, FIR1 301, FIR2 303, FR3 305, and FIR4 307. The PD also includes a third product generation block 302, a fifth product generation block 304, and a seventh product generation block 306. The output signals from the FIR filters are combined in a summing block 308. The coefficients for the plurality of FIR filters are updated by the MDS algorithm based on the adjacent channel power level or ACPR as an estimate function.

4 is a flowchart of a method of compensating PD in the DHMPA system of the present invention. It is a self-adaptive feedback part of the DHMPA system that uses the MDS algorithm. The operation of the predistortion compensator of Fig. 3 can be described with reference to this flowchart.

For brevity, but not as a limitation, WCDMA has been used as an example to illustrate the self-adaptive feedback portion and the MDS algorithm. Since the present invention is both standard and modulated, the present invention is never limited to WCDMA. In a WCDMA application, 12 WCDMA channels are first detected (401) by sweeping the PLL in the feedback portion to retrieve the activated and deactivated channels. Once the channel positions are retrieved 402, the feedback portion detects the adjacent channel power level or ACPR (especially 5 MHz offset components) by sweeping the PLL again (403). Then initialize the predistortion and apply the MDS algorithm as follows:

At any iteration k, each set of coefficients is evaluated and then the optimal set a ₀ ^k is found (404).

Rotation (405): Evaluate by rotating a ₀ ^k . If min {f ( a _ri ^k ), i = 1, ..., n} <f ( a ₀ ^k ) is achieved 406, proceed to extension 407; Otherwise, proceed to reduction 409.

Expansion (407): Evaluate by expanding a _ri ^k . If ^{_{min {f (a ei k)}} , i = 1, ..., n} <min {f (a ri k), i = 1, ..., n} is achieved when the (408), a ₀ ^k = a _ei ^k is set; Otherwise, set a ₀ ^k = a _ri ^k and proceed to (1).

Reduction 409: a ₀ ^k is reduced and evaluated, and a ₀ ^k = a _ci ^k is set, and then the process proceeds to (1).

Where a is a vector of coefficients for a plurality of FIR filters, and f is an adjacent channel power level or ACPR.

If the evaluation function is less than the minimum target value (410), the algorithm terminates. This MDS algorithm can be implemented elegantly and simply.

In summary, the DHMPA system of the present invention implements CFR, DPD, and adaptive algorithms in one digital processor, resulting in savings in hardware resources and processing time, thereby enhancing performance for efficiency and linearity more effectively have. The DHMPA system is also reconfigurable and field programmable because its algorithms and power-efficient enhancement features can be adjusted at any time, like software in a digital processor.

In addition, since the present DHMPA system accepts an RF modulated signal as an input, there is no need to use coded I and Q channel signals in the baseband. Therefore, the performance of wireless base station systems can be enhanced simply by replacing existing PA modules with the present DHMPA. The present invention provides a "plug and play" PA system solution that does not require existing base station systems to change their structures and / or rebuild a new set of signaling channels to benefit from high efficiency and high linearity PA system performance Allow.

Moreover, the present DHMPA system is agnostic to modulation schemes such as QPSK, QAM, OFDM, etc. in CDMA, GSM, WCDMA, CDMA2000, and wireless LAN systems. This means that the present DHMPA system is capable of supporting multiple modulation schemes, multiple carriers and multiple channels. Another benefit of this DHMPA system includes the correction of PA nonlinearities in repeater or indoor coverage systems where the required baseband signal information is not readily available.

Although the present invention has been described in connection with preferred embodiments, it will be understood that the invention is not limited to the details set forth herein. Various alternatives and modifications have been suggested in the foregoing description, and those of ordinary skill in the art will recognize other things. Therefore, all such alternatives and modifications should be included within the scope of the present invention as defined in the appended claims.

[Appendix I]

A term dictionary

ACLR - Adjacent Channel Leakage Ratio

ACPR - Adjacent Channel Power Ratio

ADC - Analog to Digital Converter

AQDM - Analog Quadrature Demodulator

AQM - Analog Quadrature Modulator

AQDMC - Analog Quadrature Demodulator Corrector

AQMC - Analog Quadrature Modulator Corrector

BPF - Bandpass Filter

CDMA - Code Division Multiple Access (CDMA)

CFR - Crest Factor Reduction

DAC - Digital to Analog Converter

DET - Detector

DHMPA - Digital Hybrid Mode Power Amplifier

DDC - Digital Down Converter

DNC - Down Converter (Down Converter)

DPA - Doherty Power Amplifier (Doherty Power Amplifier)

DQDM - Digital Quadrature Demodulator

DQM - Digital Quadrature Modulator

DSP - Digital Signal Processing

DUC - Digital Up Converter

EER - Envelope Elimination and Restoration

EF - Envelope Following

ET - Envelope TRacking

EVM - Error Vector Magnitude (Error Vector Magnitude)

FFLPA - Feedforward Linear Power Amplifier

FIR - Finite Impulse Response

FPGA-Field-Programmable Gate Array

GSM - Global System for Mobile communications

I-Q - In-phase / Quadrature

IF - Intermediate Frequency

LINC - Linear Amplification using Nonlinear Components

LO - Local Oscillator

LPF - Low Pass Filter

MCPA - Multi-Carrier Power Amplifier

MDS - Multi-Directional Search

OFDM - Orthogonal Frequency Division Multiplexing (OFDM)

PA - Power Amplifier

PAPR - Peak-to-Average Power Ratio (PAPR)

PD - Digital Baseband Predistortion

PLL - Phase Locked Loop

QAM - Quadrature Amplitude Modulation

QPSK - Quadrature Phase Shift Keying (QPSK)

RF - Radio Frequency

SAW - Surface Acoustic Wave Filter

UMTS - Universal Mobile Telecommunications System

UPC - Up Converter

WCDMA - Wideband Code Division Multiple Access (WCDMA)

WLAN - Wireless Local Area Network (WLAN)

Claims (1)

A method of updating coefficients of predistortion in a digital hybrid mode power amplifier (DHMPA) system of the present invention,
Retrieving locations of a main channel signal to detect adjacent channel powers; And
A multi-directional search algorithm including evaluation, rotation, expansion, and contraction using the adjacent channel power value or adjacent channel power ratio as an evaluation function, Lt; RTI ID = 0.0 &gt;
Wherein the coefficients of the predistortion are updated in a digital hybrid mode power amplifier system.

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