KR20140021110A - High electron mobility transistor and manufacturing method of the same - Google Patents

High electron mobility transistor and manufacturing method of the same Download PDF

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KR20140021110A
KR20140021110A KR1020120086394A KR20120086394A KR20140021110A KR 20140021110 A KR20140021110 A KR 20140021110A KR 1020120086394 A KR1020120086394 A KR 1020120086394A KR 20120086394 A KR20120086394 A KR 20120086394A KR 20140021110 A KR20140021110 A KR 20140021110A
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South Korea
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semiconductor layer
region
layer
recess region
semiconductor
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KR1020120086394A
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Korean (ko)
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허홍표
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삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A high electron mobility transistor is disclosed. The disclosed high electron mobility transistor may include a recess region formed in the first semiconductor layer, and may include a 2DEG region formed at a lower end and an upper end of the recess region, respectively.

Description

TECHNICAL FIELD [0001] The present invention relates to a high electron mobility transistor and a manufacturing method thereof,

Embodiments of the present invention relate to a semiconductor device, and more particularly, to a high electron mobility transistor (HEMT) including a 2DEG region separated from a lower end and an upper end of a recess region.

As communication technology develops, electronic devices used in a high frequency region are being studied. Particularly, a field effect type semiconductor device such as a high electron mobility transistor (HEMT) is attracting attention as a power electronic device used in a high frequency region.

A high electron mobility transistor includes a heterojunction structure in which semiconductor material layers having different band gaps are formed adjacent to each other, and a semiconductor material layer having a large bandgap serves as a donor. As the materials having different band gaps are formed in a heterojunction structure, a two-dimensional electron gas layer (2DEG) may be induced in the semiconductor material layer having a small band gap, thereby improving the movement speed of electrons. .

A high electron mobility transistor can be used not only to enhance the mobility of an electron carrier, but also as a high voltage transistor as one of the power electronic devices. High electron mobility transistors include semiconductors having a wide band gap, such as compound semiconductors, and can have a relatively high breakdown voltage, which can be used in fields where a high voltage is applied.

In general, silicon, which is widely used for semiconductor devices, has a low electron mobility and may cause a high source resistance, and research is currently underway to apply a III-V semiconductor compound to a high electron mobility transistor. In particular, the gallium nitride compound has a relatively wide band gap, has a high electron saturation velocity, and is chemically stable. Therefore, the gallium nitride compound has attracted attention as a material for a high electron mobility transistor. Therefore, a high electron mobility transistor using a gallium nitride compound has been actively studied as a high temperature, high output and high frequency electronic device.

One aspect of the present invention is to provide a high electron mobility transistor including a 2DEG region formed below the recess gate.

Another aspect of the present invention is to provide a method of manufacturing a high electron mobility transistor including a 2DEG region formed under the recess gate.

In the disclosed embodiment,

Board;

A first semiconductor layer formed on the substrate and including a recess region; And

And a second semiconductor layer formed on each of a lower end and an upper end of the recess region of the first semiconductor layer.

Provided is a high electron mobility transistor including 2DEG regions respectively formed at a lower end and an upper end of a recess region of the first semiconductor layer.

A source and a drain formed on both sides of the second semiconductor layer;

A gate insulating layer formed on the first semiconductor layer and the second semiconductor layer except for the region where the source and drain are formed; And

And a gate formed on the gate insulating layer.

And a buffer layer formed between the substrate and the first semiconductor layer.

The recess region of the first semiconductor layer may have a metal-insulator-semiconductor (MIS) structure of a gate, a gate insulating layer, and the first semiconductor layer.

The buffer layer may include a recess region corresponding to the recess region of the first semiconductor layer.

The substrate and the buffer layer may include a recess region corresponding to the recess region of the first semiconductor layer.

The first semiconductor layer may be formed of GaN, GaAs, InN, InGaN or AlGaN.

The second semiconductor layer may be formed of AlN, AlGaN, AlInN, AlGaInN or AlGaAs.

In addition, forming a buffer layer, a first semiconductor layer and a second semiconductor layer on the substrate;

Forming a recess region in the second semiconductor layer and the first semiconductor layer by an etching process;

And forming a second semiconductor layer at a lower end of the recess region of the first semiconductor layer.

Forming a gate insulating layer on surfaces of the first semiconductor layer and the second semiconductor layer; And

After removing a portion of the gate insulating layer on both sides of the second semiconductor layer, the method may further include forming a source and a drain and forming a gate on the recess region.

According to the disclosed embodiment, by forming the 2DEG region separated from each other at the lower end and the upper end of the recess region of the first semiconductor layer of the high electron mobility transistor, the threshold voltage of the transistor is easily adjusted according to the spacing between the 2DEG regions. It can reduce the on resistance per unit area.

1 is a diagram illustrating a high electron mobility transistor according to an exemplary embodiment of the present invention.
2 is a view showing a modification of the high electron mobility transistor according to the embodiment of the present invention.
3 is a view showing a modification of the high electron mobility transistor according to the embodiment of the present invention.
4A to 4E are diagrams illustrating a method of manufacturing a high electron mobility transistor according to an embodiment of the present invention.

Hereinafter, a high electron mobility transistor according to an embodiment of the present invention and a method of manufacturing the same will be described in detail with reference to the accompanying drawings. The thicknesses of the layers or regions shown in the figures in this process are somewhat exaggerated for clarity of the description.

1 is a diagram illustrating a high electron mobility transistor according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a high electron mobility transistor according to an exemplary embodiment of the present invention includes a substrate 11, a buffer layer 12 formed on the substrate 11, and a recessed region on the buffer layer 12. The first semiconductor layer 13 may be formed. Second semiconductor layers 15a and 15b may be formed on the lower end and the upper end of the recess region of the first semiconductor layer 13, respectively. The source 17a and the drain 17b may be formed on both sides of the second semiconductor layer 15b, and the first semiconductor layer 13 and the second semiconductor except for the region where the source 17a and the drain 17b are formed. The gate insulating layer 16 may be formed on the layers 15a and 15b. In addition, a gate 18 may be formed on the gate insulating layer 16.

In the high electron mobility transistor shown in FIG. 1, the first semiconductor layer 13 includes a recess region, and the first semiconductor layer 13 has a first region at an interface region with the second semiconductor layers 14a and 14b at the lower and upper ends of the recess region, respectively. The 2DEG region 14a and the second 2DEG region 14b may be formed. The first 2DEG region 14a and the second 2DEG region 14b may be formed except the side of the recess region. According to the distance D between the first 2DEG region 14a and the second 2DEG region 14b, the threshold voltage Vth of the high electron mobility transistor may change, and the first 2DEG region 14a may be changed. The threshold voltage may increase when the distance D between the second 2DEG region 14b is increased.

The substrate 11 can be used without limitation as long as it is a material that can be used as the substrate of the semiconductor device. For example, Si, SiC or sapphire substrate can be used. The substrate 11 may be doped with a predetermined impurity dopant.

The buffer layer 12 is for growth of the first semiconductor layer 13 formed thereon, and the buffer layer 12 is optional. Therefore, the buffer layer 12 may be selected according to the material of the first semiconductor layer 13 thereon. For example, the buffer layer 12 may be formed of AlN or AlGaN.

The first semiconductor layer 13 and the second semiconductor layers 15a and 15b may be formed of a semiconductor material, and may be formed of materials having different bandgap energy. The second semiconductor layers 15a and 15b may be formed of a material having greater polarizability than the first semiconductor layer 11 and may be formed of a material having a greater band gap energy.

The first semiconductor layer 13 may be formed of a III-V semiconductor compound, and may include, for example, GaN, GaAs, InN, InGaN, or AlGaN. The second semiconductor layers 15a and 15b may be formed of AlN, AlGaN, AlInN, AlGaInN or AlGaAs. The second semiconductor layers 15a and 15b may have a multilayer structure formed of a plurality of layers having different Al or In contents from the above materials. The first semiconductor layer 11 may be a channel region and the second semiconductor layer 12 may be a channel supply layer.

The first semiconductor layer 13 and the second semiconductor layers 15a and 15b may be formed of compound semiconductors having different lattice constants, respectively. Heterogeneous of the first semiconductor layer 13 and the second semiconductor layer 15a, 15b in the first semiconductor layer 13 in a region close to the interface between the first semiconductor layer 13 and the second semiconductor layer 15a, 15b. A 2-Dimensional Electron Gas (2DEG) region may be generated by a heterojunction structure. In the high electron mobility transistor according to the exemplary embodiment of the present invention, recess regions are formed in the first semiconductor layer 13, and 2DEG regions 14a and 14b are formed at the bottom and top of the recess regions, respectively. The spacing D of the first 2DEG region 14a and the second 2DEG region 14b may correspond to the depth of the recess region of the first semiconductor layer 13, and the spacing D of the 2DEG regions 14a and 14b. The threshold voltage of the high electron mobility transistor may be determined.

If the first 2DEG region 14a below the recess region of the first semiconductor layer 13 is not formed, the threshold voltage may change according to the gate length, but the on resistance per unit area increases. Can be. However, the high electron mobility transistor according to the embodiment of the present invention forms the first 2DEG region 14a below the recess region of the first semiconductor layer 13, and the recess region of the first semiconductor layer 13. In this case, a metal-insulator-semiconductor (MIS) structure of the gate 18, the gate insulating layer 16, and the first semiconductor layer 13 may be formed, and the on resistance per unit area of the transistor may be prevented from increasing. have.

The gate insulating layer 16 may be formed of an insulating material. For example, the gate insulating layer 16 may be formed of Si oxide, Si nitride, Al oxide, or Hf oxide.

The source 17a, the drain 17b, and the gate 18 may be formed of a conductive material such as a metal, a metal alloy, a conductive metal oxide, or a conductive metal nitride. For example, it may be formed of Au, Ag, Hf, W, Al, indium-tin-oxide (ITO), TiN, TaN or WN.

For reference, the materials of each layer described above may also be used in the members of the same name in FIGS. 2 and 3.

2 is a view showing a modification of the high electron mobility transistor according to the embodiment of the present invention.

Referring to FIG. 2, a high electron mobility transistor includes a substrate 21, a buffer layer 22 including a recess region on the substrate 21, and a first semiconductor layer 23 formed on the buffer layer 22. It may include. The first semiconductor layer 23 may include a recess region corresponding to the recess region of the buffer layer 22, and the second semiconductor layer 23 may be formed on the lower end and the upper end of the recess region of the first semiconductor layer 23, respectively. 25a, 25b) may be formed. The source 27a and the drain 27b may be formed on both sides of the second semiconductor layer 25b, and the first semiconductor layer 23 and the second semiconductor except for the region where the source 27a and the drain 27b are formed. The gate insulating layer 26 may be formed on the surfaces of the layers 25a and 25b. The gate 28 may be formed on the gate insulating layer 26.

The first 2DEG region 24a and the second 2DEG region 24b may be formed in the interface region with the second semiconductor layers 24a and 24b at the lower end and the upper end of the recess region of the first semiconductor layer 23, respectively. have. The distance between the first 2DEG region 24a and the second 2DEG region 24b may correspond to the depth of the recess region of the first semiconductor layer 23, and the first 2DEG region 24a and the second 2DEG region ( Depending on the distance between 24b), the threshold voltage of the high electron mobility transistor may change.

3 is a view showing a modification of the high electron mobility transistor according to the embodiment of the present invention.

Referring to FIG. 3, a high electron mobility transistor includes a substrate 31 including a recess region, a buffer layer 32 formed on the substrate 31, and a first semiconductor layer 33 formed on the buffer layer 32. It may include. The buffer layer 32 and the first semiconductor layer 33 may include a recess region formed in a region corresponding to the recess region of the substrate 31. Second semiconductor layers 35a and 35b may be formed at lower and upper ends of the recessed region of the first semiconductor layer 33. The source 37a and the drain 37b may be formed on both sides of the second semiconductor layer 35b, and the first semiconductor layer 33 and the second semiconductor except for the region where the source 37a and the drain 37b are formed. The gate insulating layer 36 may be formed on the surfaces of the layers 35a and 35b. The gate 38 may be formed on the gate insulating layer 36. The first 2DEG region 34a and the second 2DEG region 34b may be formed in the interface region with the second semiconductor layers 34a and 34b at the lower end and the upper end of the recess region of the first semiconductor layer 33, respectively. have.

1, 2, and 3, recess regions are formed in the first semiconductor layer, and 2DEG regions are formed in the interface region between the second semiconductor layer at the lower end and the upper end of the recess region, respectively. The distance between the 2DEG region of the lower region of the region and the 2DEG region of the upper region may correspond to the depth of the recess region. However, in FIG. 1, a recess region is formed in the first semiconductor layer 13, and in FIG. 2, the recess region is formed to correspond to each other in the buffer layer 22 and the first semiconductor layer 23. The recess structure is formed to correspond to each other on the substrate 31, the buffer layer 32, and the first semiconductor layer 33. Such a difference in structure may vary depending on a manufacturing process, and a recess region may be formed in a substrate, a buffer layer, or a semiconductor layer in a growth process or a previous process of forming a semiconductor layer for forming a 2DEG region.

As described above, according to the exemplary embodiment of the present invention, the high electron mobility transistor forms 2DEG regions separated from each other at the lower end and the upper end of the recess region of the first semiconductor layer to adjust the threshold voltage of the transistor according to the distance between the 2DEG regions. It can reduce the on resistance per unit area.

4A to 4E are diagrams illustrating a method of manufacturing a high electron mobility transistor according to an embodiment of the present invention. Here, the manufacturing method of the high electron mobility transistor shown in FIG. 1 is shown.

Referring to FIG. 4A, the buffer layer 12, the first semiconductor layer 13, and the second semiconductor layer 15 are sequentially formed on the substrate 11. The substrate 11 may be a Si, SiC or sapphire substrate, and the buffer layer 12 may be formed of AlN or AlGaN. The first semiconductor layer 13 may be formed of GaN, and the second semiconductor layer 15 may be formed of AlGaN.

Referring to FIG. 4B, a recess region R1 is formed in the second semiconductor layer 15 and the first semiconductor layer 13 by an etching process. The recess region R1 formed by the etching process may be formed to have a depth of D in the first semiconductor layer 13.

Referring to FIG. 4C, a second semiconductor layer 15a may be formed at the lower end of the recess region R1. Accordingly, the second semiconductor layers 15a and 15b include a second semiconductor layer 15b previously formed at the upper end of the recess region R1 and a second semiconductor layer 15a formed at the lower end of the recess region R1. do. The thickness of the second semiconductor layer 15a formed at the lower end of the recess region R1 is smaller than the depth D of the recess region R1 formed in the first semiconductor layer 13.

For reference, in FIGS. 4A to 4C, after the second semiconductor layer 15 is formed on the first semiconductor layer 13, the recess region R1 is formed by an etching process. After the buffer layer 12 and the first semiconductor layer 13 are formed, a recess region having a predetermined depth D is formed in the first semiconductor layer 13 by an etching process, and then the second semiconductor layers 15a and 15b are formed. ) May be formed at the lower end and the upper end of the recess region of the first semiconductor layer 13.

Referring to FIG. 4D, the gate insulating layer 16 is formed of silicon oxide, silicon nitride, or another insulating material on the surfaces of the first semiconductor layer 13 and the second semiconductor layers 15a and 15b.

As shown in FIG. 4E, after partially removing the gate insulating layer 16 on both sides of the second semiconductor layer 15b, the source 17a and the drain 17b are formed, and the gate 18 is formed on the recess region. To form. The source 17a, the drain 17b, and the gate 18 may be formed of a conductive material, and may be formed of the same material.

In the case of the high electron mobility transistor shown in FIG. 2, after the buffer layer 22 is formed on the substrate 21, the recess region is formed in the buffer layer 22 by an etching process, and then the first semiconductor is formed thereon. And forming the layer 23 and the second semiconductor layers 25a and 25b. In the high electron mobility transistor shown in FIG. 3, after the recess region is formed in the substrate 31 by an etching process, the buffer layer 32, the first semiconductor layer 33, and the second semiconductor are formed thereon. It can be produced, including the step of sequentially forming the layers (35a, 35b).

While a great many have been described in the foregoing description, they should not be construed as limiting the scope of the invention, but rather as examples of embodiments. Accordingly, the scope of the present invention should not be limited by the illustrated embodiments but should be determined by the technical idea described in the claims.

11, 21, 31 ... substrate 12, 22, 32 ... buffer layer
13, 23, 33 ... first semiconductor layer
14a, 14b, 24a, 24b, 34a, 34b ... 2DEG region
15a, 15b, 25a, 25b, 35a, 35b ... second semiconductor layer
16, 26, 36 ... gate insulation 17a, 27a, 37a ... source
17b, 27b, 37b ... drain 18, 28, 38 ... gate

Claims (10)

Board;
A first semiconductor layer formed on the substrate and including a recess region; And
And a second semiconductor layer formed on each of a lower end and an upper end of the recess region of the first semiconductor layer.
And a 2DEG region respectively formed at a lower end and an upper end of the recess region of the first semiconductor layer. The method of claim 1,
A source and a drain formed on both sides of the second semiconductor layer;
A gate insulating layer formed on the first semiconductor layer and the second semiconductor layer except for the region where the source and drain are formed; And
And a gate formed on the gate insulating layer. The method of claim 1,
And a buffer layer formed between the substrate and the first semiconductor layer. The method of claim 1,
The recess region of the first semiconductor layer has a gate, a gate insulating layer, and a metal-insulator-semiconductor (MIS) structure of the first semiconductor layer. The method of claim 1,
And a buffer layer formed between the substrate and the first semiconductor layer, wherein the buffer layer includes a recess region corresponding to a recess region of the first semiconductor layer. The method of claim 1,
And a buffer layer formed between the substrate and the first semiconductor layer, wherein the substrate and the buffer layer include a recess region corresponding to a recess region of the first semiconductor layer. The method of claim 1,
Wherein the first semiconductor layer comprises GaN, GaAs, InN, InGaN or AlGaN. The method of claim 1,
Wherein the second semiconductor layer comprises AlN, AlGaN, AlInN, AlGaInN or AlGaAs. Forming a buffer layer, a first semiconductor layer, and a second semiconductor layer on the substrate;
Forming a recess region in the second semiconductor layer and the first semiconductor layer by an etching process;
And forming a second semiconductor layer at a lower end of the recess region of the first semiconductor layer. The method of claim 9,
Forming a gate insulating layer on surfaces of the first semiconductor layer and the second semiconductor layer; And
Removing a portion of the gate insulating layer on both sides of the second semiconductor layer, forming a source and a drain, and forming a gate on the recess region.
KR1020120086394A 2012-08-07 2012-08-07 High electron mobility transistor and manufacturing method of the same KR20140021110A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140061145A (en) * 2012-11-13 2014-05-21 삼성전자주식회사 High electron mobility transistor and method of manufacturing the same
KR102535264B1 (en) * 2021-12-09 2023-05-26 울산대학교 산학협력단 Method for manufacturing of high electron mobility transistors

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140061145A (en) * 2012-11-13 2014-05-21 삼성전자주식회사 High electron mobility transistor and method of manufacturing the same
KR102535264B1 (en) * 2021-12-09 2023-05-26 울산대학교 산학협력단 Method for manufacturing of high electron mobility transistors

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