KR20140018095A - Error check and correction circuit and memory device - Google Patents

Abstract

The present invention relates to an error check and correction circuit. The error check and correction circuit of the present invention comprises a data storage unit for storing a data line; a syndrome calculation unit for calculating syndrome; an error coefficient calculation unit for calculating the coefficient of an error location searching equation using the syndrome; a latch unit for storing the coefficient; a substitution value calculation unit for calculating a substitution value using the coefficient stored in the latch unit and the address; a ziehen searching unit for outputting an error check signal indicating the existence of errors in each bit of the data line in response to a substitution result for the error location searching equation of the substitution value in the output of the data line; and an error correction unit for outputting data by correcting the errors in response to the error check signal. [Reference numerals] (12) Page buffer; (14) Buffer; (30) Decoder unit; (31_1,31_2,31_3,31_4) Syndrome calculation circuit; (32) Error coefficient calculation unit; (33) Ziehen searching unit; (35_0,35_1,35_2,35_3) Coefficient latch; (36) Substitution value calculation unit; (40) Encoder unit; (41) Parity generation circuit

Description

ERROR CHECK AND CORRECTION CIRCUIT AND MEMORY DEVICE}

The present invention relates to an error detection correction circuit and a memory device.

NAND flash memory is known as one of electrically rewritable nonvolatile semiconductor memories (EEPROM, Electrically, Erasable, and Programmable, Read, Only Memory). A NAND flash memory uses a NAND cell unit (NAND string) in which a plurality of memory cells are connected in series, so that a large chip area can be stored.

In the NAND flash memory, due to the deterioration of the tunnel oxide film due to several rewrites, the storage characteristic of the memory element (memory cell) is degraded during data storage, and the occurrence rate (error rate) of error bits tends to increase. In particular, in the NAND type flash memory, as the capacity of the memory cells becomes larger, that is, the manufacturing process becomes smaller, the error rate tends to increase. Therefore, redundancy data of an Error Correcting Code (ECC) is added to data to be stored, and written into the flash memory as a data string, and data is read based on the redundancy data of the Error Correcting Code (ECC) at the time of reading. By performing the correction, compensation of data when an error bit occurs is performed.

For example, in Patent Document 1, a NAND flash memory having an error detection correction circuit (ECC circuit) is disclosed. In the Chien search unit of the error detection correction circuit described in Patent Document 1, the position of a bit in the received information (data string) is substituted into the error position search equation, and it is detected whether or not an error exists in the bit. At the time of outputting the data string, all addresses are assigned to the Chien search unit from the lowest to the highest. Then, the error correction circuit (error correction unit) corrects the data of the bit when there is an error in each bit, outputs the data after the correction, and outputs the data of the bit as it is without correcting when there is no error.

Japanese Patent Publication No. 2009-100369

However, in the above-described configuration described in Patent Document 1, when a bit of any address in the data string is to be read, the bit output by the error correction circuit is stored once in the buffer memory or the like, and then the address of the bit to be read is It must be supplied in addition to the buffer memory. That is, in the conventional case, in the error detection correction circuit, error correction of data of bits of an arbitrary address is performed until the error bit correction processing for all bits of the data string containing the bits to be read is completed. There is a problem that data after correction cannot be read at high speed.

SUMMARY OF THE INVENTION An object of the present invention is to provide an error detection correction circuit and a memory device capable of performing error correction of data of bits of an arbitrary address in a data string and outputting the data after error correction to the outside at high speed. Is in.

An error detection correction circuit according to an embodiment of the present invention includes a data storage unit for storing a data string; A syndrome calculation unit calculating a syndrome from the data string; An error coefficient calculator for calculating coefficients of an error location search equation using the syndrome; A latch unit for storing the coefficients; A substitution value calculator for calculating a substitution value substituted into the error location search equation using an address indicating a location of the data string and a coefficient stored in the latch unit; A Chien search unit for outputting an error detection signal indicating whether there is an error for each bit of the data string in response to a substitution result for the error position search equation of the substitution value when the data string is output; And an error correction unit for correcting and outputting an error of data of bits of the data string in response to the error detection signal.

In an embodiment, the data column includes a plurality of data columns, and the latch unit is provided to correspond to each of the plurality of data columns.

In an embodiment, a memory device may include an error detection correction circuit, and the error detection correction circuit may include: a data storage configured to store a data string; A syndrome calculation unit calculating a syndrome from the data string; An error coefficient calculator for calculating coefficients of an error location search equation using the syndrome; A latch unit for storing the coefficients; A substitution value calculator for calculating a substitution value substituted into the air position search equation using an address indicating a location of the data string and a coefficient stored in the latch unit; A Chien search unit for outputting an error detection signal indicating whether there is an error for each bit of the data string in response to a substitution result for the error position search equation of the substitution value when the data string is output; And an error correction unit for correcting and outputting an error of data of a bit of the data string in response to the error detection signal, wherein the data storage unit is a circuit which stores a data string read from a storage element, wherein the address is the memory. A column address indicating the position of the column of the device.

The error detection correction circuit of the present invention includes a latch unit for storing coefficients of the error position search equation, and an substitution value calculation unit for calculating substitution values of error position search equations such as coefficients and bit positions. Therefore, when reading the data, if the address of the bit to be read is inputted into the substitution value calculation unit, the Chien search unit detects whether or not an error exists in the data of the corresponding bit. If there is an error in the data of the corresponding bit, the error correction unit corrects the data of the bit, outputs the data of the corrected bit, and if there is no error, outputs the data of the bit as it is. Therefore, an error detection correction circuit and a memory device are provided for performing error correction on data of bits of any address in the data string and reading the data after the correction at high speed.

1 is a block diagram illustrating a NAND flash memory as a nonvolatile semiconductor memory device.
2 shows a configuration example of an error detection correction circuit.
3 shows an example of the configuration of the Chien search unit.
4 shows an example of the configuration of the substitution value calculation unit.
5 shows a configuration example of an error detection correction circuit.
6 is a diagram for explaining a comparison of error detection correction circuits.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention. .

FIG. 1 is a block diagram illustrating a NAND flash memory as a nonvolatile semiconductor memory device 10 according to an embodiment of the present invention. The nonvolatile semiconductor memory device 10 includes a memory cell array 11, a page buffer 12, an error detection correction circuit 13, a buffer 14, an I / O pad 15, a control circuit 16, and an address. Decoder 17 and row and block decoder 18 are included.

In the memory cell array 11, a plurality of stacked gate structure transistors, that is, NAND cells electrically connected to non-volatile memory cells (memory elements) that are electrically connected in series in a column direction (column direction) and provided for each bit line The string includes a plurality of blocks arranged in a row direction (array direction of bit lines). A plurality of blocks are arranged in the wiring direction of the bit line. The blocks are set in units of erasing data of the memory cells. In each block, a word line orthogonal to the bit line is connected to the gate of each of the nonvolatile memory cells arranged in the same row. The range of a nonvolatile memory cell selected by one word line is a page which is a unit of program and read.

The page buffer 12 includes a page buffer circuit provided for each bit line in order to program and read data in page units. Each page buffer circuit of the page buffer 12 includes a latch circuit connected to each bit line and used as a sense amplifier circuit for amplifying and determining the potential of the connected bit line.

The page buffer 12 (data storage section) is a cell that is data (data string) stored in memory cells of one page of the memory cell array 11 during a data read operation of the nonvolatile semiconductor memory device 10. The data Cell # Data is received, and the received data is amplified and output to the error detection correction circuit 13. On the other hand, the page buffer 12 stores the data supplied from the error detection and correction circuit 13 in the internal latch circuit during the data write (program) operation of the nonvolatile semiconductor memory device 10, and verifies the operation. While executing, all data is written into the memory cells of one page as code data Code # Data.

The code data Code_Data includes parity data Parity generated by the error detection correction circuit 13. For example, in the example of an error correction system that performs 4 bit (bit) correction using a BCH code for data having an information length of 512 bytes, one page is 2 K (= 2048) bytes, that is, 16 k ( 16384) memory cells each storing bits of normal data and memory cells each storing 208 bits of parity data. That is, the cell data Cell # Data and the code data Code # Data are composed of (16k + 208) bits. Further, for example, one page is divided into four sectors in units of correction of the error detection and correction circuit 13. That is, the data corresponding to one sector is composed of 512 bytes (= 4096 bits) of normal data and 52 bits of parity data.

In embodiments of the present invention, access from outside the memory is performed by entering a column address Y [13: 0] into the memory. Parity data is internal data added for correction of data and is not directly accessed from the outside.

In the data read operation of the nonvolatile semiconductor memory device 10, the error detection correction circuit 13 processes data read from the page buffer 12 for each sector to calculate the coefficient of the error position detection polynomial, and calculates the result. Latch and keep it inside. In addition, the error detection correction circuit 13 corrects an error of data of bits whose position is indicated by a column address during a read operation, and externally corrects the data as corrected data through the I / O pad 15. Will output In addition, an input / output circuit is provided between the input / output pad 15 and the error detection correction circuit 13, and data can be output to the outside through the input / output circuit.

In addition, the error detection correction circuit 13 receives, via the buffer 14, information data (Information_Data) input from the I / O pad 15 during the data write operation of the nonvolatile semiconductor memory device 10. do. The error detection correction circuit 13 generates parity data from the received information data, and sends the received information data and the parity data to the page buffer 12. Output The page buffer 12 writes the received data as code data to memory cells connected to the selected page.

The control circuit 16 inputs various control signals to perform operations such as programming, reading, and erasing data and verifying operations of nonvolatile memory cells. For example, the control signal includes an external clock signal, a chip enable signal (/ CE), a read enable signal (/ RE), a program enable signal (WE), a command latch enable signal (CLE), and an address latch enable. Signal ALE, write prevention signal / WP, and the like.

The control circuit 16 outputs an internal control signal to each circuit in response to the operation mode indicated by the control signal and the command data input from the I / O pad 15. For example, the control circuit 16 responds to the command latch enable signal CLE from the low (L) level to the high (H) level at the first start of the program enable signal (/ WE), The command data is read from the I / O pad 15 and stored in an internal register.

The address decoder 17 holds an address (row address, block address, column address) input from the I / O pad 15 based on an internal control signal from the control circuit 16. In addition, the address decoder 17 transfers the held address to the row and block decoder 18, the page buffer 12, and the error detection correction circuit 13 based on an internal control signal from the control circuit 16. Output

For example, the control circuit 16 may respond to the address latch enable signal ALE from the low (L) level to the high (H) level at the first start of the program enable signal / WE. The address is read from the / O pad 15 and held in an internal register of the address decoder 17.

The row and block decoder 18 selects the block and the word line of the memory cell array 11 in response to the row address and the block address held and output by the address decoder 17 to select one page of memory cells. Choose. In addition, the address decoder 17 selects the bit line and the page buffer 12 of the memory cell array 11 in response to the column address held therein.

In an embodiment of the present invention, in a data read operation, cell data stored in the page buffer 12 is transmitted to the error detection correction circuit 13 so that the coefficient of the error position search equation is calculated for each sector. Then, in response to the coefficient and the column address calculated for each sector, it is detected whether there is an error in the data of the bit whose position is specified by the column address, that is, the data (16 bits) of the memory cell, and if there is an error, it is corrected and corrected. It is output to the I / O pad 15 as (Corrected Data). Details will be described later.

In the data write operation, cell data stored in the page buffer 12 is transferred to the buffer 14. The buffer 14 may be, for example, static random access memory (SRAM).

In the buffer 14, data of a portion of the cell data corresponding to the input column address may be updated with information from the I / O pad 15. In the error detection correction circuit 13, parity data corresponding to data corresponding to one correction unit including the data after the update of the buffer 14 is calculated. The encoded data including the parity data is written to the selected page through the page buffer 12 as code data.

2 shows an example of the configuration of the error detection correction circuit 13. In the embodiment of the present invention, an example of the ECC circuit using the BCH code (Bose-Chaudhuri Hocquenghem code) as the error detection correction circuit (hereinafter, ECC circuit) 13 is described. The ECC circuit is a block code using a galloche operation represented by the BCH code. Modifications of the BCH code, for example, a Hamming code and a Reed-Solomon code may be used. In the following description, an information data length of 512 bytes (= 4096 bits) is a correction unit, that is, a BCH code in which data of a quarter of a cell is a correction unit, and 4 bits of data can be corrected in each correction unit. The ECC circuit used is described.

The error detection and correction circuit 13 includes a decoder unit 30 for decoding data and an encoder unit 40 for generating correction parity data Parity and adding correction parity data Parity to data written in a cell. Include.

The encoder unit 40 includes a parity generation circuit 41. The parity generating circuit 41 generates parity data obtained by dividing (ie, dividing) the information data written in the buffer 14 by the generation polynomial. The parity generating circuit 41 adds the parity data generated to the information data to the page buffer 12. The output data is code data (Code Data) written in the selected page when data is written in the nonvolatile semiconductor memory device 10. In addition, an embodiment of the present invention is characterized in that the error detection and correction circuit 13 performs data correction processing at high speed when reading data from the nonvolatile semiconductor memory device 10. Hereinafter, the decoder unit 30 will be described in detail.

The decoder unit 30 includes the syndrome calculator 31, the error coefficient calculator 32, the Chien search unit 33, the error corrector 34, the latch unit 35, and the substitution value calculator 36. Include.

When reading data from the nonvolatile semiconductor memory device 10, the syndrome calculation unit 31 receives the cell data read from the page buffer 12 for each sector as code data and independently receives the received code data. Calculate the syndrome by dividing (divide) in the minimum polynomial of. There are four independent minimum polynomials used in the BCH code capable of error correction of four bits of data. The syndrome calculation unit 31 includes four syndrome calculation circuits 31_1 to 31_4 corresponding to four minimum polynomials. The syndrome calculation circuits 31_1 to 31_4 calculate syndromes S1, S3, S5, and S7, respectively.

The error coefficient calculation unit 32 calculates the coefficients e4, e3, e2, e1, e0 of the error position search equation for each sector using the syndromes S1, S3, S5, and S7. The coefficients (e4, e3, e2, e1, e0) are obtained by the Chien search unit 33 of the error position search equation (Λ (x) = e4x ^ 4 + e3x ^ 3 + e2x ^ 2 + e1x ^ 1 + e0). Coefficient. The error position search equation Λ (x) is used by the Chien search unit 33 when searching for errors in the bits read from the page buffer 12 for each sector.

Here, in order to explain the error position search equation, the configuration and operation of the Chien search unit 33 are described. 3 shows an example of the configuration of the Chien search unit 33. The Chien search unit 33 includes four selectors, five flip flops, 64 integer multiplication circuits, 16 exclusive OR circuits, and 16 logic inversion circuits. As shown in FIG. 3, the four selectors are selectors 301, 302, 303, 304 and the five flip flops are flip flops 310, 311, 312, 313, 314. The 64 integer multiplication circuits are integer multiplication circuits 321_1 to 321_16, 322_1 to 322_16, 323_1 to 323_16, and 324_1 to 324_16. The 16 exclusive OR circuits are exclusive OR circuits 330_1, 330_2, 330_15, 330_16, and the 16 logical inversion circuits are logic inverting circuits 340_1, 340_2, 340_15, 340_16. .

X of "e1x, e1x ^ 2, e1x ^ 3, e1x ^ 4" respectively input to the selectors 301-304 is a value indicating the position of the sign data, that is, the cell data stored in the page buffer. . A parity bit (52 bits) is added to the lowest level of the column in the cell data. Specifically, the following value is input as x. That is, since one page contains 16 k bits of data (except parity data), the column address indicating the position of the bit line is a 14-bit column address (Y [13: 0]). Among these, the column address (Y [13: 4]) of the upper 10 bits is defined as "Y = a13 × 2 ^ 13 + a12 × 2 ^ 12 + ... + a5 × 2 ^ 5 + a4 × 2 ^ 4". In the decimal notation, since the embodiment of the present invention performs error correction of the data of bits in units of 16 bits, except "a13 x 2 ^ 13 + a12 x 2 ^ 12 + except the parity bit (52 bits) as x. + A5 x 2 ^ 5 + a4 x 2 ^ 4 + 52 "(= alpha ^ j) is input.

Here, i = 0-15 (integer), and "(alpha) ^ (i + j)" is a circle | round | yen of galoache (GF (2 ^ m)), and is the minimum value of column address Y (13: 0), ie, a column. It is a value indicating the position of the column address from the case where all the bits of the address are '0', that is, the value indicating the position of the (jx16 + i + 1) th bit line.

Since "α ^ (i + j) = α ^ i × α ^ j", the error position search equation (Λ (x) = e4x ^ 4 + e3x ^ 3 + e2x ^ 2 + e1x ^ 1 + e0 "to" x = α By substituting ^ (i + j) ", the error position search equation (Λ (x)) develops as in equation (1).

Here, the selector 301 obtains e1 (α ^ j), and when this becomes an integer multiple of (α ^ 1) ^ i times in the range of i = 0-15, the error position search equation (Λ (x)) "X = α ^ (i + j)", i.e., x representing the position of the (jx16 + i) th bit line, can be obtained. Similarly, selector 302 obtains e2 (α ^ j), and if it is an integer multiple of (α ^ 2) ^ i times in the range of i = 0-15, then the error position search equation (Λ (x)) "x = α ^ (i + j)", i.e., x indicating the position of the (jx16 + i) -th bit line substituted in x ^ 2 can be obtained. Similarly, selector 303 obtains e3 (α ^ j) and if it is an integer multiple of (α ^ 3) ^ i times in the range of i = 0-15, then the error location search equation (Λ (x)) x "X = α ^ (i + j)" assigned to ^ 3, i.e., x indicating the position of the (jx16 + i) th bit line can be obtained. Similarly, selector 304 obtains e4 (α ^ j) and if it is an integer multiple of (α ^ 4) ^ i times in the range of i = 0-15, then the error location search equation (Λ (x)) "x = α ^ (i + j)", i.e., x representing the position of the (jx16 + i) th bit line, substituted into x ^ 4 can be obtained.

Accordingly, the control signal SEL for changing the input of the selector is transmitted from the control circuit 16 to each of the selectors 301 to 304. When the control signal SEL reads data from the nonvolatile semiconductor memory device 10, after the address decoder 17 latches the column address, the control circuit 16 causes the control circuit 16 to go from the low level to the high level, for example. Is a control signal. When the control signal SEL becomes H level with respect to the selectors 301-304, the selectors 301-304 receive "e1x, e1x ^ 2, e1x ^ 3, e1x ^ 4", respectively, The value is stored in flip flops 311 314 connected to the rear end. Also, coefficient e0 is stored in flip flop 310.

16 integer multiplication circuits are connected in series at the rear ends of the flip flops 311 to 314. At the rear end of the flip flop 311, integer multiplication circuits 321_1 to 321_16 that multiply and output an input value by an integer α are connected in series. At the rear end of the flip flop 312, integer multiplication circuits 322_1 to 322_16 multiplying and outputting the input value by the integer α ^ 2 are connected in series. At the rear end of the flip-flop 313, integer multiplication circuits 323_1 to 323_16 multiplying an input value by an integer α ^ 3 and outputting the same are connected in series. At the rear end of the flip flop 314, integer multiplication circuits 324_1 to 324_16 multiplying an input value by an integer α ^ 4 and outputting the same are connected in series.

The exclusive OR circuit 330_1 calculates an exclusive OR of the outputs of the flip flops 310 to 314 and outputs the exclusive OR to the logic inversion circuit 340_1 at a later stage. The logic inversion circuit 340_1 logically inverts the operation result of the exclusive OR circuit 330_1 and outputs the error detection signal Error <0> to the error correction unit 34. That is, in the exclusive OR circuit 330_1, the error position search equation (Λ (x) = e4x ^ 4 + e3x ^ 3 + e2x ^ 2 + e1x ^ 1 + e0) is "x = α ^ (i + j)" (i When the value of the error position search equation Λ (x) is 0 when the value is substituted, the error detection signal Error <0> becomes H level. On the other hand, when the value of the error position search equation Λ (x) is not 0, the error detection signal Error <0> becomes L level.

The error correction unit 34 includes 16 exclusive logical operation circuits 34_i (see FIG. 2, i = 0 to 15) according to an embodiment of the present invention. The exclusive OR operation circuit 34_i is the (j × 16 + 0) th of the cell detection data stored in the error detection signal Error <0> and the page buffer 12 during the read operation. Receive a bit at the position of the bit line. That is, if the error detection signal Error <0> is at the H level, the exclusive OR operation circuit 340 inverts the logical value (0 or 1) of the data of the bit at the position of the (jx16 + 0) th bit line and corrects the corrective agent. Output as one bit of corrected data. On the other hand, if the error detection signal Error <0> is at the L level, the exclusive OR calculation circuit 34_0 corrects the logical value of the data of the bit at the position of the (jx16 + 0) th bit line as it is, without correcting it. Output as one bit of (Corrected Data).

Similarly, the exclusive OR circuit 330_i corresponding to "i = 1-15" is exclusive of the outputs of the integer multiplication circuit 321_i, the integer multiplication circuit 322_i, the integer multiplication circuit 323_i, and the integer multiplication circuit 323_i. The OR is calculated and output to the logic inversion circuit 340_i at the next stage. The logic inversion circuit 340_i performs a logic inversion on the operation result of the exclusive OR circuit 330_i and outputs it to the error correction unit 34 as an error detection signal Error <i>. That is, in the exclusive OR circuit 330_i, the error position search equation (Λ (x) = e4x ^ 4 + e3x ^ 3 + e2x ^ 2 + e1x ^ 1 + e0) is "x = α ^ (i + j)" (i When the values of the error position search equation Λ (x) are 0 when each of = 1 to 15) is substituted, the error detection signal Error <i> becomes H level. On the other hand, when the value of the error position search equation Λ (x) is not 0, the error detection signal Error <i> becomes L level.

In the error correcting unit 34, the exclusive OR operation circuit 34_i stores the (j × 16 + i) th of the cell detection data stored in the error detection signal Error <i> and the page buffer 12 during a read operation. Receives a bit at the position of the bit line. Each of the exclusive OR circuits 34_i (i = 1 to 15) inverts the logical value of the data of the bit at the position of the (j × 16 + i) th bit line when the error detection signal Error <i> is at the H level. Is output as one bit of corrected data. On the other hand, each of the exclusive OR circuit 34_i does not correct the logical value of the data of the bit at the position of the (j × 16 + i) th bit line as it is, if the error detection signal Error <i> is at the L level. It outputs as 1 bit of corrected data.

By the way, in a NAND flash memory having no built-in ECC circuit, when one read command, i.e., a command for reading data, is input, data corresponding to one page is read from the memory cell into the page buffer 12. After the first column address, the data stored in the page buffer 12 may be continuously read in synchronization with the read enable signal / RE.

In order to enable the same reading in the nonvolatile semiconductor memory device 10 having the ECC circuit, the following processing is required. That is, the syndrome calculation unit 31 calculates the syndrome using data read from the memory cell (data stored in the page buffer 12), and the coefficient calculation unit 32 calculates the error coefficient. Then, as described above, the column address of the input of the selector of the Chien search unit 33 is changed from, for example, the lowest, and it is checked whether the error position search equation? (X) becomes zero. According to this check result, if there is an error in the data read from the page buffer 12, the error is corrected, and the corrected data is output.

However, NAND flash memories that do not incorporate ECC circuits have a mode of access using arbitrary column addresses. When the nonvolatile semiconductor memory device 10 has a mode for accessing using any column address, following the data reading from the memory cell to the page buffer 12, the error correction processing of data for one page is completed. In addition, a process of storing the correction data after the process is required.

Since the nonvolatile semiconductor memory device 10 includes a buffer 14 (for example, SRAM, Static Random Access Memory) separate from the page buffer 12, the nonvolatile semiconductor memory device 10 stores all the corrected data in the buffer 14, After storage, any column address may be used (or input) to output the corrected data to the I / O pad 15. Alternatively, by a circuit design, a method of reading data from the page buffer 12 after storing the corrected data in the page buffer 12 instead of the buffer 14 may be considered.

As described above, in the case where the nonvolatile semiconductor memory device 10 having the ECC circuit is built in and has an access mode for inputting an arbitrary column address, an error correction process for one page of data is completed, and an arbitrary column is provided. The time until the address is input and the data of the memory cell at the corresponding position is read (hereinafter, 1st access overhead) becomes long.

The nonvolatile semiconductor memory device 10 includes a latch unit 35 and a substitution value calculation unit 36 for shortening the first access overhead and enabling random access equivalent to that of a NAND flash memory having no built-in ECC circuit. Include.

The latch unit 35 latches the coefficients e4, e3, e2, e1, e0 of the error position search equation for each sector which is a unit of ECC processing of one page. The coefficient latch 35_0 includes coefficients e4, e3, e2, e1, e0 of the error position search equation calculated from the data of the sector 0 (512 bytes of data) and the parity data corresponding to the sector 0. Save it. The upper two-bit column address Y [13:12] of the column address Y [13: 0] indicating the position of the memory cell holding the data of the sector 0 is the column address Y. [13:12] = (0, 0)).

The coefficient latch 35_1 also includes coefficients e4, e3, e2, e1, e0 of the error position search equation calculated from the data of the sector 1 (512 bytes of data) and the parity data corresponding to the sector 1. Save). Further, the column address Y [13:12 of the upper two bits of the column address Y [13: 0] indicating the position of the memory cell holding the data of the sector 1 is the column address Y [13: 12] = (0, 1) ". The coefficient latch 35_2 is a coefficient of the error position search equation calculated from the data of the sector 2 (512 bytes of data) and the parity data corresponding to the sector 2; (E4, e3, e2, e1, e0) The upper two bits of the column address (Y [13: 0]) indicating the position of the memory cell holding the data of the sector 2 are stored. Y [13:12] is represented by the column address Y [13:12] = (1, 0).

The coefficient latch 35_3 selects the coefficients e4, e3, e2, e1, e0 of the error position search equation calculated from the data of the sector 3 (512 bytes of data) and the parity data corresponding to the sector 3. Save it. The column address Y [13:12] of the upper two bits of the column address Y [13: 0] indicating the position of the memory cell holding the data of the sector 3 is the column address Y [13:12]. ] = (1, 1)).

4 shows an example of the configuration of the substitution value calculator 36. The substitution calculator 36 includes eight selectors, thirteen multiplication circuits, and two square calculation circuits.

As shown in FIG. 4, the eight selectors are selectors 401, 402, 403, 404, 405, 406, 407, 408. The thirteen multiplication circuits are the multiplication circuits 411, 412, 413, 414, 421, 422, 431, 441, 442, 461, 462, 463, 464. Also, the two square calculation circuits are square calculation circuits 451 and 452.

Each selector, as "j = 4-12", receives a value of 2 ^ j power of α and 1, selects one of the received values in response to the column address signal Yj, and selects the selected value at the rear end. Output to the multiplication circuit. The value of the 2 ^ j power of α indicates the (2 ^ j + 52) th position of the sign data substituted into the above-described error position search equation (Λ (x)). The (2 ^ j + 52) th value of the sign data indicates the position of the (2 ^ j + 52) th bit line among the bit lines including bit lines corresponding to parity bits. The column address signal Yj is one bit Y [j] of the column addresses Y [13: 0].

Each selector selects a value of the 2 ^ j power of α when the received column address signal Yj is at the H level, that is, "Y [j] = 1". On the other hand, each selector selects '1' when the received column address signal Yj is at L level, that is, "Y [j] = 0".

For example, when one bit of Y [4] of the top 10 bits of column address ([13: 4]) is '1' and the remaining nine bits of Y [13: 5] are all '0', the selector ( 401 selects 'α ^ 16', and other selectors 402-408 select '1'. In the following, connection and operation of another circuit of the substitution value calculating section 36 are described, and inputting "x = α ^ (16 + 52)" indicating the (24 + 52) th position of the sign data to the Chien search section 33. An example is described.

The multiplication circuit 411 is connected to the output terminal of the selector 401 and the output terminal of the selector 402 to multiply the output values of the selectors, and outputs the result of the multiplication to the first input terminal of the subsequent multiplication circuit 421. In the above example, the multiplication result is α ^ 16, and α ^ 16 is input to the first input terminal of the multiplication circuit 421.

The multiplication circuit 412 is connected to the output terminal of the selector 403 and the output terminal of the selector 404 to multiply the output values of the selectors, and outputs the result of the multiplication to the second input terminal of the subsequent multiplication circuit 421. In the above example, the multiplication result is 1, and 1 is input to the second input terminal of the multiplication circuit 421.

The multiplication circuit 413 is connected to the output terminal of the selector 405 and the output terminal of the selector 406 to multiply the output values of the selectors, and outputs the result of the multiplication to the first input terminal of the subsequent multiplication circuit 422. In the above-described example, the multiplication result is 1, and 1 is input to the first input terminal of the multiplication circuit 422.

The multiplication circuit 414 is connected to the output terminal of the selector 407 and the output terminal of the selector 408 to multiply the output values of the selectors, and outputs the result of the multiplication to the second input terminal of the subsequent multiplication circuit 422. In the above-described example, the multiplication result is 1, and 1 is input to the second input terminal of the multiplication circuit 422.

The multiplication circuit 421 is connected to the output terminal of the multiplication circuit 411 and the output terminal of the multiplication circuit 412 to multiply the output values of the multiplication circuits, and the result of the multiplication to the first input terminal of the subsequent multiplication circuit 431. Output In the above-described example, the multiplication result is α ^ 16, and α ^ 16 is input to the first input terminal of the multiplication circuit 431.

The multiplication circuit 422 is connected to the output terminal of the multiplication circuit 413 and the output terminal of the multiplication circuit 414 to multiply the output values of the multiplication circuits, and the result of the multiplication to the second input terminal of the subsequent multiplication circuit 431. Output In the above-described example, the multiplication result is 1, and 1 is input to the second input terminal of the multiplication circuit 422.

The multiplication circuit 431 is connected to the output terminal of the multiplication circuit 421 and the output terminal of the multiplication circuit 422 to multiply the output values of the multiplication circuits, and the result of the multiplication to the first input terminal of the subsequent multiplication circuit 441. Output In the above-described example, the multiplication result is α ^ 16, and α ^ 16 is input to the first input terminal of the multiplication circuit 441.

In the multiplication circuit 441, the first input terminal is connected to the output terminal of the multiplication circuit 431 to receive the output value of the multiplication circuit 431, and the second input terminal receives the fixed value α ^ 52. . α ^ 52 is the position of the bit line from which the code data, i.e., the normal data next to the parity bit (52 bits) among the cell data stored in the page buffer 12, is read out, that is, the column address Y [13: 0] = 0) indicates the position of the bit line where normal data is read.

The multiplication circuit 441 multiplies the output value of the multiplication circuit 431 and α ^ 52, and multiplies the result of the multiplication by the input terminal of the square-square calculation circuit 451, the first input terminal of the multiplication circuit 442, and the multiplication circuit. It outputs to the 1st input terminal of 461. In the above-described example, the result of the multiplication is "α ^ (16 + 52)", the input terminal of the square operation circuit 451, the first input terminal of the multiplication circuit 442, and the first of the multiplication circuit 461. "Α ^ (16 + 52)" is input to an input terminal.

The square operation circuit 451 is connected to the output terminal of the multiplication circuit 441 to square the output value of the multiplication circuit 441, and the square result of the input terminal of the square operation circuit 452 of the subsequent stage, the multiplication circuit 442 of the Output to the second input terminal and the first input terminal of the multiplication circuit 462. In the above-described example, the square result is "α ^ ((16 + 52) x 2)", the input terminal of the square operation circuit 452, the second input terminal of the multiplication circuit 442, and the multiplication circuit 462. "(Alpha) ((16 + 52) * 2)" is input into the 1st input terminal of the terminal.

The multiplication circuit 442 is connected to the output terminal of the multiplication circuit 441 and the output terminal of the square calculation circuit 451 to multiply the output values of the multiplication circuit 441 and the square calculation circuit 451, and multiply the result of the multiplication at a later stage. It outputs to the 1st input terminal of the circuit 463. In the above-described example, the multiplication result is "α ^ ((16 + 52) x3)", and "α ^ ((16 + 52) x)" 3 is input to the first input terminal of the multiplication circuit 463.

The square calculation circuit 452 is connected to the output terminal of the square calculation circuit 451 to square the output value of the square calculation circuit 451, and outputs the square result to the first input terminal of the multiplication circuit 464 at the rear stage. . In the above-described example, the square result is "α ^ ((16 + 52) x4)", and "α ^ ((16 + 52) x4)" is input to the first input terminal of the multiplication circuit 464.

The multiplication circuit 461 is connected to the output terminal of the coefficient latch of the latch unit 35 and the output terminal of the multiplication circuit 441 to multiply the output values of the coefficient latch and the multiplication circuit 441, and multiply the result of the multiplication by "e1x". Output to search section 33. In the above-described example, the coefficient latch is the coefficient latch 35_0, the error coefficient e1 is input to the second input terminal of the multiplication circuit 461, and the multiplication result of the multiplication circuit 461 is "e1 (α ^). (16 + 52)) ". Therefore, "e1 (α ^ (16 + 52))" is input to the selector 301 of the Chien search unit 33, that is, "(α ^ (16 + 52))" is input as x.

The multiplication circuit 462 is connected to the output terminal of the coefficient latch of the latch unit 35 and the output terminal of the square calculation circuit 451 to multiply the output values of the coefficient latch and the square calculation circuit 451 and multiply the result by "e2x". As output to the Chien search unit 33 as. In the above-described example, the coefficient latch is the coefficient latch 35_0 and the error coefficient e2 is input to the second input terminal of the multiplication circuit 462, and the multiplication result of the multiplication circuit 462 is "e2 (α ^ ( (16 + 52) × 2)) ". Therefore, "e2 (α ^ (16 + 52)) ^ 2" is input to the selector 302 of the Chien search unit 33, that is, "(α ^ (16 + 52))" as x.

The multiplication circuit 463 is connected to the output terminal of the coefficient latch of the latch unit 35 and the output terminal of the multiplication circuit 442 to multiply the output values of the coefficient latch and the multiplication circuit 442 and multiply the multiplication result as "e3x". Output to search section 33. In the above-described example, the coefficient latch is the coefficient latch 35_0, the error coefficient e3 is input to the second input terminal of the multiplication circuit 463, and the multiplication result of the multiplication circuit 463 is "e3 (α ^). ((16 + 52) x 3)) ". Therefore, "e3 (? ^ (16 + 52)) ^ 3" is input to the selector 303 of the Chien search unit 33, that is, "(? ^ (16 + 52))" as x.

The multiplication circuit 464 is connected to the output terminal of the coefficient latch of the latch unit 35 and the output terminal of the square calculation circuit 452 to multiply the output values of the coefficient latch and square calculation circuit 452 and multiply the result by "e4x". As output to the Chien search unit 33 as. In the above-described example, the coefficient latch is the coefficient latch 35_0, the error coefficient e4 is input to the second input terminal of the multiplication circuit 463, and the multiplication result of the multiplication circuit 464 is " e4 (α ^ ((16 + 52) × 4)) ”. Therefore, "e4 (alpha ^ (16 + 52)) ^ 4" is input to the selector 304 of the Chien search unit 33, that is, "(α ^ (16 + 52))" as x.

As described above, the substitution value calculation unit 36 calculates an address indicating the position of the data column (column address Y) and a coefficient stored by the latch unit 35 (coefficients e1 to e4 of the error position search equation). Using this, the substitution value x (x = alpha (16 + 52) in the above-described example) is calculated to be substituted into the error position search equation Λ (x).

Therefore, when error data for each sector is stored in the latch unit 35 based on data of one page and parity data stored in the page buffer 12 when data is read from the memory cell, the error coefficients and the column address ( The substitution value x substituted into the error position search equation Λ (x) can be calculated according to Y [13: 4]).

The Chien search unit 33, when the substitution value x is input, as described above, 16 bits having the substitution value x as an initial value (in the above-mentioned example, "x = α ^ (16 + 52), α ^). (17 + 52), α ^ (18 + 52), ..., 16 bits of α ^ (30 + 52), α ^ (31 + 52) ", and check whether the error position search equation (Λ (x)) becomes zero. . In addition, the Chien search unit 33 outputs error detection signals ERR <0> to ERR <15> in response to the check result.

The error correction unit 34 receives the data of the memory cell at the position indicated by the column address by the address decoder 17 inputting the column address to the page buffer 12. The error correction unit 34 corrects the received data in response to the error detection signal output by the Chien search unit 33 and outputs the corrected data by error correction in the case of the error data. Outputs

Next, in the nonvolatile semiconductor memory device 10 including the error detection and correction circuit 13 having the latch unit 35 and the substitution value calculation unit 36 described above, the delay time of the ECC processing (first access over) The effect on the shortening of the head) is explained with reference to the drawings.

5 shows an example of the configuration of the error detection correction circuit 13a. 6 is a diagram for explaining and comparing the error detection correction circuit 13 and the error detection correction circuit 13a.

In FIG. 5, the same parts as in FIG. 2 are denoted by the same numerals, and detailed description thereof is omitted.

The error detection correction circuit 13a shown in FIG. 5 is different from the error detection correction circuit 13 shown in FIG. 2 and does not include the latch unit 35 and the substitution value calculation unit 36. In addition, since the error detection and correction circuit 13a has a configuration that outputs the output result of the error correction unit 34 to the I / O pad 15 as corrected data through the buffer 14, an error is generated. It is different from the detection correction circuit 13.

In the following, with reference to FIG. 6, the first access overhead of each of the error detection correction circuit 13 and the error detection correction circuit 13a is described.

In the error detection correction circuit 13a, the number of bits of the decoded data of one sector is the sum of the information bits 4096 bits (= 512 k bytes) and the parity bits 52 bits (= column address x 13 bits x 4). Calculating this data in batches is not practical in terms of increasing circuit size. Therefore, the syndrome calculation unit 31 performs calculation in units of 64 bits.

Assuming that the period of the clock signal as a reference for the calculation is 40 ns, the calculation time of each syndrome calculation circuit of the syndrome calculation unit 31 is equal to the clock number clk of "(4096 + 52) / 64 x 65 clk". It is required and "40 ns x 65 clk = 2.6 microseconds (microsecond)".

In addition, each of the syndrome calculation circuits of the syndrome calculation unit 31 is " 40 ns × 20 clk " to calculate a solution of the quadratic equation (coefficients e4, e3, e2, e1, and e0 of the error location search equation). = 0. 8 microseconds ". In addition, the Chien search unit 33 determines the presence or absence of an error by collectively 16 bits as described above. The calculation time required for this determination requires a clock number clk of "(4096 + 52) / 16x260 clk", and is "40 ns x 260 clk = 10.4 mus". The error correction unit 34 corrects the input data simultaneously with the determination of the Chien search unit 33, that is, by using an error detection signal, so that no additional calculation time is required.

In other words, the time required for the ECC processing is the sum of the above-described calculation times and is about "2.6 microseconds + 0.8 micros + 10 micros = 13.8 microseconds" for about 512 bytes of one sector. Fig. 6A shows ECC processing in the order of sector 0 (Sector <0>), sector 1 (Sector <1>), sector 2 (Sector <2>), and sector 3 (Sector <3>) from time t0. To show The syndrome calculation circuit 31_1 of the syndrome calculation unit 31 requires 2. 6 s to calculate the sum of the syndromes (Partial Syndorome). Then, the error coefficient calculation unit 32 of the next stage needs 0.8 µs to calculate the coefficients e4, e3, e2, e1, and e0 of the error position search equation. The Chien search part 33 of the next stage requires 10. 4 microseconds for correction of the input data. Also. Since the time required for writing the buffer 14 (Data Out to SRAM) is short, it is assumed that it is included in 10 .4 μs.

The above ECC processing is also performed for sector 2, sector 3, and sector 4, and ends at time t1, which has elapsed time of 55. 2 s from the start of ECC processing. That is, inputting an arbitrary column address and reading the data of the bit indicated by the column address from the outside cannot be possible without waiting until the data after correction of all the cells of one page is written in the buffer 14. The time until the correction data of all the cells of one page is written into the buffer 14 is 55. 2 s, which is the first access overhead, which is almost twice that of the NAND flash memory without ECC circuitry. To this.

On the other hand, in the error detection and correction circuit 13, when reading the cell data from the memory cell into the page buffer 12 is performed, the syndrome of the syndrome calculation unit 31 is based on the data of one page. Each calculation circuit sequentially calculates syndromes for each sector. In addition, the error coefficient calculation unit 32 sequentially calculates, for each sector, a solution for a quadratic equation (coefficients e4, e3, e2, e1, e0) of the error position search equation. FIG. 6B shows a syndrome sequentially for sector 0 (Sector <0>), sector 1 (Sector <1>), sector 2 (Sector <2>), and sector 3 (Sector <3>) from time t0. Syndorome) shows that the calculation of the coefficients (e4, e3, e2, e1, e0) of the error location search equation proceeds. This calculation process requires a time of 13.6 µs from the start of the ECC process, and ends with time t2. In addition, the processing time of each calculation is the same time as the error detection correction circuit 13a.

At time t2, the coefficients e4, e3, e2, e1, e0 of the error position search equations for the sectors 1 to 4 are latched in each of the coefficient latches of the latch unit 35. That is, when an arbitrary column address is input to the substitution value calculating unit 36 after the time t2, the Chien search unit 33 can perform an error determination on the data of the bit indicated by the column address. In addition, the error correction unit 34 may detect and correct an error of the cell data whose position is identified by the column address, and output the error to the outside through the I / O pad 15. That is, compared with the error detection correction circuit 13a, the error detection correction circuit 13 does not require the process of writing the data after correction of all the cells of one page in the buffer 14, and the first access over The head can be shortened to 13.6 μs. In addition, in Fig. 6B, the output to the outside of the data is indicated in the arrangement order (the order of the column addresses) of the data of the bits in the page buffer 12, that is, the order of the sectors. However, after time t2, random access is possible, and it is possible to error-correct the bit at any position of any sector and immediately output it. That is, since only the calculation time of the correction coefficient (the calculation time by the substitution value calculation unit 36 and the Chien search unit 33, about 40 ns) is required as the calculation time required before the data output, the error detection correction circuit 13a is required. Compared with), the first access overhead can be greatly reduced.

As described above, the error detection and correction circuit 13 according to an embodiment of the present invention includes a data storage unit (page buffer 12) for storing a data string, a syndrome calculation unit 31 for calculating a syndrome from the data string, and a syndrome. An error coefficient calculation unit 32 for calculating a coefficient of the error position search equation, a latch unit 35 for storing the coefficient, an address (column address) indicating the position of the data column, and a coefficient stored in the latch unit 35. Substituting value calculation section 36 for calculating the substituting value x that is substituted into the error positioning search equation Λ (x) using the error position searching equation Λ (x) at the time of outputting the data string. In response to the assignment result of)), according to the Chien search unit 33 for outputting an error detection signal ERR <i> indicating whether there is an error for each bit of the data string, and according to the error detection signal ERR <i>. Correct the error of the data of the bit of the data string and output it. It includes an error correction unit (34).

The error detection correction circuit 13 according to an exemplary embodiment of the present invention calculates a substitution value for calculating a substitution value of an error position search equation such as a latch unit 35 that stores a coefficient of the error position search equation, a coefficient and a bit position, and the like. The part 36 is provided. Therefore, if the address (column address) of the read bit is input to the substitution value calculation unit 36 at the time of reading the data, the Chien search unit 33 detects whether or not there is an error in the data of the corresponding bit. If there is an error in the data of the corresponding bit, the error correction unit 34 corrects the data of the bit, outputs the data of the corrected bit, and if there is no error, outputs the data of the bit as it is. Accordingly, an error detection correction circuit and a memory device capable of performing error correction on the data of bits at any address in the data string (Cell Data) and outputting the data after the correction at high speed are provided.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims equivalent to the claims of the present invention as well as the claims of the following.

10; Nonvolatile semiconductor memory 11; The memory cell array
12; Page buffer 13; Error detection correction circuit
14; Buffer 15; I / O pads
16; Control circuit 17; The address decoder
18; Low and Block Decoder
30; Decoder section 31; Syndrome calculation unit
31_1-31_4; Syndrome output circuit 32; Miscalculation
33; Chien search unit 34; Error correction part
34_i, 330_1, 330_2, 330_15, 330_16; Exclusive OR operation circuit
35; Latch
35_1, 35_2, 35_3, 35_4; Counting latch
36; Substitution value calculation part
40; An encoder section 41; Parity generation circuit
301-304, 401-408; Selector
321_1, 321_2, 321_16, 322_1, 322_2, 322_16, 323_1, 323_2, 323_16, 324_1, 324_2, 324_16; Integer multiplication circuit
310, 311, 312, 313, 314; Flip flop
340_1, 340_2, 340_15, 340_16; Logic inversion circuit
411-414, 421, 422, 431, 441, 442, 461-464; Multiplication circuit
451, 452; Square operation circuit

Claims (3)

A data storage for storing a data string;
A syndrome calculation unit calculating a syndrome from the data string;
An error coefficient calculator for calculating coefficients of an error location search equation using the syndrome;
A latch unit for storing the coefficients;
A substitution value calculator for calculating a substitution value substituted into the error location search equation using an address indicating a location of the data string and a coefficient stored in the latch unit;
A Chien search unit for outputting an error detection signal indicating whether there is an error for each bit of the data string in response to a substitution result for the error position search equation of the substitution value when the data string is output; And
And an error correction unit for correcting and outputting an error of data of bits of the data string in response to the error detection signal. The method of claim 1,
The data column is composed of a plurality of data columns,
And the latch unit is provided to correspond to each of the plurality of data strings. An error detection correction circuit,
The error detection correction circuit,
A data storage for storing a data string;
A syndrome calculation unit calculating a syndrome from the data string;
An error coefficient calculator for calculating coefficients of an error location search equation using the syndrome;
A latch unit for storing the coefficients;
A substitution value calculator for calculating a substitution value substituted into the air position search equation using an address indicating a location of the data string and a coefficient stored in the latch unit;
A Chien search unit for outputting an error detection signal indicating whether there is an error for each bit of the data string in response to a substitution result for the error position search equation of the substitution value when the data string is output; And
An error correction unit configured to correct and output an error of data of bits of the data string in response to the error detection signal,
The data storage unit is a circuit which stores a data string read from the storage element,
And the address is a column address indicating a position of a column of the memory element.

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