KR20140002163A - Integrated circuit chip and memory device - Google Patents

Abstract

An integrated circuit chip includes: a plurality of test input pads which receive a plurality of test input signals; a plurality of single-ended type buffers which receive signals inputted to the test input pads in a connection test mode; a plurality of differential type buffers which receive signals inputted to the test input pads in a normal mode; a signal combining unit which generates a plurality of test output signals by combining the test input signals inputted through the single-ended type buffers; and a plurality of test output pads which output a plurality of test output signals in the connection test mode. [Reference numerals] (240) Signal combining unit; (251) Output unit

Description

INTEGRATED CIRCUIT CHIP AND MEMORY DEVICE}

The present invention relates to integrated circuit chips and memory devices, and more particularly to a technique for testing whether each pad (pin) of an integrated circuit chip is electrically connected to a substrate (board).

When attaching an integrated circuit chip such as a memory device to a board, a test is performed to check a bonding state such as whether the package is properly bonded and whether the board and the pin are properly connected. Conventionally, a test method called a boundary scan test is used to test the bonding state of a board and a pin. This method has a disadvantage in that a lot of time is consumed by shifting a test pattern.

Recently, in a memory device, a connectivity test method for testing an electrical connection state of a pad in parallel by applying signals to a plurality of pads of a chip has been proposed. Therefore, there is a need for a chip design that reliably supports new types of connection test.

An object of the present invention is to provide an integrated circuit chip that supports a connection test method for quickly testing the electrical connection state of a plurality of pads and operates stably.

An integrated circuit chip according to an embodiment of the present invention for achieving the above object, a plurality of test input pads for receiving a plurality of test input signals; A plurality of single-ended type buffers for receiving signals input to the plurality of test input pads in a connected test mode; A plurality of differential type buffers for receiving signals input to the plurality of test input pads in a normal mode; A signal combination unit generating a plurality of test output signals by combining a plurality of test input signals input through the plurality of single-ended type buffers; And a plurality of test output pads for outputting the plurality of test output signals in the connected test mode.

In addition, a memory device according to an embodiment of the present invention, a chip select pad; A plurality of control pads; A plurality of command pads; A plurality of address pads; A plurality of single-ended type buffers for receiving signals input to the chip select pad, the plurality of control pads, the plurality of command pads and the plurality of address pads in a connection test mode; A plurality of differential type buffers for receiving signals input to the chip select pad, the plurality of control pads, the plurality of command pads, and the plurality of address pads in a normal mode; In the connected test mode, a plurality of test output signals are combined by combining a plurality of test input signals input through single-ended type buffers corresponding to the plurality of control pads, the plurality of command pads, and the plurality of address pads. Signal combination unit for generating a; An output for outputting the plurality of test output signals through a plurality of data pads and a plurality of strobe pads in response to a chip select signal input through a single-ended type buffer corresponding to the chip select pad in the connection test mode It includes a circuit.

According to the present invention, both the differential type buffer and the single-ended type buffer are provided in the input pads used in the connection test mode, and optimal buffers are selected and used. Therefore, there is an advantage that it is possible to reduce the current consumption and at the same time stable operation.

1 shows package pins (pads) used in a connection test of a memory device.
2 is a block diagram of an embodiment of a memory device in accordance with the present invention.
3 is a diagram illustrating an embodiment of the single-ended type buffers 220 and 221 of FIG. 2.
FIG. 4 is a diagram illustrating an embodiment of the differential type buffers 230 and 231 of FIG. 2.
FIG. 5 is a timing diagram illustrating an operation in a connection test mode of the memory device of FIG. 2. FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

1 is a diagram illustrating package pins (pads) used in a connection test of a memory device.

These pads (pins) are used for each purpose in the connection test.

1. Test Enable Pad: This pad enables the test mode for the connection test. The test activation pad is marked TEN.

2. Chip Select Pad: The signal input to this pad is related to the output of the test output signal during the connection test. When the signal input to the chip select pad CS_n is 'low', the test output signals are output to the test output pads, otherwise the test output pads are tri-stated.

3. Test Input Pads: In the connection test mode, pads to which input signals for a connection test are input. The test input pads include bank address pads 0 to 1 (BA0 and BA1), bank group address pads (BG0) to 0, address pads 0 to 9 (A0, A1, A2, A3, A4, A5, A6, and A7). , A8, A9), address 10 / auto precharge pad (A10 / AP), address 11 (A11), address 12 / burst chop pad (A12 / BC_n), address 13 (A13), light Enable / Address 14 Pad (WE_n / A14), Column Address Strobe / Address 15 Pad (CAS_n / A15), Row Address Strobe / Address 16 Pad (RAS_n / A16), Reset Pad (RESET_n), Clock Enable Pad CKE, Active Pad ACT_n, On Die Termination Pad (ODT), Positive Clock Pad CLK_t, Sub Clock Pad CLK_c, Data Mask Low / Data Bus Inversion Low Pad (DML_n / DBIL_n), Data There are a mask up / data bus inversion up pad (DMU_n / DBIU_n), an alert pad (ALERT_n), and a parity pad (PAR). Among these, the pads (BA0, BA1, BG0, A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10 / AP, A11, A12 / BC_n, A13) are classified as address pads. , The pads WE_n / A14, CAS_n / A15, RAS_n / A16, ACT_n are classified into command pads, and the pads CKE, ODT, CLK_t, CLK_c, DML_n / DBIL_n, DMU_n / DBIU_n, ALERT_n, PAR, RESET_n ) Into the control pads.

4. Test Output Pads: In the connected test mode, test output signals generated by a logical combination of signals input to the test input pads are output pads. The test output pads include 16 data pads DQ0 to DQ15 and four strobe pads DQSU_t, DQSU_c, DQSL_t and DQSL_c.

2 is a configuration diagram of an embodiment of a memory device according to the present invention.

Referring to FIG. 2, a memory device may include a test activation pad TEN PAD, a chip select pad CS_n PAD, a plurality of test input pads 210, a plurality of single-ended type buffers 220 and 221, and a plurality of test input pads. The differential type buffers 230 and 231 include a signal combination unit 240, an output circuit 250, and a plurality of test output pads 260.

The single-ended type buffer 201 connected to the test activation pad TEN PAD buffers the test activation signal TEN. The test enable signal TEN maintains the 'high' level in the connection test mode and maintains the 'low' level during normal operation. The single-ended type buffer 201 is a buffer designed as a logic gate such as an inverter and a NAND gate. The single-ended type buffer 201 consumes less current than the differential type buffer, but does not recognize high frequency signals. Since the test enable signal TEN is a low frequency signal that maintains the 'high' level during the connection test operation and otherwise maintains the 'low' level, the test enable signal TEN is transmitted through the single-ended type buffer 201. There is no problem with receiving.

The plurality of test input pads 210 includes 30 pads. These pads 210 are address pads BA0, BA1, BG0, A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10 / AP, A11, A12 / as described above. BC_n, A13), command pads WE_n / A14, CAS_n / A15, RAS_n / A16, ACT_n, and control pads CKE, ODT, CLK_t, CLK_c, DML_n / DBIL_n, DMU_n / DBIU_n, ALERT_n, PAR, RESET_n Can be classified as).

The plurality of single-ended type buffers 220 and 221 receive signals input to the plurality of test input pads 210 and signals input to the chip select pad CS_n PAD in the connection test mode. do. Signals received into the single-ended buffers 220 through the test input pads 210 are transferred to the signal combination unit 240. The signal received through the single-ended buffer 221 is transferred to the output circuit 250. The plurality of single-ended type buffers 220 and 221 are activated when the test activation signal TEN indicating the connection test mode is 'high' level, and deactivated when the test activation signal TEN is 'low' level. The single-ended type buffers 220 and 221 consume less current than the differential type buffers 230, but are inferior to the differential type buffers 230 and 231. That is, the differential type buffers 230 and 231 operate more stably than the single-ended type buffers 220 and 221 in order to receive a high frequency signal. Since the high frequency signal is not input to the test input pads 210 in the connection test mode, the signal is applied to the pads 210 through the single-ended type buffers 220 in the connection test mode. Does not cause problems.

The plurality of differential type buffers 230 and 231 receive signals input to the plurality of test input pads 210 and the chip select pad CS_n PAD in the normal mode (ie, not in the connection test mode). do. The differential type buffers 230 and 231 are activated when the test activation signal TEN indicating the connection test mode is 'low' level, and is deactivated when the test activation signal TEN is 'high' level. The differential type buffers 230 and 231 compare the signal received by the pads 210 and CS_n PAD with the reference voltage VREF. When the voltage level of the received signal is higher than the reference voltage VREF, the received signal is' If the received signal is lower than the reference voltage VREF, the received signal is recognized as 'low'. The differential type buffers 230 and 231 have better characteristics in the reception of a high frequency signal than the single-ended type buffers 220 and 221. However, since the differential type buffers 230 and 231 are configured as a differential amplifier including a current mirror, the current type buffers 230 and 231 consume more current than the single-ended type buffers 220 and 221. The differential type buffers 230 and 231 use the reference voltage VREF for comparison with the voltage level of the received signal, and the reference voltage VREF is adjusted by setting information input from the outside of the memory device. However, in the connection test mode, since most pads are used for the connection test operation, it is impossible to receive setting information for setting the level of the reference voltage VREF. Therefore, in the connection test mode in which the level of the reference voltage VREF is unstable, the single-ended buffers 220 and 231 may operate more stably than the differential type buffers 230 and 231.

Since the differential type buffers 230 and 231 are buffers used in normal operation, signals received by the differential type buffers 230 and 231 are transferred to the normal path NORM_PATH. In this case, the transfer to the normal path NORM_PATH means address pads BA0, BA1, BG0, A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10 / AP, A11, A12 / The signals input to the BC_n and A13 are transferred to an address decoder (not shown), and the signals input to the command pads WE_n / A14, CAS_n / A15, RAS_n / A16 and ACT_n and the chip select pad CS_n PAD It is transmitted to the command decoder (not shown), and signals input to the control pads CKE, ACT_n, ODT, CLK_t, CLK_c, DML_n / DBIL_n, DMU_n / DBIU_n, ALERT_n, are transmitted to the control circuit (not shown). it means.

The signal combination unit 240 generates test output signals TEST_OUT1 to TEST_OUT20 using the test input signals transmitted from the single-ended type buffers 220. The signal combination unit 240 generates test output signals TEST_OUT1 to TEST_OUT20 by logically combining the test input signals using the XOR gates and the inverters. Table 1 below shows how the test output signals TEST_OUT1 to TEST_OUT20 are generated by logical combinations of the test input signals and to which test output pads the test output signals TEST_OUT1 to TEST_OUT20 are generated. I cleaned up. In the following table, XOR (A, B, C) indicates that a test output signal can be generated by an XOR gate that inputs A, B, C signals, and INV (D) inverts the D signal by an inverter. By means of which a test output signal can be generated.

Test output signal Logical Combination Method Test output pad TEST_OUT1 XOR (A1, A6, PAR) DQ0 TEST_OUT2 INV (TEST_OUT1) DQ1 TEST_OUT3 XOR (A8, ALERT_n, A9) DQ2 TEST_OUT4 INV (TEST_OUT3) DQ3 TEST_OUT5 XOR (A2, A5, A13) DQ4 TEST_OUT6 INV (TEST_OUT5) DQ5 TEST_OUT7 XOR (A0, A7, A11) DQ6 TEST_OUT8 INV (TEST_OUT7) DQ7 TEST_OUT9 XOR (CLK_c, ODT, CAS_n / A15) DQ8 TEST_OUT10 INV (TEST_OUT9) DQ9 TEST_OUT11 XOR (CKE, RAS_n / A16, A10 / AP) DQ10 TEST_OUT12 INV (TEST_OUT11) DQ11 TEST_OUT13 XOR (ACT_n, A4, BA1) DQ12 TEST_OUT14 INV (TEST_OUT13) DQSL_c TEST_OUT15 XOR (DMU_n / DBIU_n, DML_n / DBIL_n, CLK_t) DQ13 TEST_OUT16 INV (TEST_OUT15) DQSU_c TEST_OUT17 XOR (WE_n / A14, A12 / BC, BA0) DQ14 TEST_OUT18 INV (TEST_OUT 17) DQ15 TEST_OUT19 XOR (BG0, A3, RESET_n) DQSL_t TEST_OUT20 INV (TEST_OUT19) DQSU_t

The signal combination unit 240 receives a test activation signal TEN. When the test activation signal TEN is activated, the signal combination unit 240 is activated, and when the test activation signal TEN is deactivated, the signal combination unit 240 is activated. 240 is deactivated. Here, the meaning that the signal combination unit 240 is deactivated may mean that the input of the test input signals to the signal combination unit 240 is cut off, or the supply of power to the signal combination unit 240 is cut off.

The output circuit 250 outputs the test output signals TEST_OUT1 to TEST_OUT20 generated by the signal combination unit 430 to the plurality of test output pads 260. The output circuit 250 may include 20 output units 251, and each of the output units 251 may include a pipe latch and an output driver for outputting signals. As described above, the test output pad 260 includes 16 data pads DQ0 to DQ15 and four strobe pads DQSU_t, DQSU_c, DQSL_t, and DQSL_c. Refer to Table 1 above for which test output signal is output to which of the test output pads 260. The output circuit 250 is controlled by the chip select signal CS_n in the connection test mode section, that is, in the section in which the test activation signal TEN is activated. In this period, when the chip select signal CS_n is applied as 'low', the test output signals TEST_OUT1 to TEST_OUT20 are output to the test output pads 260, otherwise, the test output pads 260 are output to the tree state (T). tri-state) The output circuit 250 outputs signals suitable for the purpose of each pad in the normal mode other than the connection test mode. For example, in the normal mode, the output circuit 250 outputs data to the data pads DQ0 to DQ15, and outputs a data strobe signal to the strobe pads DQSU_t, DQSU_c, DQSL_t, and DQSL_c.

A host (eg, a memory controller) connected to the memory device on the board transfers test input signals to the memory device to the test input pads 210 in the connected test mode and outputs from the memory device through the test output pads 260. By checking the test output signals, the electrical connection between the test input pads 210 and the test output pads 260 may be checked.

According to the present invention, the pads receiving the signals required for the test during the connection test are provided with both a single-ended type buffer and a differential type buffer. In the connection test mode in which no high frequency signal is input to the pads and the reference voltage level is not stable, a single-ended type buffer is used, and a high frequency signal is input to the pads and the reference voltage level is stable. In mode, a differential type buffer is used. That is, according to the present invention, optimal buffers are selected and used according to the mode. Therefore, it is possible to reduce the current consumption of the memory device and at the same time enable stable operation.

FIG. 3 is a diagram illustrating an embodiment of the single-ended type buffers 220 and 221 of FIG. 2.

In FIG. 3, only a buffer corresponding to one test input pad of the 31 single-ended type buffers 220 and 221 illustrated in FIG. 2 is illustrated.

Referring to FIG. 3, the single-ended type buffers 220 and 221 include PMOS transistors 301, 302, 304, and 305 and NMOS transistors 303, 306, and 307.

When the test enable signal TEN is activated 'high', that is, when the TENB signal is activated 'low', the PMOS transistors 301 and 304 are turned on to activate the buffer. If the signal IN input to the test input pad has a high level while the buffer is activated, the NMOS transistor 303 and the PMOS transistor 305 are turned on so that the output signal OUT of the buffer becomes 'high'. When the input signal IN has a low level, the PMOS transistor 102 and the NMOS transistor 106 are turned on so that the output signal OUT of the buffer becomes 'low'. Such a single-ended buffer consumes a small amount of current to consume current only when the logic level of the input signal IN is changed, but a logic value of a signal input at a high frequency, that is, a swing width is small. There is a disadvantage in correctly recognizing. Although FIG. 3 illustrates the most basic single-ended type buffer having an inverter-like configuration, the single-ended type buffer may have various structures in which several logic gates are mixed.

FIG. 4 is a diagram illustrating the configuration of the differential type buffers 230 and 231 of FIG. 2.

In FIG. 4, only a buffer corresponding to one test input pad of the 31 differential type buffers 330 and 331 illustrated in FIG. 2 is illustrated.

Referring to FIG. 4, the differential type buffer has a differential amplifier structure for detecting a voltage difference between an input signal IN and a reference voltage VREF input to a test input pad. The two PMOS transistors 408 and 409 form a current mirror structure, and the same current is supplied to the two nodes A and B, and the reference voltage VREF and the input signal IN respectively input to the NMOS transistors 410 and 411. The two nodes A and B are differentially amplified by the potential difference of. As a result, if the input signal IN has a voltage level higher than the reference voltage VREF, the output signal OUT has a 'high' level, and if the input signal IN has a level lower than the reference voltage VREF, the output signal Has a 'low' level. Meanwhile, the NMOS transistor 412 is turned on when the test activation signal TEN has a 'low' level, that is, when the TENB signal has a 'high' level. When the NMOS transistor 412 is turned on, current flows in the buffer, and the buffer is activated. When the NMOS transistor 412 is turned off, no current flows in the buffer, and the buffer is deactivated.

This differential type buffer can accurately recognize the logic value of the signal even when the swing width of the input signal IN is small (that is, when the input signal is applied at a high speed). As current flows, it consumes a lot of current. In addition, since the differential type buffer senses the logic level of the input signal IN by comparing the level of the input signal IN with the reference voltage VREF, the level of the reference voltage VREF is unstable or the reference voltage ( If VREF) has the wrong level, it is impossible to operate stably. 4 illustrates a differential type buffer having a most basic form, and the differential type buffer may have various structures different from those of FIG. 4.

FIG. 5 is a timing diagram illustrating an operation in a connection test mode of the memory device of FIG. 2.

First, the test activation signal TEN is activated to the 'high' level at time '501', and the memory device enters the connection test mode. In response to the activation of the test activation signal TEN, the single-ended type buffers 220 and 221 are activated and the differential type buffers 230 and 231 are deactivated.

The test input signals input through the test input pads 210 at the time point '502' are buffered through the single-ended type buffers 220 and transferred to the signal combination unit 240. Then, the signal combination unit 240 generates test output signals TEST_OUT1 to TEST_OUT20 using the received test input signals.

When the chip select signal CS_n transitions to the 'low' level at the time '503', the output circuit 250 outputs the test output signals TEST_OUT1 to TEST_OUT20 through the test output pads 260.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

In addition, although the above-described embodiment illustrates that the present invention is applied to a memory device, the present invention can be applied not only to the memory device but also to all kinds of integrated circuit chips for testing the electrical connection of the pads. In addition, it is obvious that the type and number of pads used for the connection test may vary depending on the integrated circuit chip.

TEN PAD: Test Activation Pad CS_n PAD: Chip Select Pad
210: test input pads 220, 221: single-ended type buffers
230, 231: differential type buffers 240: signal combination
250: output circuit 260: test output pads

Claims (13)

A plurality of test input pads for receiving a plurality of test input signals;
A plurality of single-ended type buffers for receiving signals input to the plurality of test input pads in a connected test mode;
A plurality of differential type buffers for receiving signals input to the plurality of test input pads in a normal mode;
A signal combination unit generating a plurality of test output signals by combining a plurality of test input signals input through the plurality of single-ended type buffers; And
A plurality of test output pads for outputting the plurality of test output signals in the connected test mode
Integrated circuit chip comprising a.
The method of claim 1,
The signal combination unit
A plurality of XOR gates and a plurality of inverters for combining a plurality of test input signals input through the plurality of single-ended type buffers.
Integrated circuit chip.
The method of claim 1,
The plurality of differential type buffers
Compare the voltage level of the signal input to the connected test input pad with the level of the reference voltage.
Integrated circuit chip.
The method of claim 1,
The integrated circuit chip further includes a test activation pad for receiving a test activation signal.
According to the activation / deactivation of the test activation signal, the integrated circuit operates in the connection test mode / the normal mode.
Integrated circuit chip.
The method of claim 1,
Current supply to the plurality of differential type buffers is cut off in the connection test mode, and current supply to the plurality of single-ended type buffers is cut off in the normal mode.
Integrated circuit chip.
Chip select pads; A plurality of control pads; A plurality of command pads; A plurality of address pads;
A plurality of single-ended type buffers for receiving signals input to the chip select pad, the plurality of control pads, the plurality of command pads and the plurality of address pads in a connection test mode;
A plurality of differential type buffers for receiving signals input to the chip select pad, the plurality of control pads, the plurality of command pads, and the plurality of address pads in a normal mode;
In the connected test mode, a plurality of test output signals are combined by combining a plurality of test input signals input through single-ended type buffers corresponding to the plurality of control pads, the plurality of command pads, and the plurality of address pads. Signal combination unit for generating a;
An output for outputting the plurality of test output signals through a plurality of data pads and a plurality of strobe pads in response to a chip select signal input through a single-ended type buffer corresponding to the chip select pad in the connection test mode Circuit
≪ / RTI >
The method according to claim 6,
The memory device
A test activation pad for receiving a test activation signal; And
Further comprising a single-ended type buffer coupled to the test activation pad,
The memory device operates in the connection test mode / the normal mode according to the activation / deactivation of the test activation signal.
Memory device.
The method according to claim 6,
Current supply to the plurality of differential type buffers is cut off in the connection test mode, and current supply to the plurality of single-ended type buffers is cut off in the normal mode.
Memory device.
The method according to claim 6,
The signal combination unit
A plurality of XOR gates and a plurality of inverters for combining the plurality of test input signals
Memory device.
The method according to claim 6,
The plurality of differential type buffers
Compare the voltage level of the signal input to the pad connected to it with the level of the reference voltage.
Memory device.
The method according to claim 6,
The plurality of control pads
Reset pads;
One or more data mask pads;
One or more data bus inversion pads;
One or more clock pads;
A clock enable pad;
Parity pads;
On die termination pads; And
Containing the pad
Memory device.
The method according to claim 6,
The signal combination unit
A first test output signal is generated by logical combination of the first address signal, the sixth address signal, and the parity signal,
Inverting the first test output signal to generate a second test output signal;
A third test output signal is generated by logically combining the eighth address signal, the alert signal, and the nineth address signal,
Inverting the third test output signal to generate a fourth test output signal,
A fifth test output signal is generated by logical combination of address signal 2, address 5 and address 13,
Inverting the fifth test output signal to generate a sixth test output signal,
A seventh test output signal is generated by performing a logical combination of the address signal 0, the address 7 and the address 11,
Inverting the seventh test output signal to generate an eighth test output signal,
A ninth test output signal is generated by logically combining the subclock signal, the on die termination signal, and the column address strobe / address 15 signal,
Inverting the ninth test output signal to generate a tenth test output signal,
An eleventh test output signal is generated by logically combining the clock enable signal, the row address strobe / address 16 and the address 10 / auto-charge signal;
Inverting the eleventh test output signal to generate a twelfth test output signal,
A thirteenth test output signal is generated by logically combining the active signal, the address 4, and the bank address 13;
Inverting the thirteenth test output signal to generate a fourteenth test output signal,
Generating a fifteenth test output signal by logical combination of the data mask / data bus inversion up signal, the data mask / data bus inversion down signal, and the positive clock signal;
Inverting the fifteenth test output signal to generate a sixteenth test output signal,
The 17th test output signal is generated by logical combination of the write enable / address 14, address 12 / burst chop signal, and bank address 0 signal.
Inverting the seventeenth test output signal to generate an eighteenth test output signal,
A logical combination of the 0 bank group address, the 3 address and the reset signal is generated to generate a 19 th test output signal;
Inverting the nineteenth test output signal to generate a twentieth test output signal
Memory device.
13. The method of claim 12,
The output circuit
Outputting the first to thirteenth test output signals, the fifteenth test output signals, and the seventeenth to eighteenth test output signals to data pads 0 to 15;
Outputting the fourteenth test output signal, the sixteenth test output signal, and the nineteenth to twentieth test output signals to four data strobe pads.
Memory device.

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