KR20130142057A - Organic light emitting display device - Google Patents

Abstract

The present invention relates to an organic light emitting display device. According to the present invention, the organic light emitting display device includes a first line formed on a substrate, a second line intersecting with the first line, and an electrostatic distribution pattern insulated from and intersecting with the second line. The side of the first line is vertical to one surface of the substrate.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light-

The present invention relates to an organic light emitting display device, and more particularly, to an organic light emitting display device that prevents damage caused by electrostatic discharge (ESD).

The organic light emitting diode display includes an organic light emitting diode, and energy generated when an exciton generated by combining electrons and holes in the organic light emitting layer of the organic light emitting diode falls from the excited state to the ground state. Emits light.

The organic light emitting display devices may be manufactured individually, but a plurality of organic light emitting display devices may be formed on one mother substrate to improve productivity, and then cut into each organic light emitting display device. In this case, the panel inspection of the organic light emitting display device is performed after being cut by each organic light emitting display device, so the efficiency of the inspection is inferior. The inspection is performed.

However, the test wiring used for the panel inspection of the ledger unit, so-called ledger wiring, remains in the organic light emitting display device even after cutting the mother substrate, and static electricity flows through the ledger wiring, causing damage to internal elements.

In particular, when a two-step cutting process is performed in a dummy space between the organic light emitting display devices, the amount of ledger wiring remaining in the organic light emitting display device is small. In order to remove the dummy space and cut once in order to increase the efficiency of production, the amount of ledger wires remaining in the organic light emitting diode display is relatively increased, which causes more damage due to static electricity.

Accordingly, an object of the present invention is to provide an organic light emitting display device capable of preventing damage caused by the inflow of static electricity.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a method of manufacturing the same.

An organic light emitting display device according to an exemplary embodiment of the present invention provides a substrate, a first wiring formed on the substrate, a second wiring insulated from and intersecting the first wiring, and an insulation from the second wiring. And intersect with the electrostatic dispersion pattern.

According to another aspect of the present invention, an organic light emitting display device includes a substrate, a gate line and a data line formed on the substrate, and are insulated from each other, and are the same as one of the gate line and the data line. A dummy wiring formed in the layer and having at least one end aligned with the sidewalls of the substrate, a dummy crossing wiring insulated from and intersecting the dummy wiring, and an electrostatic dispersion pattern insulated from and intersecting the dummy crossing wiring.

In accordance with another aspect of the present invention, an organic light emitting display device includes a substrate, a first wiring formed on the substrate, a second wiring insulated from and intersecting the first wiring, and an insulation from the second wiring. And intersect with each other to form a closed curve shape, and a semiconductor pattern insulated from and cross the electrostatic dispersion pattern.

The details of other embodiments are included in the detailed description and drawings.

The embodiments of the present invention have at least the following effects.

That is, an organic light emitting display device capable of preventing damage due to static electricity inflow can be provided.

In addition, even when the process of cutting each organic light emitting display device formed on the mother substrate once, an organic light emitting display device capable of preventing damage due to static electricity can be provided.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the specification.

1 is a conceptual diagram of a mother substrate of an organic light emitting display device according to an embodiment of the present invention.
2 is a schematic diagram of a planar layout of an organic light emitting display device according to an exemplary embodiment.
3 is an enlarged view of region A in Fig.
4 and 5 are cross-sectional views of substrate sidewall alignment lines in accordance with some embodiments of the present invention.
6 is a cross-sectional view of a substrate sidewall misaligned wiring in accordance with some embodiments of the present invention.
FIG. 7 is an enlarged view of region B of FIG. 2.
FIG. 8 is an enlarged view of region C of FIG. 2.
FIG. 9 is an enlarged view of region D of FIG. 2.
FIG. 10 is a cross-sectional view taken along the line XX 'of FIG. 9.
11 is a partial cross-sectional view of an organic light emitting display device according to another exemplary embodiment of the present invention.
12 is a schematic diagram of a planar layout of an organic light emitting diode display according to another exemplary embodiment of the present invention.
FIG. 13 is a cross-sectional view taken along the line XIII-XIII ′ of FIG. 12.
14 is a schematic diagram of a planar layout of an organic light emitting display device according to another exemplary embodiment.
FIG. 15 is a cross-sectional view taken along the line XV-XV ′ of FIG. 14.
16 is a cross-sectional view illustrating a pixel area and an electrostatic dispersion area of an organic light emitting diode display according to an exemplary embodiment of the present invention.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

It is to be understood that elements or layers are referred to as being "on " other elements or layers, including both intervening layers or other elements directly on or in between. Like reference numerals refer to like elements throughout.

Although the first, second, etc. are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may be the second component within the technical scope of the present invention.

Hereinafter, with reference to the accompanying drawings will be described embodiments of the present invention.

1 is a conceptual diagram of a mother substrate of an organic light emitting display device according to an embodiment of the present invention. Referring to FIG. 1, the mother substrate 10 includes a plurality of cells CE. Each cell CE may be arranged in a matrix shape. Each cell CE may have substantially the same structure and the same size.

A cutting line CL is defined at a boundary between each cell CE, and each cell CE cut along the cutting line CL may be harvested with one organic light emitting display. The mother substrate driver 11 may be formed at the periphery of the mother substrate 10. The cutting line CL is defined between the mother substrate driver 11 and the adjacent cell CE, and the mother substrate driver 11 may be separated and removed from the cell CE by cutting.

A plurality of signal wires 12 are formed on the mother substrate 11. Specific examples of the signal wiring 12 include a gate line, a data line, a power supply line, an inspection wiring, and the like. Some signal wires 12_1, for example, gate lines or data lines, may cross the plurality of cells CE. Some of the other signal lines 12_2 may not cross the specific cell CE, and the terminal may be located at the end of the specific cell CE, or may enter the specific cell CE and be folded back to return to the entered direction.

At least some signal wires 12 may be connected to the mother substrate driver 11. The mother substrate driver 11 may provide various electrical signals (voltage or current) for testing or simulating the signal wire 12 or elements directly or indirectly connected thereto. As an example of the test, a test signal may be provided to the signal line 12 to perform lighting inspection on a plurality of cells CE connected to the plurality of cells CE and the pixels included therein. In addition, the test signal may be provided to the signal line to perform an aging test, a leakage current test, or the like for each cell CE or pixel element.

As an alternative or combination embodiment of the mother substrate driver 11 described above, a wiring pad unit capable of applying an electrical signal using a probe may be provided at the periphery of the mother substrate 10.

The signal line 12 which enters or exits the mother substrate driver 11 or another cell CE from a specific cell CE is cut together when the mother substrate 10 is cut along the cutting line CL. do. Accordingly, the sidewalls of the substrate 110 (110 in FIG. 2) of the cut cell CE and the ends of the cut signal wire 12 will be substantially aligned with each other.

The mother substrate 110 may be cut in a direction perpendicular to one surface. Accordingly, in the cut cell CE, the sidewall of the substrate 110 '110' of FIG. 2 may be perpendicular to one surface or the other surface of the substrate 110'110 'of FIG. 2. Similarly, the end of the cut signal wire 12 may also be perpendicular to one side or the other side of the substrate. Furthermore, the sidewalls of the substrate 110 '110' and the surface of the signal wire 12 end may be disposed in the same plane.

FIG. 2 is a schematic diagram of a planar layout of an organic light emitting display device according to an embodiment of the present invention. FIG. 2 is a planar layout of an organic light emitting display device corresponding to one cell that is cut and cut along a cutting line from the mother substrate of FIG. 1. Shows. FIG. 3 is an enlarged view of region A of FIG. 2.

2 and 3, the organic light emitting diode display 100 may include a substrate 110 in which a display area DA and a non-display area NDA are defined. A plurality of pixels PX may be disposed in the display area DA. Each pixel PX may be arranged in a matrix shape. Each pixel PX may be a pixel representing any one of a plurality of colors. For example, each pixel PX may be one of a red pixel, a green pixel, and a blue pixel. In some embodiments, the plurality of pixels PX may further include white pixels.

In an embodiment, each pixel PX may include a light emitting layer that emits a color corresponding to the corresponding color. For example, the red pixel may include a red organic emission layer, the green pixel may include a green organic emission layer, and the blue pixel may include a blue organic emission layer. In another embodiment, each pixel PX may include a white light emitting layer, and a red, green, or blue color filter may be installed on a path through which light is emitted.

The non-display area NDA may be located at the periphery of the display area DA. In the drawing, a case in which a non-display area is formed outside two neighboring sides of the rectangular display area DA is illustrated, but the non-display area is located only outside one side or non-outside on three or four sides. The display area may be located.

The driver 111 may be disposed in the non-display area NDA. The driver 111 may include a gate driver 111_1, a data driver 111_2, and the like. The driving unit 111 may further include a driving chip that generates and provides a driving signal or receives and transfers a driving signal. In another embodiment, the driving chip may be mounted on an external substrate such as a printed circuit board or a flexible printed circuit board, and then connected to a pad unit provided in the driving unit 111.

A plurality of wirings are disposed on the substrate 110. The wiring is made of a conductive material. Wiring may be made of a single conductive film or a plurality of conductive films may be stacked.

Some wires may be at least one end aligned with the sidewalls 110s of the substrate 110. Such wiring is referred to herein as substrate sidewall alignment wiring (AW). At least one end of the substrate sidewall alignment line 110s extends to an edge of the substrate 110 in plan view.

The substrate sidewall alignment line AW originally extended to the neighboring cell ('CE' in FIG. 1) or the mother substrate driver ('12' in FIG. 1) on the mother substrate ('10' in FIG. 1), but the mother substrate ( As the '10' of FIG. 1 is cut along the cutting line (“CL” of FIG. 1), an end thereof may be aligned with the sidewall 110s of the substrate 110.

4 and 5 are cross-sectional views of substrate sidewall alignment lines in accordance with some embodiments of the present invention. 4 illustrates a case where the side surface AW_1s of the end of the substrate sidewall alignment line AW_1 is at least partially inclined at an acute angle θ1, and the lower end is aligned with the sidewall 110s of the substrate 110. FIG. 5 illustrates a case where the side surface AW_2s of the end of the substrate sidewall alignment line AW_2 is perpendicular to one surface of the substrate 110 to be substantially parallel to the sidewall 110s of the substrate 110. When the wires are cut together when the mother substrate ('10' of FIG. 1) is cut along the cutting line ('CL' of FIG. 1), as shown in FIG. An angle formed by the side surface may be the same as an angle formed by the sidewall 110s of the substrate 110. Furthermore, the sidewalls 110s of the substrate 110 and the side surfaces AW_2s of the ends of the cut sidewall alignment wiring AW_2 may be disposed in the same plane.

Referring again to FIGS. 2 and 3, some other wires may not have all ends aligned with the sidewalls of the substrate. Such wiring is referred to herein as substrate sidewall unaligned wiring (NAW).

6 is a cross-sectional view of a substrate sidewall misaligned wiring in accordance with some embodiments of the present invention. As shown in FIG. 6, the substrate sidewall unaligned wiring NAW is spaced apart from the sidewall 110s of the substrate 110s by a predetermined distance d1. The side surfaces NAWs of the end portions of the substrate sidewall misalignment wiring NAW may have a predetermined inclination angle, for example, an inclination angle θ2 of one surface of the substrate 110.

In plan view, the substrate sidewall unaligned wiring NAW does not extend to the edge of the substrate 110 at all ends but has a shape spaced apart from the edge.

Referring again to FIGS. 2 and 3, some wirings formed on the substrate 110 may be signal wirings 121 for transmitting an electrical signal to various elements such as pixels, electrodes, driving chips, and the like. Can be. Some other wires may be dummy wires 122 where signals are applied from the mother substrate, but signals such as driving signals or test signals are not applied after being cut. The dummy wiring 122 may be a floating wiring floating from the signal wiring.

The signal wire 121 may include a gate line 121_1 and a data line 121_2. The gate line 121_1 may extend in the first direction X1, and the data line 121_2 may extend in the second direction X2 crossing the first direction X1. The first direction X1 and the second direction X2 may be perpendicular to each other. Although the gate line 121_1 and the data line 121_2 cross each other on the top view, they may be insulated from each other by being disposed on different layers with an insulating layer therebetween.

The pixel PX may be disposed in an area defined by the intersection of the neighboring gate line 121_1 and the neighboring data line 121_2. That is, the gate line 121_1 and the data line 121_2 may be arranged along the boundary of the neighboring pixel PX.

The gate line 121_1 and the data line 121_2 may include electrodes corresponding to the adjacent pixels PX. For example, the gate line 121_1 may include a gate electrode extended or branched toward the pixel PX side. The data line 121_2 may include a source electrode extended or branched toward the pixel PX side. These electrodes can form a thin film transistor which is a switching element.

The gate line 121_1 and the data line 121_2 may be formed to cross from one side to the other side of the substrate 110, respectively. The gate line 121_1 and the data line 121_2 may include pad portions having an enlarged width positioned in the non-display area NDA.

FIG. 7 is an enlarged view of region B of FIG. 2. FIG. 8 is an enlarged view of region C of FIG. 2.

7 and 8, the gate line 121_1 and the data line 121_2 each have a gate pad part 121_1p having an enlarged width GW2 and DW2 compared to the line widths GW1 and DW1 of the display area. The data pad part 121_2p may be included. The gate line 121_1 and the data line 121_2 extend through the gate pad portion 121_1p and the data pad portion 121_2p to the sidewall 110s of the substrate 110, and the end portion thereof may be a sidewall of the substrate 110. 110s). That is, the gate line 121_1 and the data line 121_2 may be substrate sidewall alignment lines. The line widths GW3 and DW3 at the ends of the gate line 121_1 and the data line 121_2 aligned with the sidewalls 110s of the substrate 110 may be substantially the same as the line widths GW1 and DW1 in the display area. However, it is not limited thereto. The gate pad part 121_1p and the data pad part 121_2p may be omitted.

Hereinafter, the dummy wiring and the surrounding structure will be described in more detail. FIG. 9 is an enlarged view of region D of FIG. 2. FIG. 10 is a cross-sectional view taken along the line XX 'of FIG. 9. 2, 9, and 10, one end of the dummy wire 122 may be aligned with the sidewall 110s of the substrate 110. A plurality of dummy wires 122 may be formed on the substrate 110, and in this case, at least some of the plurality of dummy wires 122 may be substrate sidewall alignment wires AW.

The dummy wire 122 may have a shape extending in the inward direction of the substrate 110 using the sidewalls 110s of the substrate 110 as a starting point. Some dummy wires 122 may extend to the display area DA where the pixel PX is disposed. Although not limited thereto, the dummy wiring 122 may be formed on the same layer as the gate line 121_1 or the data line 121_2. In this case, the dummy wiring 122 may be made of the same process using the same material as the gate line 121_1 or the data line 121_2, and may have the same stacked structure.

The dummy wire 122 may be insulated from and intersect the dummy cross wire 124 at one or more spots SP1. The dummy crossover wiring 124 may be located in the non-display area NDA. The dummy crossover wiring 124 may be formed on a different layer from the dummy wiring 122. An insulating layer 130 may be interposed between the dummy crossover wiring 124 and the dummy wiring 122.

The dummy crossover wiring 124 may be a signal wire such as a gate line 121_1 or a data line 121_2. For example, when the dummy wiring 122 is formed on the same layer as the gate line 121_1, the dummy crossing wiring 124 may be a data line 121_2. On the other hand, when the dummy wiring 122 is formed on the same layer as the data line 121_2, the dummy crossing wiring 124 may be the gate line 121_1. In alternative embodiments, the dummy crossover wiring 124 may be another dummy wiring to which no signal is applied.

The dummy crossover wires 124 may extend along the same direction as the extension direction of the sidewalls 110s of the substrate 110 on which the dummy wires 122 that cross each other are aligned. For example, one sidewall 110s of the substrate 110 is formed along the second direction X2, and the dummy wire 122 is a first perpendicular to the second direction X2 starting from the sidewall 110s. The dummy cross line 124 may extend in the second direction X2.

An electrostatic dispersion pattern 126 may be formed in the vicinity of the dummy wiring 122. The static electricity dissipation pattern 126 may be spaced apart from the dummy wiring 122, and may cross each other by being insulated from one or more spots SP2 and SP3 with respect to the dummy crossing wiring 124. An insulating layer 130 may be interposed between the dummy crossover wiring 124 and the static electricity dissipation pattern 126. When a plurality of dummy wires 122 are provided as the substrate sidewall alignment wires NAW, the electrostatic dispersion pattern 126 may be formed to correspond to the dummy wires 122 one-to-one, although not limited thereto.

The electrostatic dispersion pattern 126 may be made of a conductive material. The static electricity dissipation pattern 126 may be formed on the same layer as the adjacent dummy wiring 122 where the dummy cross wiring 124 intersects, or may be formed by the same process using the same material as the dummy wiring 122. have.

The dummy wiring 122 and the electrostatic dispersion pattern 126 may be formed of the same material on the same layer as the gate line 121_1. In this case, the dummy crossover line 124 may be the data line 121_2 or a signal line or a dummy line having substantially the same extension direction. In another embodiment, the dummy wiring 122 and the electrostatic dispersion pattern 126 may be formed of the same material on the same layer as the data line 121_2. In this case, the dummy crossover wiring 124 may be a gate line 121_1 or a signal wire or a dummy wire having substantially the same extension direction.

In an exemplary embodiment of the stacked structure, the dummy wiring 122 and the electrostatic dispersion pattern 126 are formed on the substrate 110, and the insulating film 130 is covered, and the dummy cross wiring is formed on the insulating film 130. 124 may be formed.

The electrostatic dispersion pattern 126 may be a substrate sidewall unaligned wiring NAW that is not aligned with the sidewall 110s of the substrate 110. That is, the electrostatic dispersion pattern 126 may be disposed to be spaced inward from the sidewall 110s of the substrate 110. The electrostatic dispersion pattern 126 may be disposed in the non-display area NDA. In addition, the static electricity dissipation pattern 126 may be formed to be spaced apart from other signal lines or driving circuits, or may be formed in a region having a low density of signal lines.

The electrostatic dispersion pattern 126 may be formed in a closed curve shape. In this case, there may be a plurality of spots SP2 and SP3 in which the electrostatic dispersion pattern 126 and the dummy crossover wiring 124 cross each other by being insulated from each other. The number of intersection spots SP2 and SP3 illustrated in the figure is two.

In an exemplary embodiment, the electrostatic dispersion pattern 126 may be rectangular in shape. The first side 126_1 and the third side 126_3 facing each other of the electrostatic dispersion pattern 126 cross the dummy crossover wiring 124, and the second side 126_2 extends outside the dummy crossover wiring 124. The fourth side 126_4 may be located inside the dummy crossover wire 124. Here, the outer side of the dummy crossover wiring 124 is a direction close to the sidewall of the substrate with respect to the dummy crossover wiring 124, and the inside of the dummy crossover wiring 124 has the substrate 110 based on the dummy crossover wiring 124. The direction away from the sidewalls 110s of the substrate 110 may refer to a direction toward a central portion of the substrate 110.

The static electricity dissipation pattern 126 may include a portion extending in a direction substantially the same as a direction in which the dummy wire 122 extends. In FIG. 9, the first side 126_1 and the third side 126_3 extend in substantially the same direction as the dummy wiring 122. Other wires having the same extension direction as that of the dummy wire 122 may not be interposed between the electrostatic dispersion pattern 126 and the dummy wire 122 closest thereto.

The electrostatic dispersion pattern 126 may include at least one corner portion. The number of corner portions illustrated in the figure is four. Each corner portion is formed to be relatively pointed, thereby inducing static electricity. In an exemplary embodiment, the interior angle of at least one or all of the corners of the electrostatic dispersion pattern 126 may be right angle or acute angle.

Hereinafter, an electrostatic propagation path in the aforementioned organic light emitting display device will be described. 2, 9, and 10, the dummy wiring 122, which is the substrate sidewall alignment wiring AW, extends to the edge of the organic light emitting diode display 100, and one end thereof is sidewall 110s of the substrate 110. Side), the side surface of the dummy wiring 122 may be directly exposed to the outside.

The exterior of the organic light emitting display device 100 may generate static electricity in various situations. For example, external static electricity may be generated when the organic light emitting display device 100 is tested or packaged, or during storage or normal use of the organic light emitting display device 100. Static electricity generated from the outside may be applied into the organic light emitting display device 100. The initial starting point of the static electricity flowing from the outside will be the outer surface of the organic light emitting display 100. Static electricity is well transmitted through the conductive material. Therefore, the surface of the organic light emitting display device 100 which is made of a conductive material may be a main path for the inflow of static electricity.

As described above, since the dummy wiring 122, which is the substrate sidewall alignment wiring AW, is made of a conductive material and its side surface is directly exposed to the outside, external static electricity may flow therethrough. The introduced static electricity may be transferred along the dummy wiring 122. If the dummy wire 122 extends to the display area DA, static electricity may be transferred to the display area DA. If the amount of static electricity transferred to the display area DA is large, damage may occur to elements or signal wires of the adjacent pixels PX.

On the other hand, a portion of the static electricity transferred along the dummy wiring 122 may be transferred to the cross wiring 124 side at the cross spot SP1 with the cross wiring 124. As a result, the amount of static electricity flowing into the display area DA along the extending direction of the dummy wiring 122 decreases, so that damage to the elements of the pixel or the signal wiring can be reduced. Although the dummy wiring 122 and the cross wiring 124 are insulated and not electrically connected, the static electricity of the dummy wiring 122 jumps to the adjacent cross wiring 124 at the cross spot SP1 where they are closest to each other. Can be delivered.

Static electricity jumped to the cross wiring 124 is transferred along the extending direction of the cross wiring 124. When the static electricity transferred through the cross wiring 124 reaches the cross spots SP2 and SP3 with the static dispersion pattern 126, a part of the static electricity may be jumped and transferred to the static dispersion pattern 126. Static electricity transferred to the static dispersion pattern 126 may be distributed along the extension direction of the static dispersion pattern 126. As a portion of the static electricity introduced from the outside is transferred to the static dispersion pattern 126, the amount of static electricity transferred to the display area DA through the dummy wiring 122 is further reduced to reduce damage of the display area DA. Can be. When the static electricity dispersing pattern 126 is positioned in the non-display area NDA, spaced apart from other signal wirings or driving circuits, or formed in a region with low density of signal wirings, static electricity is transferred to the static electricity dispersing pattern 126. Even so, the influence on the overall organic light emitting display device 100 is minimal.

On the other hand, the static electricity transferred to the electrostatic dispersion pattern 126 may be concentrated in the corner portion of the electrostatic dispersion pattern 126, in this case, the edge portion of the electrostatic dispersion pattern 126 may melt or burn out according to energy concentration. However, even if the electrostatic dispersion pattern 126 is partially damaged, it does not affect the display quality of the organic light emitting display 100, and the formation position of the electrostatic dispersion pattern 126 is relatively far from other elements. Is far away and does not directly affect other devices, so this is not a problem. Rather, it may be evaluated that the energy emitted from the outside was effectively discharged while minimizing the influence on the display quality.

11 is a partial cross-sectional view of an organic light emitting display device according to another exemplary embodiment of the present invention. FIG. 11 illustrates that the same planar arrangement as FIG. 9 may have various stacking structures other than the embodiment of FIG. 10. Referring to FIG. 11, in the organic light emitting diode display according to the present exemplary embodiment, a dummy crossover wiring 124 is formed on a substrate 110, an insulating film 130 is covered, and a dummy wire ( 122 and the electrostatic dispersion pattern 126 are formed. Since other configurations are substantially the same as those in the embodiment of FIG. 10, redundant descriptions are omitted.

12 is a schematic diagram of a planar layout of an organic light emitting diode display according to another exemplary embodiment of the present invention. FIG. 13 is a cross-sectional view taken along the line XIII-XIII ′ of FIG. 12.

12 and 13, the organic light emitting diode display according to the present exemplary embodiment further includes a semiconductor pattern 140 overlapping the electrostatic dispersion pattern 126, which is different from the exemplary embodiment of FIG. 9.

The semiconductor pattern 140 may be formed to intersect the electrostatic dispersion pattern 126. In the present exemplary embodiment, the semiconductor pattern 140 is formed to intersect the second side 126_2 of the electrostatic dispersion pattern 126 positioned outside the dummy crossover line 124. However, the present invention is not limited thereto, and the semiconductor pattern 140 may be formed to intersect the fourth side 126_4, the first side 126_1, or the third side 126_3 of the electrostatic dispersion pattern 126. In addition, two or more semiconductor patterns that cross different sides may be formed. Furthermore, two or more semiconductor patterns crossing one side may be formed. The number and positions of the semiconductor patterns exemplarily listed above may be combined in various ways.

The semiconductor pattern 140 may include at least one line having a predetermined length. In an exemplary embodiment, the semiconductor pattern 140 may include a first side 140_1, a second side 140_2, a third side 140_3, and a fourth side 140_4. Any one of the first side 140_1, the second side 140_2, the third side 140_3, and the fourth side 140_4 may be physically connected to the other. The shape of the semiconductor pattern 140 illustrated in the figure is a substantially rectangular shape. However, the present invention is not limited thereto and may be formed of at least one line type crossing the electrostatic dispersion pattern 126.

The first side 140_1 and the third side 140_3 of the semiconductor pattern 140 may be parallel to each other and may perpendicularly cross the second side 126_2 of the electrostatic dispersion pattern 126 at the intersection spots SP4 and SP5. Can be. The second side 140_2 and the fourth side 140_4 of the semiconductor pattern 140 may be parallel to each other, and may be substantially parallel to the cross wiring 124. The second side 140_2 and the fourth side 140_4 of the semiconductor pattern 140 may protrude from both sides of the first side 140_1 and the third side 140_3. The four protruding portions constitute a substantial corner portion of a rectangular shape, which may serve to relatively concentrate static electricity.

The semiconductor pattern 140 may be formed of amorphous silicon, polycrystalline silicon, single crystal silicon, or an oxide semiconductor. The semiconductor pattern 140 may be formed of the same material as the material constituting the channel region of the thin film transistor provided in the pixel.

The first insulating layer 130_1 may be interposed between the dummy wiring 122 and the electrostatic dispersion pattern 126, and the second insulating layer 130_2 may be interposed between the semiconductor pattern 140 and the electrostatic dispersion pattern 126. The first insulating film 130_1 is substantially the same as the insulating film 130 of FIGS. 10 and 11 described above. As the second insulating film 130_2, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a laminated film including a combination thereof may be applied. The second insulating layer 130_2 not only covers the semiconductor pattern 140, but is not limited thereto, and may cover the whole surface of the substrate 110. In this case, the dummy wiring 122 and the electrostatic dispersion pattern 126 may be formed on the second insulating layer 130_2.

In an exemplary embodiment, the first insulating film 130_1 may be formed of the same material as the thin film transistor interlayer insulating film provided in the pixel, and the second insulating film 130_2 may be formed of the same material as the gate insulating film of the thin film transistor provided in the pixel. .

In this embodiment, the external static electricity introduced through the dummy pattern 122 is transferred to the static dispersion pattern 126 is substantially the same as the embodiment of FIG. According to the present exemplary embodiment, some of the static electricity dispersed in the static dispersion pattern 126 may be further dispersed by jumping to the semiconductor pattern 140 crossing the semiconductor pattern 140. Therefore, the amount of static electricity flowing into the display area DA through the dummy wiring 122 can be effectively dispersed and reduced. When the semiconductor pattern 140 is positioned in the non-display area NDA, even if static electricity is transferred to the semiconductor pattern 140, the influence on the overall organic light emitting display device is minimal. As described above, even if the energy is concentrated in the semiconductor pattern 140 and the pattern is damaged, the impact on the overall organic light emitting display device will be small.

The semiconductor pattern 140 described above may be replaced with a conductive pattern made of a conductive material. Of course, in this case, the substantially same static electricity dissipation mechanism will work.

14 is a schematic diagram of a planar layout of an organic light emitting display device according to another exemplary embodiment. FIG. 15 is a cross-sectional view taken along the line XV-XV ′ of FIG. 14.

14 and 15, the organic light emitting diode display according to the present exemplary embodiment differs from the exemplary embodiment of FIG. 12 in that it further includes a conductive pattern layer 150 electrically connected to the semiconductor pattern 140.

The conductive pattern layer 150 may be formed on a layer different from the semiconductor pattern 140. At least one insulating layer may be interposed between the conductive pattern layer 150 and the semiconductor pattern 140. In an exemplary embodiment, the insulating film between the conductive pattern layer 150 and the semiconductor pattern 140 may be the first insulating film 130_1.

The conductive pattern layer 150 may be formed on the same layer as the dummy crossover line 124. In addition, the conductive pattern layer 150 may be formed of the same material as the dummy crossover line 124.

The conductive pattern layer 150 at least partially overlaps the first conductive pattern layer 150_1 and the fourth side 140_4 of the semiconductor pattern 140 at least partially overlapping the second side 140_2 of the semiconductor pattern 140. The overlapped second conductive pattern layer 150_2 may be included. The first conductive pattern layer 150_1 and the second conductive pattern layer 150_2 may be physically spaced apart from each other.

The first conductive pattern layer 150_1 and the second conductive pattern layer 150_2 may have an extension direction substantially parallel to the dummy crossover line 124, but are not limited thereto.

Contacts 151_1, 151_2, 151_3, and 151_4 are formed in regions where the conductive pattern layer 150 and the semiconductor pattern 140 overlap. The conductive pattern layer 150 and the semiconductor pattern 140 may be electrically connected to each other through the contacts 151_1, 151_2, 151_3, and 151_4. The contacts 151_1, 151_2, 151_3, and 151_4 may be formed by filling conductive materials in contact holes penetrating the first insulating layer 130_1 and the second insulating layer 130_2. The material of the contacts 151_1, 151_2, 151_3, and 151_4 may be the same as the material of the conductive pattern layer 150.

The electrostatic dispersion pattern 126, the semiconductor pattern 140, and the conductive pattern layer 150 may have a shape of a thin film transistor.

In the present exemplary embodiment, not only external static electricity introduced through the dummy pattern 122 is transferred to the semiconductor pattern 140, but also a part of the static electricity transferred to the semiconductor pattern 140 is contacts 151_1, 151_2, 151_3, and 151_4. Through it may be further transferred to the conductive pattern layer 150 side. Accordingly, the static electricity may be further dispersed to the conductive pattern layer 150, thereby effectively dispersing and reducing the amount of static electricity flowing into the display area DA through the dummy wiring 122. When the conductive pattern layer 150 is positioned in the non-display area NDA, even if static electricity is transferred to the conductive pattern layer 150, the influence on the overall organic light emitting display device is minimal. Although energy is concentrated in the conductive pattern layer 150 and both ends of the conductive pattern layer 150 are damaged, the impact on the overall organic light emitting display device may be small.

16 is a cross-sectional view illustrating a pixel area and an electrostatic dispersion area of an organic light emitting diode display according to an exemplary embodiment of the present invention. In FIG. 16, the electrostatic dispersion region has the same cross-sectional structure as that of FIG. 15 as an example. However, the electrostatic dispersion region may be replaced with other examples described above.

Referring to FIG. 16, a buffer layer 112 may be formed on the whole surface of the substrate 100. The buffer layer 112 may prevent diffusion of moisture or impurities penetrating from the substrate 110.

The semiconductor layer 142 is formed on the buffer layer 102 of the pixel region I, and the semiconductor pattern 140 is formed on the buffer layer 112 of the electrostatic dispersion region II. The semiconductor layer 142 may include a channel region overlapping the gate electrode 128 and a source / drain region doped with a high concentration of impurities at both ends of the channel region. The semiconductor layer 142 and the semiconductor pattern 140 may be formed of, for example, a polysilicon layer in which an amorphous silicon layer is crystallized.

The first insulating layer 130_1 may be formed on the semiconductor layer 142 and the semiconductor pattern 140. The first insulating layer 130_1 may be a gate insulating layer.

In the pixel region I, the gate electrode 128 may be formed on the first insulating layer 130_1. The gate electrode 128 may be formed to overlap the semiconductor layer 142. In addition, an electrostatic dispersion pattern 126 and a dummy pattern 122 may be formed on the first insulating layer 130_1 of the electrostatic dispersion region II. The electrostatic dispersion pattern 126 may be formed so that a portion thereof overlaps with the semiconductor pattern 140. The gate electrode 128, the electrostatic dispersion pattern 126, and the dummy pattern 122 may be formed on the same layer, respectively, and may be formed of the same material.

The second insulating layer 130_2 may be formed on the gate electrode 128, the electrostatic dispersion pattern 126, and the dummy pattern 122. The second insulating layer 130_2 may be an interlayer insulating layer.

The source electrode 154_1 and the drain electrode 154_2 may be formed on the second insulating layer 130_2 of the pixel region I. In addition, a first conductive pattern layer 150_1 and a second conductive pattern layer 150_2 may be formed on the second insulating layer 130_2 of the electrostatic dispersion region II. The source electrode 154_1 and the drain electrode 154_2 are connected to the lower semiconductor layer 142 through the contact holes 155_1 and 155_2 penetrating the second insulating film 130_2 and the first insulating film 130_1. The conductive pattern layer 150_1 and the second conductive pattern layer 150_2 may be connected to the lower semiconductor pattern 140 through the contact holes 151_1 and 151_3.

The source electrode 154_1 and the drain electrode 154_2, the first conductive pattern layer 150_1 and the second conductive pattern layer 150_2 may be formed on the same layer, respectively, and may be made of the same material.

The planarization layer 160 may be formed on the source electrode 154_1 and the drain electrode 154_2, the first conductive pattern layer 150_1, and the second conductive pattern layer 150_2.

The first electrode 170, which is a pixel electrode, is formed on the planarization layer 160 of the pixel region I. The first electrode 170 may be connected to the drain electrode 154_2 through the contact hole 162 provided in the planarization layer 160.

The pixel defining layer 180 may be formed on the first electrode 170. The pixel defining layer 180 may expose a portion of the first electrode 170. The organic emission layer 185 may be positioned on the first electrode 170 exposed by the pixel defining layer 180. The second electrode 190, which is a common electrode, may be formed on the organic emission layer 185. The second electrode 190 may extend to the static dispersion region II of the second electrode 190.

The first electrode 170 described above may be an anode electrode, and the second electrode 190 may be a cathode electrode. In contrast, the first electrode 170 may be a cathode electrode, and the second electrode 190 may be an anode electrode. .

In the OLED display, the first electrode 170 may be formed of a reflective conductive film, and the second electrode 190 may be formed of a transmissive conductive film. On the other hand, in the bottom emission type organic light emitting display device, the first electrode 170 may be formed of a transmissive conductive film, and the second electrode 190 may be formed of a reflective conductive film.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

100: organic light emitting diode display 110: substrate
122: dummy wiring 124: dummy cross wiring
126: electrostatic dispersion pattern 140: semiconductor pattern
150: conductive pattern layer

Claims (33)

Board;
First wiring formed on the substrate;
A second wiring insulated from and intersecting the first wiring; And
And an electrostatic dispersion pattern insulated from and intersecting the second wiring. The method according to claim 1,
And the first wiring is a substrate sidewall alignment wiring having at least one end aligned with the sidewall of the substrate. The method of claim 2,
The side of one end of the first wiring is disposed on the same plane as the side wall of the substrate. The method of claim 3,
The side of one end of the first wiring is perpendicular to one surface of the substrate. The method of claim 2,
The first wiring is a dummy wiring to which a driving signal is not applied. The method of claim 2,
One end of the first wiring and the sidewall of the substrate are formed by the same cutting process. The method according to claim 1,
The substrate includes a display area and a non-display area, wherein the electrostatic dispersion pattern is positioned in the non-display area. The method according to claim 1,
And the electrostatic dispersion pattern is spaced apart from the sidewalls of the substrate and is not aligned with the sidewalls of the substrate. The method according to claim 1,
And the first wiring and the electrostatic dispersion pattern are formed on the same layer. The method according to claim 1,
The electrostatic dispersion pattern has a rectangular shape and crosses the second wiring at a plurality of spots. The method according to claim 1,
And a semiconductor pattern insulated from and cross the electrostatic dispersion pattern. 12. The method of claim 11,
The semiconductor pattern may include a first side, a second side, a third side, and a fourth side,
Any one of the first to fourth sides is connected to at least the other. 12. The method of claim 11,
The organic light emitting display device of claim 1, wherein the electrostatic dispersion pattern and the semiconductor pattern cross each other on the outside of the second wiring in a direction close to the sidewall of the substrate with respect to the second wiring. 12. The method of claim 11,
The organic light emitting display device further comprises a conductive pattern layer connected to the semiconductor pattern. 15. The method of claim 14,
The conductive pattern layer is formed with the semiconductor pattern and the insulating layer interposed therebetween, and is connected to each other through a contact formed in the insulating layer. 16. The method of claim 15,
The conductive pattern layer is formed on the same layer as the second wiring. 17. The method of claim 16,
And the electrostatic dispersion pattern, the insulating film, the semiconductor pattern, and the conductive pattern layer constitute a thin film transistor. Board;
Gate lines and data lines formed on the substrate and insulated from and intersecting with each other;
A dummy wiring formed on the same layer as any one of the gate line and the data line, and at least one end of which is aligned with a sidewall of the substrate;
A dummy crossover wiring that is insulated from and crosses the dummy wire; And
And an electrostatic dispersion pattern insulated from and intersecting the dummy crossover wiring. 19. The method of claim 18,
The side of one end of the dummy wiring is disposed on the same plane as the side wall of the substrate. 20. The method of claim 19,
The side of one end of the dummy wiring is perpendicular to one surface of the substrate. 19. The method of claim 18,
One end of the dummy wiring and the sidewall of the substrate are formed by the same cutting process. 19. The method of claim 18,
And the electrostatic dispersion pattern is spaced apart from the sidewalls of the substrate and is not aligned with the sidewalls of the substrate. 19. The method of claim 18,
And the dummy wiring and the electrostatic dispersion pattern are formed on the same layer. 19. The method of claim 18,
And the dummy crossover line is formed on the same layer as the other one of the gate line and the data line. 19. The method of claim 18,
And a semiconductor pattern insulated from and cross the electrostatic dispersion pattern. 20. The method of claim 19,
The organic light emitting display device further comprises a conductive pattern layer connected to the semiconductor pattern. 21. The method of claim 20,
The conductive pattern layer is formed with the semiconductor pattern and the insulating layer interposed therebetween, and is connected to each other through a contact formed in the insulating layer. 22. The method of claim 21,
The conductive pattern layer is formed on the same layer as the dummy crossover line. 23. The method of claim 22,
And the electrostatic dispersion pattern, the insulating film, the semiconductor pattern, and the conductive pattern layer constitute a thin film transistor. Board;
First wiring formed on the substrate;
A second wiring insulated from and intersecting the first wiring;
An electrostatic dispersion pattern insulated from and intersecting with the second wiring and formed in a closed curve shape; And
And a semiconductor pattern insulated from and cross the electrostatic dispersion pattern. 31. The method of claim 30,
And a conductive pattern layer formed with the semiconductor pattern and the insulating layer therebetween and connected to the semiconductor pattern through a contact. 32. The method of claim 31,
The conductive pattern layer is formed on the same layer as the dummy crossover line. 31. The method of claim 30,
And the first wiring is a substrate sidewall alignment wiring having at least one end aligned with the sidewall of the substrate.

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