KR20120126442A - Method for forming pattern of Semiconductor Device - Google Patents

Abstract

PURPOSE: A pattern formation method of a semiconductor device is provided to easily form a micro-pattern less than 20nm by eliminating an undesirable pattern using a mask for blocking a desire pattern when forming the micro-pattern. CONSTITUTION: An oxide film and a nitride film are successively formed on a semiconductor substrate(300). A DSA(Direct Self-Assembly) pattern is formed on the nitride film. The DSA pattern comprises a main pattern and a dummy pattern. A nitride pattern is formed by etching the nitride film using the DSA pattern as an etching mask. A photosensitive pattern is formed on the upper side of the nitride pattern and the oxide film. A micro-pattern(315) is formed by etching the oxide film using the nitride pattern as the etching mask.

Description

Method for forming pattern of semiconductor device

The present invention relates to a method of forming a pattern of a semiconductor device, and to a method of forming a pattern by applying direct self-assembly (DSA).

BACKGROUND With the rapid spread of information media such as computers, semiconductor memory devices are also rapidly developing. In terms of its function, the semiconductor memory device must operate at a high speed and have a large storage capacity. In order to meet these demands, it is required to develop process equipment or process technology for manufacturing semiconductor memory devices having low manufacturing atoms, and having improved integration, reliability, and electrical characteristics for accessing data.

Photolithography is one of the methods for improving the degree of integration of semiconductor memory devices. Photolithography is a technique for exposing and developing a photoresist material with a deep ultra violet (DUV) light source, which is a short wavelength chemically amplified type such as ArF (193 nm) or VUV (157 nm), to form a fine pattern.

As semiconductor device sizes become smaller and smaller, controlling critical dimensions of pattern line widths has become an important issue when applying photolithography technology. In general, the speed of a semiconductor device is faster as the critical dimension of the pattern line width, that is, the size of the pattern line is smaller, and the performance of the device is also improved. However, it is difficult to form a line-and-space pattern of 40 nm or less in a single exposure process due to the limitation of photolithography technology using ArF exposure equipment having a numerical aperture of 1.2 or less. Accordingly, double patterning technology has been developed as part of resolution enhancement and process margin expansion of photolithography technology. Double patterning is a technique for exposing and developing two masks on a photoresist-coated wafer, respectively, to form complex patterns, dense patterns, and isolated patterns. .

On the other hand, since the double patterning technique uses two different masks for patterning, the manufacturing cost and turn-around-time are lower than the patterning technique using the single mask, resulting in lower throughput. . In addition, when forming a pattern having a pitch smaller than the resolution of the exposure equipment in the cell region, the aerial images are overlapped to obtain a pattern of a desired shape, and overlay misalignment at the time of alignment. There are several disadvantages such as this occurring.

In order to alleviate this drawback, double exposure etch technology (DEET) and spacer patterning technology (SPT) have been developed and applied to the semiconductor device mass production process. DEET is a technique of forming a first pattern having a line width twice as large as a desired pattern line width, and then forming a second pattern having the same line width period as the first pattern between neighboring first patterns.

However, since the DEET method uses two kinds of masks or one mask to form a pattern having a desired resolution, the process step is complicated, manufacturing costs are increased, and the alignment of the pattern when forming the second photoresist pattern is achieved. Misalignment is likely to occur in the process.

Another technique, the SPT method, is a technique in which a self-align method is applied to prevent misalignment by performing a mask process only once to form a pattern of a cell region. However, the process step is complicated because an additional mask process is required to form a pattern in the core and peri regions or to separate the pattern portion of the mini cell block region. Since it is difficult to control the line width, the uniformity of the fine pattern line width in the semiconductor device determined by the line width of the spacer is low.

As described above, the method of manufacturing a semiconductor device according to the prior art has a problem that it is difficult to pattern to a fine 20 nm or less by the exposure equipment and the patterning method that are already commercialized.

In order to solve the above-mentioned conventional problems, the present invention forms a fine pattern by applying DSA (Direct Self-Assembly), but when forming the fine pattern, by removing the unwanted pattern using a mask to shield the desired pattern 20nm The manufacturing method of the semiconductor element which can form the following fine patterns is provided.

The present invention provides a method of forming a neutral material on a semiconductor substrate having an insulating film on a lower layer, forming a guide pattern on the neutral material, and forming a patterned copolymer between the guide patterns. Forming an insulating layer pattern by etching the insulating layer using a copolymer as a mask, wherein the insulating layer pattern includes a main pattern and a dummy pattern, and etching the lower layer using the main pattern as an etching mask. Provided is a method of manufacturing a device.

Preferably, the method may further include removing the exposed dummy pattern by using the dummy pattern as a mask for exposing the insulating layer pattern.

Preferably, the forming of the patterned copolymer may include embedding a copolymer including a hydrophobic material and a hydrophilic material between the guide patterns and aligning the copolymer with the hydrophobic material and the hydrophilic material. It is characterized by including.

Preferably, the step of aligning the copolymer is characterized in that the baking of the copolymer.

In addition, the present invention is a step of forming a first guide pattern on a semiconductor substrate having an insulating film on the lower layer, the first guide pattern and forming a neutral material on the semiconductor substrate, the first guide pattern and the Etching a neutral material to form a second guide pattern and a neutral material pattern, forming a patterned copolymer on the second guide pattern and the neutral material pattern, and forming the insulating film using the patterned copolymer as a mask Etching to form an insulating film pattern, the insulating film pattern provides a method for manufacturing a semiconductor device comprising the step of including a main pattern and a dummy pattern and etching the lower layer using the main pattern as an etching mask.

Preferably, the method may further include removing the exposed dummy pattern by using the dummy pattern as a mask for exposing the insulating layer pattern.

Preferably, forming the patterned copolymer comprises aligning the copolymer with the hydrophobic material and the hydrophilic material.

Preferably, the step of aligning the copolymer is characterized in that the baking of the copolymer.

According to the present invention, a fine pattern is formed by applying DSA (Direct Self-Assembly), but when forming a fine pattern, a fine pattern of 20 nm or less can be formed by removing an unwanted pattern by using a mask that shields a desired pattern. There is this.

1A to 1C are cross-sectional views illustrating a method of manufacturing a direct self-assembly (DSA) pattern according to an embodiment of the present invention.
2A to 2D are cross-sectional views illustrating a method of manufacturing a direct self-assembly (DSA) pattern according to another embodiment of the present invention.
3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings.

1A to 1C are cross-sectional views illustrating a method of manufacturing a direct self-assembly (DSA) pattern according to an embodiment of the present invention.

Referring to FIG. 1A, a neutral material 110 is formed on a semiconductor substrate 100. In this case, the neutral material 110 may neutralize the semiconductor substrate 100.

Referring to FIG. 1B, after the photoresist film is formed on the neutral material 110, the photoresist pattern 120 is formed by an exposure and development process using a guide pattern mask. In this case, the hard mask layer or the anti-reflection coating may be used instead of the photoresist pattern 120.

Referring to FIG. 1C, a DSA (Direct Self-Assembly) material is coated between the photoresist pattern 120 and then baked to form a DSA pattern 130. In this case, the DSA material may include a polymer (Block Copolymer, BCP). Here, the polymer comprises two materials. PS 140 and PMMA 150, PS 140 and PMMA 150 is characterized in that the self-aligned in various forms according to the composition ratio. Such polymers are preferably self-aligned at regular intervals, but are preferably used in a technique for fine patterning by having regularity.

2A to 2D are cross-sectional views illustrating a method of manufacturing a direct self-assembly (DSA) pattern according to another embodiment of the present invention.

Referring to FIG. 2A, after the photoresist film is formed on the semiconductor substrate 200, the photoresist pattern 210 is formed by an exposure and development process using a guide pattern mask. In this case, the hard mask layer or the anti-reflection coating may be used instead of the photoresist pattern 210.

Referring to FIG. 2B, a neutral material 220 is formed on the photoresist pattern 210 and the semiconductor substrate 200. In this case, the neutral material 220 preferably serves to neutralize the semiconductor substrate 200.

Referring to FIG. 2C, the neutral material 220 and the photoresist pattern 210 may be partially etched to form the neutral material pattern 225 and the photoresist pattern 210 ′. Here, the semiconductor substrate 200 under the neutral material pattern 225 is neutralized, and the photoresist pattern 210 'has a hydrophilic property by the OH- group.

Referring to FIG. 2D, a DSA (Direct Self-Assembly) material is coated on the neutral material pattern 225 and the photoresist pattern 210 'and then baked to form a DSA pattern 230. In this case, the DSA material may include a polymer (Block Copolymer, BCP). Here, the polymer comprises two materials. PS 240 and PMMA 250, PS 240 has a hydrophobic property, and since the PMMA 250 has a hydrophilic property, it is characterized in that the self-aligned in various forms according to the composition ratio. Such polymers are self-aligned at regular intervals, but have a regularity and are used in the fine patterning method. Specifically, since the photoresist pattern 210 'has a hydrophilic property, when the DSA material is applied, the PMMA 250 is aligned on top of the photoresist pattern 210', and since the PS 240 has a hydrophobic property, the DSA material has a hydrophobic property. Upon application, it is aligned on top of the neutral pattern 225.

3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Referring to FIG. 3A, an oxide film 310 and a nitride film 320 are sequentially formed on the semiconductor substrate 300.

Next, a DSA (Direct Method) according to one embodiment (a method of manufacturing a semiconductor device according to FIGS. 1A to 1C) or another embodiment (a method of manufacturing a semiconductor device according to FIGS. 2A to 2D) is disposed on an upper surface of the nitride film 320. The DSA pattern 330 is formed using a self-assembly method. Here, the DSA pattern 330 includes a main pattern 340 and a dummy pattern 350. Here, the dummy pattern 350 includes an unwanted pattern or a pattern to be removed in the manufacturing process.

Referring to FIG. 3B, the nitride layer 320 is etched using the DSA pattern 330 as an etch mask to form the nitride layer pattern 325. In this case, the nitride film pattern 325 includes a main nitride film pattern 335 and a dummy nitride film pattern 345.

Referring to FIG. 3C, after the photoresist film is formed on the nitride film pattern 325 and the oxide film 310, the photoresist film pattern is exposed and developed using a mask 360 that shields an area other than the dummy nitride film pattern 345. Form 360 '. The dummy nitride film pattern 345 is removed using the photoresist pattern 360 'as an etching mask.

Referring to FIG. 3D, the oxide layer 310 is etched using the main nitride layer pattern 335 as an etch mask to form a fine pattern 315.

As described above, the present invention forms a fine pattern by applying DSA (Direct Self-Assembly), but when forming the fine pattern, by removing the unwanted pattern using a mask to shield the desired pattern to remove the fine pattern of 20nm or less There is an advantage that can be formed.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

Claims (8)

Forming a neutral material on a semiconductor substrate having an insulating film on a lower layer;
Forming a guide pattern on the neutral material;
Forming a patterned copolymer between the guide patterns;
Etching the insulating film using the patterned copolymer as a mask to form an insulating film pattern, wherein the insulating film pattern includes a main pattern and a dummy pattern; And
Etching the lower layer using the main pattern as an etching mask
And forming a second insulating film on the semiconductor substrate. The method according to claim 1,
After forming the insulating film pattern,
And removing the exposed dummy pattern by using the dummy pattern as a mask for exposing the dummy pattern. The method according to claim 1,
Forming the patterned copolymer is
Embedding a copolymer including a hydrophobic material and a hydrophilic material between the guide patterns; And
And aligning the copolymer with the hydrophobic material and the hydrophilic material. The method according to claim 3,
Aligning the copolymer is a method of manufacturing a semiconductor device, characterized in that for baking the copolymer. Forming a first guide pattern on a semiconductor substrate having an insulating film on a lower layer;
Forming a neutral material on the first guide pattern and the semiconductor substrate;
Etching the first guide pattern and the neutral material to form a second guide pattern and the neutral material pattern;
Forming a patterned copolymer on the second guide pattern and the neutral material pattern;
Etching the insulating film using the patterned copolymer as a mask to form an insulating film pattern, wherein the insulating film pattern includes a main pattern and a dummy pattern; And
Etching the lower layer using the main pattern as an etching mask
And forming a second insulating film on the semiconductor substrate. The method according to claim 5,
After forming the insulating film pattern,
And removing the exposed dummy pattern by using the dummy pattern as a mask for exposing the dummy pattern. The method according to claim 5,
Forming the patterned copolymer is
And aligning the copolymer with the hydrophobic material and the hydrophilic material. The method of claim 7,
Aligning the copolymer is a method of manufacturing a semiconductor device, characterized in that for baking the copolymer.

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