KR20120125148A - Package-on-package assembly with wire bonds to encapsulation surface - Google Patents

Abstract

PURPOSE: A package stack type assembly is provided to perform operation of assembly at high speed and to limit signaling time between devices. CONSTITUTION: A substrate(12) has a first side(14) and a second side(16) which is separate from the first side. A microelectronic element(22) is located on the first side of the substrate within a first area. A conductive element(28) is electrically connected to the microelectronic element. The conductive element is arranged as a first array of a first configuration. The conductive element is exposed to one or more sides of the first side and the second side within a second area. A wire bond comprises an end side which is separated from a base.

Description

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE}

The present invention relates to a microelectronic package.

Microelectronic devices, such as semiconductor chips, typically require many input and output connections to connect to other electronic components. The input and output contacts of a semiconductor chip or similar device are generally a grid-like pattern (commonly referred to as an "area array") that substantially covers the surface of the device. Or in rows extending in a row that may extend parallel to each edge of the front face of the device and adjacent to each edge of the front face of these devices, or in the center of the front face. Typically, a device such as a semiconductor chip must be physically mounted on a substrate such as a printed circuit board, and the contact of the device must be electrically connected to an electrically conductive element of the circuit board.

The semiconductor chip is generally provided in a package form to facilitate handling of the semiconductor chip during the manufacturing process and during mounting the semiconductor chip on an external substrate such as a circuit board or another circuit panel. For example, many semiconductor chips are provided in a package suitable for surface mounting. Many packages of this general type have been proposed for various purposes. Most commonly, such a package includes a dielectric element, commonly referred to as a "chip carrier," which is a terminal formed as a metal structure that is plated or etched on the dielectric. ). These terminals are typically connected to the contacts of the chip itself by elements such as thin traces extending along the chip carrier and by leads or wires extending between the contacts of the chip and the terminals or traces. In a surface mount process, a package is placed on a circuit board such that each terminal on the package is aligned with a corresponding contact pad on the circuit board. Solder or other bonding material is provided between the terminal and the contact pad. The package can be permanently bonded in place by heating the assembly to melt or “reflow” the solder, or otherwise activate the bonding material.

In many packages, solder mass is attached to the terminals of the package, typically in the form of solder balls that are typically between about 0.1 mm and about 0.8 mm [5 to 30 mils] in diameter. Packages having solder balls in the form of arrays protruding from the bottom side of the package are generally referred to as ball grid array (BGA) packages. To the substrate, another package, called a land grid array (“LGA”) package, is fixedly attached by a thin layer or land formed of solder. This type of package can be made very compact. The area that a given package, generally referred to as a "chip scale package", occupies on the circuit board is equal to or slightly larger than the area of the device contained within the package. This reduces the overall size of the assembly, has the advantage of shortening the connection between the various elements on the substrate, and can limit the signal propagation time between the elements, thereby enabling the operation of the assembly at high speed. Will be.

Packaged semiconductor chips are often provided in a "stacked" configuration, in which one package is provided on a circuit board, for example, and the other package is mounted on top of the first package. This arrangement allows for the mounting of multiple different chips in a single footprint on a circuit board, enabling high speed operation with only short interconnections between packages. In many cases, this interconnect distance is slightly larger than the thickness of the chip itself. For interconnections to be achieved within the stack structure of the chip package, it is necessary to provide structures for mechanical and electrical connections on both sides of each package (except for the top of the package). This configuration is achieved by providing contact pads or lands on both sides of the substrate on which the chip is mounted, and the contact pads are connected through the substrate by conductive vias or the like. Solder balls and the like have been used to bridge the gap between the contacts at the top of the lower substrate to the contacts at the bottom of the upper substrate. The solder ball must be higher than the height of the chip to connect the contacts. Examples of stacked chip configurations and interconnect structures are disclosed in US Patent Application No. 2010/0232129, which is incorporated herein by reference.

Microcontact elements in the form of elongated posts or pins are used to connect a microelectronic package to a circuit board and may be used for other connections in microelectronic packaging. In some cases, microcontacts have been formed by etching metal structures comprising one or more metallic layers. This etching process limits the size of the microcontacts. With conventional etching processes, it is not possible to form microcontacts with a ratio of height to maximum width, referred to herein as an "aspect ratio." It has been difficult or impossible to form an array of microcontacts with significant heights and very small pitches or spaces between neighboring microcontacts. In addition, the configuration of the microcontact formed by the conventional etching process is limited.

Despite these advances in the art, there are further improvements in manufacturing and testing microelectronic packages.

Embodiments of the present invention relate to microelectronic packages. The microelectronic package includes a substrate having a first region, a second region, a first surface, and a second surface spaced apart from the first surface. One or more microelectronic elements are located above the first face in the first region. The electrically conductive element is exposed to one or more of the first and second sides of the substrate in the second region, and at least a portion of the conductive element is electrically connected to the one or more microelectronic elements. The microelectronic package each has a base bonded to each of the electrically conductive elements, an end surface spaced from the substrate and the base, and an edge surface extending between the base and the end surface. It further comprises a wire bond. A dielectric encapsulation layer extends from one or more of the first and second faces and fills the space between the wire bonds so that the wire bonds are separated from each other. The encapsulation layer is positioned over at least the second region of the substrate, and the unencapsulated portions of the wire bond consist of at least portions of the end face of the wire bond not covered by the encapsulation layer. The substrate may be a lead frame and the conductive element may be a lead in the lead frame.

The unencapsulated portion of the wire bond may consist of an end face of the wire bond and an edge face adjacent to the end face that is not covered by the encapsulation layer. The microelectronic package can further include an oxidation protection layer in contact with at least a portion of the unencapsulated portion of the wire bond. The portion adjacent to the end face of the wire bond of one or more of the wire bonds may be adapted to be substantially perpendicular to the surface of the encapsulation layer. The conductive element can be a first conductive element and the microelectronic package can further include a plurality of second conductive elements electrically connected to the unencapsulated portion of the wire bond. In such an embodiment, the second conductive element may be brought into contact with the first conductive element. The second conductive element may comprise a plurality of stud bumps bonded to the end faces of at least some of the first wire bonds.

One or more of the wire bonds may extend substantially straight between the base of the wire bond and the unencapsulated portion of the wire bond, the substantially straight lines making an angle of less than 90 degrees with respect to the first side of the substrate. Can be. Additionally or alternatively, the edge face of the one or more wire bonds of the wire bond may comprise a first portion neighboring the end face and a second portion separated from the end face by the first portion, the first portion being The second portion may extend in a direction away from the extending direction.

Another embodiment of the invention is directed to a replaceable microelectronic package. Such a microelectronic package includes a substrate having a first region, a second region, a first side, and a second side spaced from the first side. One or more microelectronic elements are located above the first face in the first region. The electrically conductive element is exposed to one or more of the first and second sides of the substrate in the second region, at least a portion of the conductive element being electrically connected to the one or more microelectronic elements. The microelectronic package has a plurality of bases bonded to each of the electrically conductive elements, a substrate and end surfaces spaced from the base, and a plurality of edge surfaces extending between the base and the end surfaces. It further comprises a wire bond. A dielectric encapsulation layer extends from one or more of the first and second faces and fills the space between the wire bonds so that the wire bonds are separated from each other. The encapsulation layer is positioned over at least the second region of the substrate, and the unencapsulated portions of the wire bond consist of at least the portion of the edge face adjacent to the end face of the wire bond not covered by the encapsulation layer.

The encapsulation layer may be a monolithic layer formed on the substrate by depositing a dielectric material on the first substrate and curing the deposited dielectric material after forming the wire bond. Can be. Formation of the integral encapsulation layer may include a process of molding the dielectric material.

One or more portions of the unencapsulated portion may consist of a portion of the end face not covered by at least the encapsulation layer. The portion not covered by the encapsulation layer of the edge face may be the longest in the portion extending in a direction substantially parallel to the surface of the encapsulation layer. The length of the portion not covered by the encapsulation layer of the edge face and extending substantially parallel to the surface of the encapsulation layer may be larger than the width of the cross section of the wire bond.

Among the above-mentioned embodiments, the first face of the substrate may extend in a first lateral direction and a second lateral direction, wherein the first and second lateral directions are between the first and second faces of the substrate. It is to cross the direction of the thickness of. The unencapsulated portion of the one or more wire bonds of the wire bond may be displaced in one or more of the first lateral direction and the second lateral direction from the conductive element to which the one or more wire bonds are bonded. One or more of the wire bonds may comprise a substantially curved portion between the base and the end face of the wire bond. The unencapsulated portion of the one or more wire bonds may be located on the major surface of the microelectronic element.

In the above-mentioned embodiments, solder balls may be joined to an unencapsulated portion of one or more of the wire bonds.

In addition, in the aforementioned embodiments, the encapsulation layer may include one or more surfaces, and the unencapsulated portion of the wire bond need not be covered by the encapsulation layer on one of the one or more surfaces. . One or more surfaces of the encapsulation layer may include a major surface that is substantially parallel to the first side of the substrate, wherein an unencapsulated portion of the one or more wire bonds of the wire bond is connected to the encapsulation layer at the major surface. It does not have to be covered by it. The unencapsulated portion of the one or more wire bonds may have substantially the same height as the major surface. As an alternative to this, the unencapsulated portion of the one or more wire bonds may extend above the major surface. The one or more surfaces of the encapsulation layer may include a major surface separated by a first distance from the first side of the substrate and a recessed surface separated by a distance shorter than the first distance from the first side of the substrate, The unencapsulated portion of the wire bond does not have to be covered by the encapsulation layer on the concave side. One or more surfaces of the encapsulation layer may include sides that extend at a substantial angle from the first side in a direction away from the first side of the substrate, wherein the unencapsulated portion of the one or more wire bonds It does not have to be covered by the encapsulation layer at. The encapsulation layer may have a cavity therein, the cavity extending from the surface of the encapsulation layer towards the substrate, and an unencapsulated portion of one or more of the wire bonds may be located in the cavity.

In addition, among the above-mentioned embodiments, the wire bond may essentially include one or more materials selected from the group consisting of copper, gold, aluminum, and solder. One or more of the wire bonds may define a longitudinal axis along the length of the wire bond, wherein the wire bond is spaced apart from the longitudinal axis with an inner layer of the first material extending along the longitudinal axis. And may each include an outer layer of a second material having a length extending in the long direction of the wire bond. In such an embodiment, the first material may comprise one of copper, gold, nickel, and aluminum, and the second material may comprise one of copper, gold, nickel, aluminum, and solder.

In the above-mentioned embodiments, the plurality of wire bonds may be first wire bonds, the microelectronic package having one or more second wire bonds having a base bonded to a contact on the microelectronic element and an end face spaced from the contact. It may further include. The one or more second wire bonds can include an edge face extending between the base and the end face, wherein an unencapsulated portion of the one or more second wire bonds is in the end face of the second wire bond or in the edge face of the second wire bond. It may consist of an uncovered portion of one or more sides by an encapsulation layer. The one or more microelectronic elements can be a first microelectronic element and the microelectronic package can further include one or more second microelectronic elements located at least partially on the first microelectronic element. In such embodiments, the wire bond may be a first wire bond, and the microelectronic package includes a base bonded to a contact on the microelectronic element and one or more second wire bonds having end faces spaced from the contact, one The second wire bond may comprise an edge face between the base and the end face, wherein an unencapsulated portion of the second wire bond is selected from a portion of the end face of the second wire bond or a portion of the edge face of the second wire bond. It may consist of a part which is not covered by the encapsulation layer.

In the above embodiment, the first wire bond in the wire bond delivers a first signal electric potential, and at the same time the second wire bond in the wire bond delivers a second signal potential different from the first signal potential. Can be.

Any of the above embodiments may further comprise a redistribution layer extending along the surface of the encapsulation layer. The rearrangement layer is exposed to a redistribution substrate having a first side adjacent to the major surface of the encapsulation layer, a second side spaced from the first side, the first side of the rearrangement substrate and not encapsulated in the wire bond. And a first conductive pad aligned with the non-engaged portion and mechanically connected to the unencapsulated portion, and a second conductive pad exposed on the second side of the substrate and electrically connected to the first conductive pad.

In another embodiment, the microelectronic assembly may comprise a first microelectronic package according to any of the above embodiments. The microelectronic assembly can also include a second microelectronic package having a substrate having a first side and a second side. The second microelectronic element may be mounted on the first side and the contact pad may be exposed on the second side and electrically connected to the second microelectronic element. The second microelectronic package is mounted to the first microelectronic package, wherein a second side of the second microelectronic package is positioned over at least a portion of the surface of the dielectric encapsulation layer, and at least a portion of the contact pad is an unencapsulated portion of the wire bond. The second microelectronic package can be mounted to the first microelectronic package so as to be electrically and mechanically connected to at least a portion thereof.

Another embodiment of the invention includes a microelectronic substrate comprising a substrate having a first region, a second region, a first surface, and a second surface spaced from the first surface and extending in a lateral direction. It's about packages. The microelectronic element is located above the first face in the first region and has a major surface spaced from the substrate. The electrically conductive element is exposed to the first side of the substrate in the second region, and at least a portion of the conductive element is electrically connected to the microelectronic element. The microelectronic package each has a base bonded to each of the electrically conductive elements, an end surface spaced from the substrate and the base, and an edge surface extending between the base and the end surface. Wire bonds. A dielectric encapsulation layer extends from one or more of the first and second faces, fills the space between the wire bonds so that the wire bonds are separated from each other, and over the at least second region of the substrate. Located. The unencapsulated portions of the wire bond consist of at least one of the end faces of the wire bond not covered by the encapsulation layer. The unencapsulated portion of the at least one wire bond is located in at least one lateral direction along the first face from the conductive element to which the at least one wire bond is bonded, wherein the unencapsulated portion of the wire bond is located on the major surface of the microelectronic element. Displaced to

The conductive elements may be disposed in a first array of a first predetermined configuration, and the unencapsulated portion of the wire bond may be disposed in a second array of a second predetermined predetermined configuration that is different from the first configuration. The array of the first configuration may have a first pitch, and the array of the second configuration may have a second pitch that is finer than the first pitch. The microelectronic package can further include an insulating layer extending over at least the surface of the microelectronic element. An insulating layer can be disposed between the surface of the microelectronic element and one or more wire bonds having portions that are not encapsulated on the major surface of the microelectronic element. Multiple unencapsulated portions of the wire bond can be located on the major surface of the microelectronic element.

The microelectronic assembly according to the embodiment of the present invention may include the first microelectronic package according to the embodiment. A microelectronic assembly of the present invention includes a substrate having a first side and a second side, a second microelectronic element attached on the first side, and a contact pad exposed on the second side and electrically connected to the microelectronic element. It can include a microelectronic package. The second microelectronic package is attached onto the first microelectronic package, such that the second side of the second microelectronic package is located on at least a portion of the surface of the dielectric encapsulation layer, and at least a portion of the contact pad is disposed of the wire bond. A second microelectronic package can be attached on the first microelectronic package to be electrically and mechanically connected to at least a portion of the unencapsulated portion.

The electrically conductive elements of the first microelectronic package can be arranged in a first array of a first predetermined configuration, and the contact pads of the second microelectronic package are arranged in a second array of a second predetermined predetermined configuration that is different from the first configuration. Can be. At least some of the unencapsulated portions of the wire bonds of the first microelectronic package may be disposed in a third array corresponding to the array of the second configuration. The array of the first configuration may have a first pitch, and the array of the second configuration may have a second pitch that is finer than the first pitch.

Another embodiment of the invention is directed to a method of manufacturing a microelectronic package. The method includes forming a dielectric encapsulation layer on an in-process unit. The in-process unit includes a substrate having a first face and a second face spaced from the first face, a microelectronic element mounted on the first face of the substrate, and a plurality of conductive elements exposed on the first face. At least a portion of the conductive element is electrically connected to the microelectronic element. The inprocessor unit includes a wire bond having a base bonded to the conductive element, an end face spaced from the base, and an edge face extending between the base and the end face. The encapsulation layer is configured to at least partially cover the first face and a portion of the wire bond, and wherein the unencapsulated portions of the wire bond are at least one of the end face or edge face of the wire bond to the encapsulation layer. It is formed to be made of a portion that is not covered by. The substrate of the in-process unit can be a lead frame and the conductive element can be a lead in the lead frame. Stud bumps may be formed on the unencapsulated portion of one or more of the wire bonds. Solder balls may be deposited on the unencapsulated portion of one or more of the wire bonds.

Forming an encapsulation layer includes forming a dielectric material mass on substantially both of the first face and the wire bond, and the unencapsulated portion of the wire bond such that a portion of the wire bond is not covered. May comprise removing a portion of the dielectric material mass to form a. As a variant, one or more wire bonds of the wire bond can each be joined to two or more of the conductive elements and extend in the form of a loop. The dielectric material mass may be formed to at least partially cover the one or more wire bond loops and the first side. Removing a portion of the dielectric material mass may include one or more wire bond loops, each having a free end uncoated by an encapsulation layer to form an unencapsulated portion of the wire bond. And removing a portion of the one or more wire bond loops to cut into. The loop includes bonding the first end of the wire to the conductive element, drawing the wire away from the first face, drawing the wire at least in a lateral direction along the first face, and drawing the wire to the second conductive edge. By drawing up the element and bonding it to the second conductive element.

The encapsulation layer is formed on the in-process unit by pressing the dielectric material mass to contact the first surface of the substrate from a location away from the substrate over the wire bond, and allowing at least one wire bond through the dielectric material mass to penetrate the dielectric material mass. Can be. The wire bond may consist of a wire bond substantially comprising gold, copper, aluminum, or solder. The first wire bond may comprise aluminum and the wire bond may be bonded to the conductive element by wedge bonding. Forming the encapsulation layer may further or alternatively include forming one or more cavities extending from the major surface of the encapsulation layer towards the substrate. One or more cavities can be formed by depositing a dielectric encapsulation material on a substrate, followed by etching the encapsulation material by one or more of wet etching, dry etching, or laser etching. One or more cavities may be formed by depositing a dielectric encapsulation material on a substrate and one or more wire bonds, then removing at least a portion of the sacrificial material from a predetermined location of one or more wire bonds of the wire bonds. Forming the encapsulation layer causes a portion of the sacrificial material to be exposed on the major surface of the encapsulation layer, allowing the exposed portion of the sacrificial material to surround a portion of the wire bond near the free end of the wire bond, It can be done by spacing some away from the wire bond. One or more of the wire bonds may define a longitudinal axis along the length of the wire bond, wherein the wire bond is spaced apart from the inner layer of the first material extending along the longitudinal axis and extending along the length of the wire bond. And an outer layer of the second material. The first portion of the sacrificial material may be removed to form a cavity, and the second portion of the sacrificial material may remain adjacent to the base.

The first side of the substrate may extend in the lateral direction and the unencapsulated portion of the one or more wire bonds of the wire bond may be formed such that the one or more wire bonds are displaced in one or more lateral directions from the bonded conductive element. . Accordingly, the in-process unit can be formed including forming a wire bond such that at least one of the wire bonds comprises a substantially curved portion located between the conductive element and the end face of the at least one wire bond.

As another variant, the substrate may comprise a first region and a second region, and the microelectronic element may be located above the first region and have a major surface spaced from the substrate. The first conductive element is located in the second region, and the in-process unit may be formed by forming a wire bond such that at least a portion of the one or more wire bonds extend above the major surface of the microelectronic element.

The wire bond may define a longitudinal axis along the length of the wire bond, the wire bond of the second material spaced from the longitudinal direction of the first material extending along the longitudinal axis and extending along the length of the wire bond. It may include an outer layer. In this modification, the first material may be copper and the second material may be solder. A portion of the second material may be removed after forming the encapsulation layer to form a cavity extending from the surface of the dielectric encapsulation layer, such that a portion of the edge face of the inner layer of the wire bond is not covered.

Another embodiment of the invention is directed to a microelectronic package comprising a substrate having a first region, a second region, a first side, and a second side spaced from the first side. One or more microelectronic elements are located above the first face in the first region. The electrically conductive element is exposed to the first side of the substrate in the second region, and at least a portion of the conductive element is electrically connected to one or more microelectronic elements. The plurality of bond elements each have a first base, a second base, and an edge face extending between the bases. The first base is bonded to one of the conductive elements. The edge face further comprises a first portion extending away from the contact pad to a vertex of the edge face spaced from the substrate, the edge face further comprising a second portion extending from the vertex to the second base, the second base being the substrate Is bonded to the elements of. A dielectric encapsulation layer extends from one or more of the first and second faces, and between and between the first and second portions of the plurality of bond elements such that the bond elements are separated from each other. It fills a space between and is located above at least a second area of the substrate. The unencapsulated portions of the bond element consist of at least the portion of the end face of the bond element surrounding the vertex that is not covered by the encapsulation layer.

As a variant of the above embodiment, the bond element is a wire bond. In this variant, the element of the substrate to which the second base of the substrate is bonded may be the conductive element to which the first base is bonded. As an alternative, the element of the substrate to which the second base of the substrate is bonded may be a different conductive element than the conductive element to which the first base is bonded. The conductive element to which the second base is bonded does not have to be electrically connected to the microelectronic element. As an alternative variant, the bond element can be a bond ribbon. In this variant, a portion of the first base may extend along a portion of the contact pad and the element to which the second base is bonded may be the length portion of the first base extending along the portion of the contact pad.

In this embodiment, the first side of the substrate may extend in the first lateral direction and the second lateral direction, wherein the first and second lateral directions are of the thickness of the substrate between the first side and the second side. It may be a direction crossing the direction. The unencapsulated portion of one or more wire bonds of the wire bond can be displaced in one or more of the first and second lateral directions from the conductive element to which the one or more wire bonds are bonded. In addition, the unencapsulated portion of the one or more wire bonds may be located on the major surface of the microelectronic element.

Another embodiment of the invention is directed to a method of manufacturing a microelectronic package. The embodiment includes bonding the first microelectronic package manufactured by the above embodiment to a second microelectronic package, wherein the second microelectronic package comprises a substrate having a first side, and a substrate of the substrate. Comprising a plurality of contacts exposed on one side, and bonding the first microelectronic package to the second microelectronic package, wherein the unencapsulated portion of the wire bond of the first microelectronic package is contacted with the second microelectronic package. And electrical and mechanical connection.

Another embodiment of the invention is directed to another method of manufacturing a microelectronic package. The method of the present embodiment includes a substrate having a first face and a second face spaced from the first face, a plurality of thin conductive elements exposed on the first face, and a base spaced from the base, the base and the substrate bonded to the conductive element. Positioning a dielectric material mass on an in-process unit comprising a face and a wire bond having an edge face extending between the base and the end face. The method also includes pressing the dielectric material mass on the wire bond to contact the first side of the substrate and forming an encapsulation layer on the in-process unit such that the wire bond penetrates the dielectric material mass. Accordingly, the encapsulation layer fills the space between the wire bonds so that the wire bonds are separated from each other and forms an encapsulation layer such that the encapsulation layer is positioned over at least the second region of the substrate. The unencapsulated portion of the first wire bond is formed by a wire bond extending through a portion of the encapsulation layer such that a portion of the first wire bond is not covered by the encapsulation layer.

Yet another embodiment of the present invention is directed to another method of manufacturing a microelectronic package. The method of this embodiment includes a substrate having a first side and a second side spaced from the first side, a plurality of thin conductive elements exposed on the first side, and at least two conductive elements of the conductive element are formed in the first base and the second side. Forming a dielectric encapsulation layer on an in-process unit that includes a wire loop each bonded to a base. The encapsulation layer is formed to at least partially cover the first face and the one or more wire loops. The method also includes part of the wire loop and part of the encapsulation layer and part of the wire loop such that the wire loop is cut into individual wire loops corresponding to the first base and the second base, respectively, and having end faces spaced from the substrate and the base. Removing the step. As such, the wire bonds constitute an edge face extending between the base and the end face. The encapsulation layer fills the space between the wire bonds such that the wire bonds are separated from each other, the wire bond having an unencapsulated portion formed by the free end of the wire bond that is not at least partially covered by the encapsulation layer.

Another embodiment of the invention is directed to a system comprising a microelectronic package or assembly according to one of the aforementioned embodiments and at least one electronic component electrically connected to the microelectronic package. The system further includes a housing, in which a microelectronic package or assembly and other electronic components can be installed in the housing.

1 shows a microelectronic package according to an embodiment of the present invention.
FIG. 2 is a top view of the microelectronic package of FIG. 1.
3 shows a microelectronic package according to another embodiment of the present invention.
4 illustrates a microelectronic package according to another embodiment of the present invention.
5 shows a microelectronic package according to another embodiment of the present invention.
6 illustrates a stacked microelectronic assembly including a microelectronic package according to an embodiment of the present invention.
7 illustrates a microelectronic package according to another embodiment of the present invention.
8A-8E show some details of a microelectronic package according to various embodiments of the present invention.
9 shows a detail of a microelectronic package according to another embodiment of the present invention.
10A-10D show some details of a microelectronic package according to various embodiments of the present invention.
11-14 illustrate various manufacturing steps of a microelectronic package according to an embodiment of the present invention.
15 shows a manufacturing step of a microelectronic package according to another embodiment of the present invention.
16A-16C show some of the details in various stages of fabrication of a microelectronic package according to an embodiment of the invention.
17A-17C illustrate some of the details in various stages of fabrication of a microelectronic package according to another embodiment of the invention.
18 is a top view of a microelectronic package according to another embodiment of the present invention.
19 is a top view of a portion of a microelectronic package according to another embodiment of the present invention.
20 is a top view of a microelectronic package according to another embodiment of the present invention.
FIG. 21 shows a front view of the microelectronic package of FIG. 20.
22 is a front view of a microelectronic package according to another embodiment of the present invention.
23 shows a system according to another embodiment of the present invention.
24 is a front view of a microelectronic package according to another embodiment of the present invention.
25 is a front view of a microelectronic package according to another embodiment of the present invention.
FIG. 26 illustrates a top surface of a microelectronic package according to a modification of the embodiment of FIG. 25.
27 is a front view of a microelectronic package according to another embodiment of the present invention.
FIG. 28 illustrates a top view of a microelectronic package according to a modification of the embodiment of FIG. 27.

Referring to the drawings, like reference numerals refer to like elements. 1 shows a microelectronic assembly 10 according to an embodiment of the invention. 1 is a microelectronic assembly comprised of packaged microelectronic elements, such as semiconductor chip assemblies used in computers and other electronic devices.

The microelectronic assembly 10 of FIG. 1 includes a substrate 12 having a first side 14 and a second side 16. Substrate 12 typically consists of a substantially flat dielectric element. The dielectric element can be sheet-like and thin. In one example, the dielectric element may be made of polyimide, polytetrafluoroethylene ("PTFE"), epoxy, epoxy-glass, FR-4, BT resin, thermoplastic or thermoset plastic materials. It may comprise one or more layers of the same dielectric composite material or organic dielectric material. The first face 14 and the second face 16 are substantially parallel to each other and spaced apart by a predetermined distance in a direction orthogonal to the faces 14, 16 that define the thickness of the substrate 12. It is preferable. It is preferable that the thickness of the substrate 12 is within an approximately acceptable range in the present invention. In one example, the distance between the first face 14 and the second face 16 is approximately 25 μm to 500 μm. For this configuration, the first face 14 may be located opposite the second face 16 or spaced apart from the second face 16. This description and the description of the relative positions of the elements as used herein, which mean the vertical position or the horizontal position of these elements, are used for illustrative purposes only to correspond with the position of the elements in the figures, and the scope thereof is limited. It is not intended to be.

As a preferred example, the substrate 12 may be divided into a first region 18 and a second region 20. The first region 18 is located in the second region 20 and includes a central portion of the substrate 12 and extends outwardly from the central portion. The second region 20 substantially surrounds the first region 18 and extends outward from the first region to the outer edge of the substrate 12. In this example, the physical properties of the substrate itself are not divided into two regions, but are separated for description herein in connection with the elements or processes applied to or included therein.

The microelectronic element 22 is mounted on the first face 14 of the substrate 12 in the first region 18. Microelectronic element 22 may be a semiconductor chip or similar device. In the example of FIG. 1, the microelectronic element 22 is mounted on the first face 14 in a manner known in the art or in a "face-up" manner. In this example, a wire lead 24 is used to electrically connect the microelectronic element 22 to a portion of the plurality of conductive elements 28 exposed on the first face 14. Can be used Wire lead 24 may be bonded to a trace (not shown) or other conductive element in substrate 12 that is connected to conductive element 28.

Conductive element 28 includes a “contact” or pad 30 exposed to first side 14 of the substrate. In this specification, the expression that the electrically conductive element is "exposed" on the surface of another element having the dielectric structure means that the electrically conductive structure is perpendicular to the surface of the dielectric structure from the outermost side of the dielectric structure toward the surface of the dielectric structure. It means being able to come into contact with moving theoretical points. Thus, conductive elements such as terminals exposed on the surface of the dielectric structure may protrude from, have the same height as the surface, or may be recessed below the surface and may be exposed through holes or holes in the dielectric. . The conductive element 28 may be a flat, thin element with the pad 30 exposed to the first face 14 of the substrate 12. In one example, the conductive elements 28 may be substantially curved and may be connected to each other by traces (not shown) or to the microelectronic elements 22. Conductive element 28 may be formed in at least second region 20 of substrate 12. In addition, as an example, the conductive element 28 may be formed in the first region 18. This arrangement allows contacts on the microelectronic element 122 to be connected to the conductive element 128 in the first region 118 by solder bumps 126 or the like located directly below the microelectronic element 122. It is particularly useful when mounting the microelectronic element 122 (see FIG. 3) to the substrate 112 in a manner known as the " flip-chip " configuration. In another configuration, shown in FIG. 22, the microelectronic element 622 is mounted on the substrate 612 in a face-down manner and electrically connected to the conductive element on the chip by wire leads 624. The wire lead 624 extends over an outwardly-facing surface, such as the surface 616 of the substrate 612. In the example shown, wire lead 624 passes through opening 625 in substrate 612 and may be encapsulated by overmold 699.

In one example, conductive element 28 is formed of a solid metal material, such as copper, gold, nickel, or other materials that can be used for such use, including one or more of copper, gold, nickel, or a combination thereof. There are a variety of alloys, including.

At least some of the conductive elements 28 may be interconnected to a second conductive element, such as a conductive pad exposed on the second side 16 of the substrate 12, as an element corresponding to the conductive element 28. Such interconnection may be constructed using vias 41 formed in the substrate 12, which may be covered with or filled with a conductive metal, which may be made of the same material as the conductive elements 28, 40. Conductive element 40 may also be interconnected by traces on substrate 12.

The microelectronic assembly 10 further includes a plurality of wire bonds 32 bonded to at least some of the conductive elements 28, for example on the pads 30 of the conductive elements 28. The wire bond 32 is bonded to the base 34 of the conductive element 28 and may extend to a free end 36 spaced apart from the base 34 and the substrate 12. . The free end 36 of the wire bond 32 is electrically connected to or otherwise connected to the microelectronic element 22 or any other conductive element connected to the microelectronic element 22 within the microelectronic assembly 10. It is characterized as a free end in that it is not. In other words, the free end 36 may be used for electronic connection, either directly or indirectly, to a conductive element external to the microelectronic assembly 10, by solder balls or other elements described herein. The free end 36 is, for example, maintained in a predetermined position by an encapsulant layer 42 or otherwise bonded or electrically connected to another conductive element, such that any element is a microelectronic element. Unless electrically connected to (22), this does not mean that these free ends are not "free" as described herein. In contrast, the base 34 is not free since it is electrically connected directly or indirectly to the microelectronic element 22, as described herein. As shown in FIG. 1, the base 34 can be substantially curved, from the edge surface 37 of the wire bond 32 between the base 34 and the free end 36. It may extend outward. The size and shape of the base 34 depends on the type of material used to form the wire bond 32, the connecting force between the wire bond 32 and the conductive element 28, and to form the wire bond 32. It may vary depending on the specific process used. Examples of methods for making wire bonds 32 disclose US patents 7,391,121 and O. 2005/0095835 (wedge-bonding, which may be viewed as a kind of wire bonding) by Otremba. Yes, the contents of this document are incorporated herein by reference. Alternative implementation in which the wire bond 32 extending in a direction away from the second face 16 is additionally or otherwise bonded to the conductive element 40 exposed on the second face 16 of the substrate 12. Yes it is possible.

Wire bond 32 may be made of a conductive material such as copper, gold, nickel, solder, aluminum, or the like. In addition, the wire bond 32 may be made from a combination of materials, such as a core of conductive material, such as copper or aluminum, for example coated with a coating on top of the core. This coating can be another conductive material, such as aluminum, nickel, or the like. Alternatively, the coating may be made of an insulating material, such as an insulating jacket. In one example, the wire used to form the wire bond 32 may have a dimension transverse to the length of the wire, ie, a thickness of approximately 15 μm to 150 μm. In other examples, including embodiments in which wedge bonding is used, wire bond 32 may have a thickness of approximately 500 μm or less. In general, wire bonds are formed on conductive elements such as conductive elements 28, pads, traces, and the like, using dedicated equipment known in the art. By heating the leading end of the wire segment and pressing against a receiving surface to which the wire segment is to be bonded, a ball or ball shaped base 34 is formed which is bonded to the surface of the conductive element 28. do. The desired length of the wire segment for forming the wire bond may be drawn out from the bonding tool and then cut at the desired length. Wedge bonding, which can be used to form a wire bond of aluminum, is a process in which the heated portion of the wire extends across the receiving surface to form a wedge approximately parallel to the surface. . The wire bond of the wedge adhesion system may be curved upward as needed, or may be extended to a desired length or position before cutting. In one example, the wire used to form the wire bond may be cylindrical in cross section. Alternatively, the wire supplied from the bonding tool to form a wire bond or a wire bond of the wedge bonding method may have a polygonal shape such as a square or a trapezoid in cross section.

The free end 36 of the wire bond 32 includes an end surface 38. The end face 38 may form at least a portion of the array-shaped contacts formed by each end face 38 of the plurality of wire bonds 32. 2 shows an example of a pattern for an array of contacts formed by end faces 38. Such an array may be formed in an area array configuration, and modifications thereof may be implemented using the structures described herein. Such an array can be used to electrically and mechanically connect the microelectronic assembly 10 to other microelectronic structures, such as a printed circuit board (“PCB”) or other packaged microelectronic elements such as shown in FIG. 6. . In this stacked structure, wire bond 32 and conductive elements 28 and 40 can carry multiple electronic signals, and different signal potentials so that multiple signals can be processed by multiple microelectronic elements in a single stacked structure. Have each. Solder mass 52 may be used to interconnect the microelectronic assembly of such a laminate structure to conductive element 40 by, for example, electrical and mechanical attachment end faces 38.

The microelectronic assembly 10 further includes an encapsulation layer 42 made of a dielectric material. In the embodiment of FIG. 1, encapsulation layer 42 is a top or conductive element 28 of a portion of first surface 14 of substrate 12 that is not covered or occupied by microelectronic element 22. Is formed on top of the Likewise, encapsulation layer 42 is formed on top of a portion of conductive element 28, which is not covered by wire bond 32, including pad 30 of conductive element 28. Encapsulation layer 42 may substantially cover at least a portion of microelectronic element 22, wire bond 32, including base 34, and edge face 37. A portion of the wire bond 32 may be uncovered by the encapsulation layer 42, which is also referred to as an unencapsulated portion, whereby the wire bond is positioned outside of the encapsulation layer 42. It can be used to make electrical connections with the element. In one example, the end face 38 of the wire bond 32 is not covered by the encapsulation layer 42 at the major surface 44 of the encapsulation layer 42. In another example, a portion of the edge face 37 is not covered by the encapsulation layer 42 in addition to or as an alternative to leaving the end face 38 uncovered by the encapsulation layer 42. You may also In other words, the encapsulation layer 42 is microelectronic from the first face 14 to the top thereof, except for a portion of the wire bond 32, such as at least one of the end face 38 and the edge face 37. It is possible to cover all of the assemblies 10. In the example shown in the figures, a surface, such as the major surface 44 of the encapsulation layer 42, may be spaced apart from the first face 14 of the substrate 12 by a distance sufficient to cover the microelectronic element 22. . Thus, the embodiment of the microelectronic assembly 10, in which the end face 38 of the wire bond 32 is flush with the major surface 44, has a higher wire bond 32 than the microelectronic element 22. ), And bottom solder bumps for flip chip connections. Of course, other configurations for the encapsulation layer 42 are also possible. For example, the encapsulation layer can have multiple faces with varying heights. In this configuration, the major surface 44 on which the end face 38 is located may be higher or lower than the upwardly facing surface on which the microelectronic element 22 is located.

Encapsulation layer 42 protects elements in microelectronic assembly 10, in particular wire bond 32. This allows for a rigid structure that can be less damaged while inspecting the assembly or transporting the assembly to other microelectronic structures. Encapsulation layer 42 may be formed of a dielectric material having insulating properties such as disclosed in US Patent Application Publication No. 2010/0232129, the contents of which are incorporated herein by reference.

3 shows an embodiment of a microelectronic assembly 110 that includes a wire bond 132, where the end 136 of the wire bond 132 is not located in a straight line on the base 134. That is, in order to be substantially planar, when looking at the first surface 114 of the substrate 112 extending in two lateral directions, at least one of the end 136 or the wire bond 132 is formed of the base 134. It is moved in at least one of these lateral directions from the corresponding lateral position. As shown in FIG. 3, the wire bond 132 is substantially straight along the longitudinal axis of the wire bond, and as in the example of FIG. 1, the longitudinal axis is formed of the substrate 112. The angle 146 is angled with respect to the one surface 114. In the cross section of FIG. 3, only the angle 146 through the first plane perpendicular to the first plane 114 is shown, but the wire bond 132 is in another plane perpendicular to both the first plane and the first plane 114. You may make an angle with respect to the 1st surface 114. FIG. This angle may be substantially the same as or different from the angle 146. That is, the end portion 136 may be displaced with respect to the base 134 in two lateral directions, and the distances in these directions may be the same or different.

In one example, the wire bond 132 may be displaced in various directions and by different distances throughout the microelectronic assembly 110. With this arrangement, the microelectronic assembly 110 can have an array that is configured differently at the level of the surface 144 compared to at the level of the substrate 12. For example, the array may cover a smaller overall area or have a smaller pitch on the surface 144 than at the level of the first face 114 as compared to the first face 114 of the substrate 112. In addition, some wire bonds 132 may have ends 138 located on top of microelectronic elements 122 to accommodate stacked configurations of packaged microelectronic elements of different sizes. As another example, as shown in FIG. 19, the wire bond 132 has an end 136A of one wire bond 132A positioned substantially above the base 134B of the other wire bond 134B, End 132B of wire bond 134B may be configured to be positioned anywhere else. Such a configuration can be said that the relative position of the contact end face 136 in the contact array has changed relative to the position of the corresponding contact array on the second face 116. Within such arrays, the relative position of the contact end faces can be varied or varied as needed, depending on the use of the microelectronic assembly or other requirements.

4 illustrates an embodiment of a microelectronic subassembly 210 that includes a wire bond 232, wherein the end 236 of the wire bond 232 is lateral to the base 234. Displaced into position. In the example of FIG. 4, the wire bond 132 achieves this lateral displacement by including a curved portion 248 therein. The curved portion 248 may be formed as an additional step during the wire bond forming process, and the formation of the curved portion may be performed while drawing out a portion of the wire by a desired length. This step can be performed using commercially available wire bonding equipment, including using one machine.

Curved portion 248 may be configured in various forms, as needed, to achieve the desired location of end 236 of wire bond 232. For example, curved portion 248 may be formed of an S-shaped curve, such as that shown in FIG. 4, or of a flatter shape (see that shown in FIG. 5), among other forms. Further, the curved portion 248 may be located closer to the base 234 than to the end 236, and conversely may be located closer to the end than the base. The curved portion 248 may be in the form of a spiral or a loop, or may be a mixed type including curves in a plurality of directions or having different forms or features.

5 illustrates an embodiment of a microelectronic package 310 having a combination of wire bonds 332 of various shapes that allows for relative lateral displacement between the base 334 and the end 336. The wire bond 332A in the wire bond is substantially straight with the end 336A located on top of the base 334A, while the other wire bond 332B is slightly relative between the end 336B and the base 334B. Some curved portion 348B with lateral displacements. Some wire bonds 332C have a sweeping shape in which end 336C is laterally displaced from base 334C by a longer distance than end 334B. 5 also shows a pair having bases 334Ci and 334Cii located in the same column of a substrate-level array and ends 336Ci and 336Cii located in different columns of the corresponding surface-level array. Wire bonds 332Ci and 332Cii are shown.

Another variation of the wire bond 332D is shown that the wire bond is not covered by the encapsulation layer 342 on the side surfac 47. In the example in which the free end 336D is shown not covered, a portion of the edge face 337D may not be further covered by the encapsulation layer 342 or may be uncovered instead of the free end. . This configuration can be used for mechanical or electrical connection to other elements disposed laterally of the microelectronic assembly 310 or for grounding the microelectronic assembly 10 by electrical connection to appropriate elements. . 5 may also be removed, molded, or otherwise formed by etching the encapsulation layer 342 to form a recessed surface 345 located closer to the substrate 312 than the surface 344. Indicates a part. One or more wire bonds, such as wire bond 332A, do not have to be covered in the area along the concave surface 345. In the example shown in FIG. 5, a portion of the edge face 337A and the end face 338A are not covered by the encapsulation layer 342. According to this configuration, for example, a solder ball or the like allows the solder to be bonded to the edge face in addition to wicking the solder along the edge face 337A and to the end face 338. Can be accessed. Other configurations are also possible such that a portion of the wire bond is not covered by the encapsulation layer 342 along the concave side 345, with the end face relative to the concave side 345 or any other surface of the encapsulation layer 342. A configuration having substantially the same height as other configurations shown herein is also possible. Similarly, configurations in which a portion of the wire bond 332D is not covered by the encapsulation layer 342 along the side surface 347 are similar to those described elsewhere herein in connection with a modification of the major face of the encapsulation layer. Can be similar.

5 shows two microelectronic elements 322, 350, which show a microelectronic assembly 310 in which the microelectronic element 350 is stacked up on the microelectronic element 322. In this configuration, a lead 324 is used to electrically connect the microelectronic element 322 to a conductive element on the substrate 312. Various leads are used to electronically connect the microelectronic element 350 to various other elements of the microelectronic assembly 310. For example, the lead 380 electrically connects the microelectronic element 350 to the conductive element of the substrate 312, and the lead 382 electrically connects the microelectronic element 350 to the microelectronic element 322. do. In addition, wire bonds 384, which may be similar to structures having various wire bonds 332, are contacts that are electrically connected to the microelectronic element 350 on the surface 344 of the encapsulation layer 342. It is used to form a contact surface 386. This can be used to electrically connect an element of another microelectronic assembly directly to the microelectronic element 350 from the top of the encapsulation layer 342. Leads connected to the microelectronic element 322 may be included, including when no other microelectronic element 350 is attached to the microelectronic element 322. In encapsulation layer 342, leads 380 are formed for electrical connection to elements located outside of surface 344 by forming openings (not shown) that extend from surface 344 to a point along lead 380. You may be able to access. An upper portion of the wire bond 332 or any other lead, such as the upper portion of the wire bond 332C, may be provided with an opening similar to the opening at a point far from the end portion 336C. In this example, end 336C may be positioned below surface 344, in which case the opening is provided only for access for electrical connection.

6 shows a stacked package of microelectronic assemblies 410, 488. In this configuration, the solder mass 452 electrically and mechanically connects the end face 438 of the microelectronic assembly 410 to the conductive element 440 of the microelectronic assembly 488. This stacked package may include additional assemblies and may later be attached to contacts on the PCB 490 for use in electronic devices, for example. In such a stacked configuration, the wire bond 432 and the conductive element 430 allow the different signals to be processed by several microelectronic elements, such as the microelectronic element 422 or the microelectronic element 489 in a single stack. A plurality of electronic signals, each having a different signal potential, can be delivered.

In the configuration shown in FIG. 6, the wire bond 432 is possible to include a curved portion 448 in which at least a portion of the end 436 extends to an area on the major surface 424 of the microelectronic element 422. . This region is made by the outer periphery of the microelectronic element 422 and may extend upward from the microelectronic element. An example of such a configuration is shown in the view of the first surface 414 of the substrate 412 shown in FIG. In this configuration, the wire bond 432 is located on the back side of the microelectronic element 422 and is flip chip bonded to the substrate 412 at the front side 425 of the microelectronic element. As another configuration (see FIG. 5), the microelectronic element 422 can be mounted face up to the substrate 312, with the front surface 325 facing away from the substrate 312, and having one or more wire bonds. 336 is located on the front side of the microelectronic element 322. In one example, such wire bond 336 is not electrically connected to microelectronic element 322. The wire bond 336 bonded to the substrate 312 may be disposed on the front or back side of the microelectronic element 350. In the embodiment of the microelectronic assembly 410 shown in FIG. 18, the conductive elements 428 consist of a pattern forming a first array disposed in rows and columns surrounding the microelectronic elements, with individual conductive elements 428. It can have a predetermined pitch in between. Wire bond 432 is bonded to conductive element 428 such that each base 434 of the wire bond follows the pattern of the first array initiated by conductive element 428. Wire bond 432 has a configuration in which each end 436 of the wire bond can be arranged in a different pattern according to the second array configuration. In the example shown, the pitch of the second array can be different than the first array, and in some cases finer than the pitch of the first array. However, in other embodiments, the pitch of the second array is greater than the pitch of the first array, or the conductive elements 428 are not located in a predetermined array, but the end 436 of the wire bond 432 is predetermined. Arrays located in arrays are also possible. In addition, conductive element 428 may consist of a set of arrays located throughout the substrate 412, and wire bond 432 may be configured such that end 436 is a single array or multiple sets of arrays.

6 shows an insulating layer 421 extending along the surface of the microelectronic element 422. The insulating layer 421 may be formed of a dielectric or other electrically insulating material before forming the wire bond. The insulating layer 421 may be configured such that the microelectronic element does not come into contact with any wire bond 423 extending above the microelectronic element. In particular, the insulating layer 421 can prevent electrical shorts between the wire bonds and shorts between the wire bonds and the microelectronic element 422. In this way, the insulating layer 421 can avoid failure or damage due to unintentional electrical contact between the wire bond 432 and the microelectronic element 422.

According to the wire bond configurations shown in FIGS. 6 and 18, for example, when the relative sizes of the microelectronic assembly 488 and the microelectronic element 422 are not allowed, the microelectronic assembly 410 may be replaced with the microelectronic assembly ( 488), and other microelectronic assemblies. In the example of FIG. 6, the microelectronic assembly 488 may be in an array form in which some contact pads 440 are smaller than the area of the front 424 or back 426 of the microelectronic element 422. Has a size. Instead of wire bond 432, in a microelectronic assembly having a substantially vertical conductive element such as a pillar or the like, direct connection between conductive element 4428 and pad 440 will not be allowed. However, as shown in FIG. 6, the wire bond 432 with the properly configured curved portion 448 is in the proper position to make the necessary electronic connection between the microelectronic assembly 410 and the microelectronic assembly 488. It may have an end 436. This configuration is a stacked package in the case where the microelectronic assembly 418 is, for example, a DRAM chip having a predetermined pad array, and the microelectronic element 422 is a logic chip configured to control the DRAM chip. It can be used to construct. This allows a single type of DRAM chip to be used with a number of different logic chips that are larger than the DRAM chip and of various sizes, which allows the wire bond 432 to make the desired connection with the DRAM chip. This is possible because it includes an end 436 disposed in the required position. As another example, the microelectronic package 410 may be mounted on a printed circuit board 490 in a different configuration, in which case the unencapsulated surface 436 of the wire bond 432 is a circuit board 490. Is electrically connected to a pad 492. Also in this example, another microelectronic package, such as variant package 488, may be mounted on package 410 by solder balls 452 bonded to pad 440.

FIG. 7 shows a microelectronic assembly 10 of the type shown in FIG. 1, comprising a redistribution layer extending along the surface 44 of the encapsulation layer 42. As shown in FIG. 7, the trace 58 is electrically connected to an inner contact pad 61, which is electrically connected to the end face 38 of the wire bond 32, and the rearrangement layer 54. ) Extends through the substrate 56 to the contact pads 60 exposed on the surface 62 of the substrate 56. The contact pad 60 may be connected to an additional microelectronic assembly by a solder lump or the like. Along a second side 16 of the substrate 12, a layer similar to the rearrangement layer 54, known as a fan-out layer, may extend. The fan out layer allows the microelectronic assembly 10 to be connected to an array of configurations other than that where the array of conductive elements 40 is acceptable.

8A-8E illustrate various configurations that may be implemented in a structure similar to FIGS. 1-7, with or near the structure of the end 36 of the wire bond 32. 8A shows a structure in which a cavity 64 is formed in a portion of the encapsulation layer 42. In this configuration, the end 36 of the wire bond 32 protrudes over the minor surface 43 of the encapsulation layer in the cavity 64. In the example shown, the end face 38 is located below the major surface 44 of the encapsulation layer 42, and the cavity 64 has the end face 38 at the surface 44. By exposing, the electronic structure has a structure that can be connected to the end face. Embodiments in which the end face 38 is substantially parallel to the surface 44 or spaced to the top of the surface 44 are also possible. In addition, in the cavity 64, a portion of the edge face 37 near the end 36 of the wire bond 32 may not be covered by the encapsulation layer 42 in the cavity 64. This configuration enables connection to the wire bond 32 from the outside of the assembly 10 by solder connection or the like, which connection is an uncoated portion of the edge face 37 near the end 36 of the wire bond. And by end face 38 both. Such a connection is shown in FIG. 8B, and the solid connection to the second substrate 94 is possible using the solder lump 52. In one example, the cavity 64 may have a depth below the surface 44 of between about 10 μm and 50 μm and a width of between about 100 μm and 300 μm. FIG. 8B shows a cavity having a structure similar to that of FIG. 8A, but the cavity of FIG. 8B includes a tapered sidewall 65. FIG. 8 also shows a second microelectronic assembly 94 electrically and mechanically connected to the wire bond 32 by the solder mass 52 in the contact pad 96 exposed on the surface of the substrate 98.

Cavity 64 may be formed by removing a portion of encapsulation layer 42 in a desired region. The formation of such cavities can be done by known processes such as laser etching, wet etching, lapping, and the like. Alternatively, in embodiments in which the encapsulation layer 42 is formed by injection molding, the cavity 64 can be formed by including corresponding elements in the mold. Such a process is disclosed in US Patent Application Publication No. 2010/0232129, which is incorporated by reference herein. The tapered shape of the cavity 64 shown in FIG. 8B can be the result of the particular etching process used when forming the cavity.

8C and 8E show the end structure in which the end portion 70 on the wire bond 32 is substantially curved. The curved end portion 70 is configured to have a cross section that is wider than the cross section of the portion between the base 34 and the end 36 of the wire bond 32. The curved end portion 70 also includes an edge face 71, which is a wire bond 32 at the transition between the edge face 37 and the edge face 71. Extend outward from the edge face 37 of the. By including the curved edge portion 70, the wire bond 32 can be secured within the encapsulation layer 42 by providing an anchoring feature. In this case, the encapsulation layer 42 can be provided in a position to surround the end portion 70 on the three sides by a change in the direction of the edge face 71. This may help to prevent the wire bond 32 from being separated from the conductive element 28 on the substrate 12 and thus resulting in poor electrical connection. In addition, the curved end portion 70 can increase the surface area not covered by the encapsulation layer 42, in which electronic connection can be made within the surface 44. As shown in FIG. 8E, the curved end portion 70 may extend to the top of the surface 44. Alternatively, as shown in FIG. 8C, the curved end portion 70 may be polished or planarized to provide a surface that is substantially the same height as the surface 44, rather than a cross section of the wire bond 32. It can have a large area.

The curved end portion 70 may be formed by locally applying heat in the form of sparks or sparks to the end of the wire used to make the wire bond 32. A known wire bonding machine can be modified to carry out this process, which may be carried out immediately after cutting the wire. In this process, heat melts the ends of the wire bonds. The localized portions of these liquid metals are curved by surface tension and retain their shape as the metal cools.

FIG. 8D shows the configuration of the microelectronic assembly 10 in which the end 36 of the wire bond 32 includes a surface 38 spaced above the major surface 44 of the encapsulation layer 42. This configuration provides a tighter connection, in particular by the solder mass 68 wicking along the portion of the edge face 37 which is not covered by the encapsulation layer 42 on the surface 44. It may have similar advantages as described above with respect to (64). In one embodiment, the end face 38 may be spaced apart by a distance between approximately 10 μm and 50 μm above the surface 42. In addition, in the embodiment of FIG. 8D and in other embodiments where a portion of the edge face 37 is not covered by the encapsulation layer 42 on top of the surface of the encapsulation layer 42, the end is protected. layer) may be included thereon. Such layers can include an oxide protective layer, including layers of gold, oxide coatings, or OSPs.

9 shows an embodiment of a microelectronic assembly 10 in which a stud bump 72 is formed on an end face 38 of a wire bond 32. The stud bumps 72 may be formed after fabricating the microelectronic assembly 10 by providing another modified wire bond to the top of the end face 44 and selectively extending along a portion of the surface 44. The deformed wire bond is cut near the base or otherwise cut out without drawing the wire. The stud bump 72 containing the desired metal can be provided directly to the end face 38 without first providing a bonding layer such as UBM, so that it is not directly wetted by solder. A method of forming a conductive interconnect to a bond pad is provided. This may be useful when the wire bond 32 is formed of a non-wettable metal. Generally, stud bumps which basically comprise one or more of copper, nickel, silver, platinum, and gold may be applied in this manner. 9 shows the formation of a solder mass 68 on top of stud bumps 72 for electronic or mechanical connection to additional microelectronic assemblies.

10A-10D illustrate a configuration for an end 36 of wire bond 32 that includes a bent or curved shape. In each embodiment, the end 36 of the wire bond 32 is bent such that a portion 74 of the end extends substantially parallel to the surface 44 of the encapsulation layer 42 and the edge face 76. At least a portion of the is not, for example, covered by the major surface 44. The portion of the edge face 76 may extend upwards on the outside of the surface 44 or may be polished or planarized to extend substantially the same height as the surface 44. The embodiment of FIG. 10A is a configuration in which the wire bond 32 is sharply bent at a portion 74 that is parallel to the surface 44 of the end 36 and terminates at an end face 38 substantially orthogonal to the surface 44. It includes. FIG. 10B shows the end 36 having a gentler curve near the portion 74 parallel to the surface 44 of the end 36 than shown in FIG. 10A. A portion of the wire bond according to the configuration shown in FIG. 3, 4 or 5 has a portion substantially parallel to the surface 44 and is covered by the encapsulation layer 42 at a position in the surface 44 among the edge faces. Many other configurations are possible, including configurations that include ends having non-parts. The embodiment shown in FIG. 10B also includes a hooked portion 75 on the end of the wire bond, with the end face 38 positioned below the surface 44 in the encapsulation layer 42. Done. This can provide a rigid structure that allows the end 36 to be less in place within the encapsulation layer 42. 10C and 10D are similar to those shown in FIGS. 10A and 10B, respectively, but not covered by the encapsulation layer 42 at a position along the surface 44 by a cavity 64 formed in the encapsulation layer 42. Represents a structure. These cavities can be structurally similar to those described with respect to FIGS. 8A and 8B. By including an end 36 having a portion 74 extending parallel to the surface 44, by means of the elongated, uncoated edge face 75, the area for connection with the surface can be increased. . The length of this portion 74 may be larger than the width of the cross section of the wire used to form the wire bond 32.

11-15 illustrate microelectronic assemblies at various stages in the method of manufacturing the microelectronic assembly 10. 11 shows the microelectronic assembly 10 in a step in which the microelectronic element 22 is electrically and mechanically connected to the substrate on the first face 14 of the substrate 12 and in the first region 18. '). The microelectronic element 22 is shown in FIG. 11 mounted on the substrate 12 in a flip chip configuration by the solder mass 26. Instead of such a flip chip configuration, a face up bonding as shown in Fig. 1 may be used. In the embodiment of the process shown in FIG. 11, an underfill dielectric layer 66 may be provided between the microelectronic element 22 and the substrate 12.

Figure 12 shows a microelectronic assembly 10 "with wire bonds applied to a pad 30 of conductive element 28 exposed on first side 14 of substrate 12. As previously described, Wire bond 32 may be provided by heating and softening the ends of the wire segments, which are pressed against the conductive elements 28 to deposit bonds to the conductive elements 28. And the base 34. The wire is then drawn out from the conductive element 28 and, if necessary, to form the end face 38 and the end 36 of the wire bond 32. The wire bond 32 may be formed of, for example, aluminum wire by wedge bonding, before cutting or otherwise cutting it into a specific shape. Wire part adjacent to the end And dragging along the conductive element 28 while applying pressure to that portion, which is disclosed in US Pat. No. 7,391,121, the disclosure of which is incorporated herein by reference. Shall be.

In FIG. 13, the microelectronic assembly 10 ″ ′ is encapsulated applied onto the first side 14 of the substrate and extending above the first side and along the edge face 37 of the wire bond 32. Added layer 42. Encapsulation layer 42 is adapted to cover underfill layer 66. Encapsulation layer 42 is resin on microelectronic assembly 10 'shown in FIG. This configuration can be formed by depositing the microelectronic assembly 10 in a mold of a suitable configuration having a cavity in the encapsulation layer 42 of a preferred form that is capable of receiving the microelectronic assembly 10 '. A method for forming such a mold and an encapsulation layer with a mold is shown and disclosed in US Patent Application Publication No. 2010/0232129, the disclosure of which is incorporated herein by reference. In contrast, the cap The encapsulation layer 42 can be prefabricated to a desired shape, at least in part, by a compliant material, in this configuration, due to the compliant nature of the dielectric material, the encapsulation layer 42 can be wire-bonded 32. And to a position on the microelectronic element 22. In this process, the wire bond 32 penetrates into the compliant material and forms holes in the compliant material, respectively, encapsulating along the hole. The layer 42 is in contact with the edge face 37. The microelectronic element 22 can also deform the compliant material so that the microelectronic element can be accommodated within the compliant material. The compliant material may be compressed to expose the end face 38 on the outer face 440. Alternatively, excess dielectric compliant material may be removed from the encapsulation layer. It may be removed to form a surface 44 on which the end face 38 of the wire bond 32 is not covered, or a cavity 64 not covering the end face 38 at a position in the surface 63 may be formed. .

In the embodiment shown in FIG. 13, the encapsulation layer is initially formed such that the surface 44 of the encapsulation layer is spaced apart from the top of the end face 38 of the wire bond 32. By exposing the upper portion of the end face 38 of the encapsulation layer 42 to expose the end face 38, a new one having substantially the same height as the end face 38, as shown in FIG. 14. Surface 44 'is exposed. Alternatively, it is possible to form a cavity 64 as shown in FIGS. 8A and 8B, in which the end face 38 is not covered by the encapsulation layer 42. As another example, encapsulation layer 42 may have surface 44 at substantially the same height as end face 38, or surface 44 may be below end face 38, as shown in FIG. 8D. It can be formed to be located. If a portion of the encapsulation layer needs to be removed, it can be removed by polishing, dry etching, laser etching, wet etching, lapping, or the like. If a portion of the end 36 of the wire bond 32 is to be removed, it may be done simultaneously with the step of achieving a substantially flat end face 38 of substantially the same height as the surface 44, and in addition thereto. You may also If necessary, the cavity 64 may be formed after this step, or the stud bumps shown in FIG. 10 may be applied. Thereafter, the microelectronic assembly 10 produced by the above process may be attached to the PCB or may be included in another assembly, for example, in a stacked package as shown in FIG.

In another embodiment, shown in FIG. 15, the wire bonds 32 are initially formed in pairs as part 32 ′ of the wire loop 86. In the present embodiment, the wire loop 86 is in the form of a wire bond as described above. The wire segment is pulled upwards and then bent in a direction having one or more components in the direction of the first face 14 of the substrate 12 to pull it to a position that substantially covers the top of the neighboring conductive element 28. The wire is then pulled substantially downward to a location near the neighboring conductive element 28 and then cut or otherwise cut. The wire is then heated and connected to adjacent conductive elements 28 by vapor deposition or the like to form a wire loop 86. Next, the encapsulation layer 42 is formed to substantially cover the wire loop 86. Subsequently, a portion of the encapsulation layer 42 is removed by polishing or etching, and the wire loop is cut into two portions 32 ′ at a position along the surface 44 formed on the encapsulation layer 42. A portion of the wire loop 86 is removed to form a wire bond 32 having an end face 38 that is not covered by the encapsulation layer 42. Subsequently, a subsequent finishing process may be performed on the microelectronic assembly 10 as described above.

16A-16C show a process in another embodiment of manufacturing the cavity 64 described above that surrounds the end 36 of the wire bond 32. 16A shows a general type of wire bond 32 described in connection with FIGS. 1-6. The wire bond 32 is coated with a sacrificial material mass 78 at the end 36. The sacrificial material mass 78 may be substantially spherical, which may be caused by the surface tension of the sacrificial material during formation of the sacrificial material mass, and may be known to those skilled in the art. You may make it. The sacrificial material mass 78 can be formed by dipping the end 36 of the wire bond 32 in solder paste to coat the end. Prior to dipping the ends, the viscosity of the solder paste can be adjusted to control the amount of solder mass to be wicked and the surface tension to adhere to the ends 36. Thus, accordingly, the size of the sacrificial material mass 78 applied to the end portion 36 can be adjusted. As an alternative to this, the sacrificial material mass 78 may be formed by depositing a soluble material on the end 36 of the wire bond 32. As examples of other sacrificial material masses 78, individual solder balls or other mass masses may be used, or may be formed by other means using other materials such as copper or gold flashing, later removed. You may also

In FIG. 16B, the dielectric layer 42 is shown added to the microelectronic assembly 10 upwards along the edge face 37 of the wire bond 32. This dielectric layer extends along a portion of the surface of the sacrificial material mass 78, thereby being spaced apart from the end 36 of the wire bond 32. The sacrificial material mass 78 is then removed, for example, by washing or cleaning with a solvent, melting, chemically etching, or using other techniques. Prior to removing the sacrificial material mass, the cavity 68 is left in the dielectric layer 42 substantially in the shape of the intaglio of the sacrificial material mass 78, and the edge face (in the vicinity of the end 36 of the wire bond 32) is removed. Part of 37).

As an alternative to this, substantially all of the wire bond 32 can be coated by extending the sacrificial material mass 78 along the edge face 37 of the wire bond 32. This configuration is shown in Fig. 17A. Such a coating may be applied to the top of the wire bond 32 after being formed on the microelectronic assembly 10, as described above, or to the wire used to manufacture the wire bond 32. This will essentially be a coated wire or a two part wire, for example a wire comprising an inner core of copper and a solder coating. FIG. 17B shows that the dielectric layer 42 is applied over the wire bond 32 and the sacrificial material mass 78 so that the dielectric layer 42 extends along the edge face 37 of the sacrificial material mass 78. Layer 42 is substantially spaced from the wire bond along the long side of the wire bond.

FIG. 17C shows a structure in which a portion of the sacrificial material mass 78 has been removed to form a cavity 64 around the end 36 and exposed a portion of the end face 37. In this embodiment, most or at least a portion of the sacrificial material mass 78 may be left at a location between the dielectric layer 42 and the wire bond 32. FIG. 17C shows a solder mass 52 that electrically and mechanically connects wire bonds 32 to contact pads 40A of another microelectronic structure 10A.

20 and 21 show an embodiment of a microelectronic assembly 510 in which wire bonds 532 are formed on a lead-frame structure. Examples of lead frame structures are shown and disclosed in US Pat. Nos. 7,176,506 and 6,765,287, the disclosures of which are incorporated herein by reference. In general, a lead frame is a structure made of a conductive metal sheet such as copper, and the conductive metal sheet is divided into segments and frames including a plurality of leads and additional paddles. Patterned. The frame is used to secure the leads and paddles during fabrication of the microelectronic assembly. In one embodiment, a microelectronic element, such as a die or chip, may be face-up bonded to the paddle and may be electrically connected to the leads using wire bonds. As an alternative, the microelectronic element may be mounted directly on a lead which can extend below the microelectronic element. In such embodiments, the contacts on the microelectronic elements may be electrically connected to the respective leads by solder balls or the like. The leads may then be used to form electrical connections to various other conductive structures for exchanging electronic signal potentials with the microelectronic elements. Upon completion of the microelectronic assembly of such a structure, the microelectronic assembly may form an encapsulation layer on top, or the temporary elements of the frame may be removed from the leads and paddles of the lead frame to form individual leads. To illustrate this, each lead 513 and paddle 515 can be a separate component of a structure forming a substrate 512 that includes a conductive element 528 formed integrally with the substrate. In this embodiment, the paddle 515 may be in the first region 518 of the substrate 512, and the lead 513 may be in the second region 520. Wire bond 524 shown in the side view of FIG. 21 connects microelectronic element 22 located on paddle 515 to conductive element 528 of lead 515. Wire bond 532 may bond to additional conductive element 528 on lead 515 at base 534. Encapsulation layer 542 forms on microelectronic assembly 510 leaving end 538 of wire bond 532 uncovered at a location in surface 544. Wire bond 532 may include additional or replaceable portions that are not covered by encapsulation layer 542 in the structure corresponding to the structure described with respect to other embodiments of the present invention.

24-26 show another embodiment of a microelectronic package 810 having a closed-loop wire bond 832. The wire bond 832 of this embodiment includes two bases 834a and 834b that can be joined to neighboring conductive elements 828a and 828b, as shown in FIG. 24. Alternatively, a configuration is also possible in which the bases 834a and 834b are all joined to a common conductive element 828, as shown in FIGS. 25 and 26. In this embodiment, wire bond 832 forms an edge face 837 in a loop form extending between two bases 834a and 834b, whereby edge face 837 extends from the base, substrate 812. It extends upwards at each portion 837a, 837b to an apex 839 at the surface 844 of the encapsulation layer 842. Encapsulation layer 842 extends along at least a portion of edge face portions 837a and 837b to separate each edge face portion from each other and from other wire bonds 832 in package 810. At apex 839, at least a portion of edge face 837 is covered by encapsulation layer 842, whereby wire bond 832 may be another microelectronic component, a separate element such as a capacitor or an inductor, or the like. It can be used for electrical interconnection with other parts that may be present. As shown in FIGS. 24-26, wire bond 832 is formed such that vertex 839 is displaced from conductive element 828 in at least one lateral direction across surface of substrate 812. In one example, vertex 839 may be positioned over a major surface of microelectronic element 820 or may be positioned over first region of substrate 812 in which microelectronic element 820 is aligned. Other configurations for wire bond 832 are possible. For example, the structure where the vertex 839 is arrange | positioned in the arbitrary position of the end surface of a wire bond is possible, as demonstrated in another embodiment. In addition, the vertex 839 may not be coat | covered in a hole as shown in FIG. 8A. Further, the vertex 839 may be elongated, or as shown with respect to the edge face of FIGS. 10A-10D, a portion extending along the length on the surface 844 may not be covered. The connecting element is supported by the surface 844 by allowing the connecting element in the form of an uncoated edge face 837 surrounding the vertex 839 to be supported by a wire bond extending between two bases 834a and 834b. It is possible to place more precisely in the defined direction.

27 and 28 show an example of using a bond ribbon 934 instead of the wire bond 834 as a modification of the embodiment shown in FIGS. 24 to 26. The bond ribbon can be a substantially flat portion of the conductive material of any of the materials described above forming the wire bond. Unlike the wire bond, the bond ribbon structure may be wider than the thickness so that the cross section is substantially circular. As shown in FIG. 27, the bond ribbon 934 each includes a first base 934a that is attached to and extends along a portion of the conductive element 928. The second base 934b of the bond ribbon 932 may be bonded to a portion of the first base 934a. The edge face 937 extends from the two corresponding portions 937a and 937b to the vertex 939 between the bases 934a and 934b. The portion of the edge face in the region of vertex 939 is covered by encapsulation layer 942 along a portion of major surface 944. As described in connection with the wire bonds used in other embodiments described herein, further variations are possible.

The structures described above can be used in the construction of various electronic systems. For example, system 711 according to an embodiment of the present invention includes microelectronic assembly 710 as described above, along with other electronic components 713 and 715. In the example shown, component 713 is a semiconductor chip and component 715 is a display screen, although any other component may be used. Of course, although only two parts are shown in FIG. 23 for the sake of simplicity, the present system may be configured to include any number of parts. The microelectronic assembly 710 described above may be, for example, a microelectronic assembly described with reference to FIG. 1, or a structure including a plurality of microelectronic assemblies described with reference to FIG. 6. The microelectronic assembly 710 may further include any of the embodiments described in FIGS. 2 through 22. As another variant, many variations can be provided, and any number of such structures can be used.

The microelectronic assembly 710 and the components 713 and 715 are installed in a common housing 719 schematically shown by a dotted line, and can be electrically connected to each other to constitute a desired circuit as necessary. The illustrated system includes a circuit board 717, such as a flexible printed circuit board, which includes a plurality of conductors 721 that connect the components together, and only one of them is shown in FIG.

The housing 719 is shown to be a portable housing that can be used in a cell telephone or PDA, with the screen 715 exposed on the surface of the housing. The microelectronic assembly 710 includes light-sensitive elements, such as imaging chips, and may be provided with other optical elements, such as a lens 723, for directing light to the structure. The system shown briefly in FIG. 23 is merely an example, and a system generally considered as a fixed structure such as a desktop computer, a router, or the like can also be made using the structure described above.

While the present invention has been described with reference to specific embodiments, it should be understood that these embodiments merely illustrate the principles and applications of the present invention. Accordingly, it should be understood that various modifications may be made to the illustrated embodiments without departing from the spirit and scope of the invention as claimed by the claims.

Claims (1)

In a microelectronic package,
A substrate having a first region, a second region, a first surface, and a second surface spaced apart from the first surface;
One or more microelectronic elements positioned above the first face within the first region;
An electrically conductive element exposed to at least one of the first and second sides of the substrate in the second region, at least a portion of the conductive element being electrically connected to the at least one microelectronic element, the conductive element Is a conductive element disposed in a first array of a first predetermined configuration;
A wire bond having a base bonded to each of the conductive elements, and an end surface spaced apart from the substrate and the base, the wire bond being between the base and the end face. An elongated edge surface is formed, respectively, wherein a first wire bond in the wire bond delivers a first signal electric potential, while at the same time a second wire bond in the wire bond is applied to the first wire bond. A wire bond, transferring a second signal potential different from the signal potential; And
A dielectric encapsulation layer extending from at least one of the first and second faces, the encapsulation layer filling the space between the wire bonds so that the wire bonds are separated from each other, the encapsulation A layer located over at least a second region of the substrate, the encapsulation layer comprising one or more surfaces forming a major surface parallel to the first face of the substrate
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The unencapsulated portions of the wire bond consist of at least a portion of the end face of the wire bond not covered by the encapsulation layer,
The unencapsulated portion of the wire bond is not covered by the encapsulation layer at the major surface,
The unencapsulated portion of the wire bond is arranged in a second array of a second predetermined configuration different from the first configuration,
Microelectronic package.

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