KR20120120038A

KR20120120038A - Mos semiconductor device and methods for its fabrication

Info

Publication number: KR20120120038A
Application number: KR1020120040582A
Authority: KR
Inventors: 수레쉬 벤카테산
Original assignee: 글로벌파운드리즈 인크.
Priority date: 2011-04-20
Filing date: 2012-04-18
Publication date: 2012-11-01

Abstract

A Morse device having a channel region selectively formed therein and a method of manufacturing the same are provided. This method includes forming a mask defining a gate region on a surface of a semiconductor substrate. Source and drain regions aligned with the gate regions are formed in the semiconductor substrate, and sub-surface under-doped impurity regions are formed in the semiconductor substrate using the mask as a doping mask. Thereafter, a gate electrode aligned with the gate region is formed on the semiconductor substrate using the mask as a gate alignment mask.

Description

MOS SEMICONDUCTOR DEVICE AND METHODS FOR ITS FABRICATION

In general, the present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a MOS semiconductor device having a selectively formed channel region and a method for manufacturing such a semiconductor device.

Today, most integrated circuits (ICs) are implemented using a plurality of interconnected field effect transistors (FETs), referred to simply as metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. One MOS transistor includes a gate electrode as a control electrode and includes a source and a drain region spaced apart from each other and formed in the semiconductor substrate, so that current may flow between the source region and the drain region. The control voltage applied to the gate electrode controls the flow of current through the channel between the source and drain regions.

The manufacture of integrated circuits faces a number of challenges. As functions implemented in integrated circuits (ICs) become more and more complex, more MOS transistors must be integrated on integrated circuit chips. Integrated circuits not only become more complex, but also tend to require increasingly faster integrated circuits. That is, there is a tendency to reduce the switching speed of integrated circuits.

As the number of transistors on an IC increases, there is a need to reduce the size of each individual transistor and hence the size of the components constituting the transistor. Reducing the size of the MOS transistor requires reducing the spacing between the source and drain regions, while reducing the source-drain spacing is not only a punch through breakdown, but also a number of short channel effects. Can cause problems. Typical solutions to these problems include halo implants to counter short channel effects and punch through implants to increase doping of the channel and substrate wells to prevent punch throughs. However, these solutions cause other problems.

Junction capacitance, i.e., the capacitance of the source-substrate junction and especially the drain-substrate junction, has a great influence on the speed of the IC because these capacitances must be charged or discharged during the switching operation. Junction capacitance is increased by increasing impurity doping of the material on either side of the junction. Typical halo implants, threshold voltage implants, and punch-through implants increase impurity doping in substrate wells and channels, thus increasing junction capacitance and adversely affecting switching speed.

One of the approaches considered was to lower the impurity doping concentration in the substrate well to increase the dose of the punch through implant and reduce the junction capacitance by placing the implant deeper in the channel region. However, in a typical MOS process, the threshold voltage implant and punch-through implant are applied over the entire active region of the transistor, including the channel region and the source / drain regions. Therefore, placing the punch through implant deeper in the channel region actually positions the implant below the source and drain regions, which increases but does not reduce the junction capacitance. Therefore, this solution is not a valid solution.

In addition to the junction capacitance problem, increased doping concentration below the source / drain extension region results in increased band-band leakage current (or referred to as gate induced drain leakage or GIDL). This leakage current establishes a floor below which the leakage current can no longer be reduced, so this leakage current reduces the static power consumption of a given technique and the static power consumption of devices made based on that technique. To establish. To reduce the leakage current, the short channel characteristics of the device must be improved without increasing the punch through or halo doping under the source / drain extension region.

Accordingly, there is a need to provide a method of manufacturing an integrated circuit in which the source-drain spacing of the MOS transistor is reduced without adversely affecting the switching speed of the integrated circuit. In addition, it is desirable to provide a MOS transistor that can ensure the switching speed required for the integrated circuit implementation. In addition, it is desirable to provide a MOS transistor having a good short channel controllability with minimal halo or source drain doping, and having a low junction capacitance and a low interband leakage current, and a method of manufacturing the same. Furthermore, other desirable advantages and other features of the present invention will become apparent from the following detailed description and claims in view of the accompanying drawings and the background art as described above.

According to an embodiment of the present invention, there is provided a method for manufacturing a MOS device, the method comprising: depositing a dummy gate material layer on a surface of a semiconductor substrate and patterning the dummy gate material layer to form a dummy gate It includes. Spaced apart source and drain regions are implanted in alignment with the dummy gate, and a gap fill material is deposited over the semiconductor substrate and the dummy gate. A portion of the gapfill material is removed to expose the top surface of the dummy gate and the dummy gate is removed to form a recess extending through the gapfill material. Conductivity determining ions are implanted through the recess and into the semiconductor substrate to form a channel region doped with impurities between the spaced source and drain regions. A portion of the surface of the semiconductor substrate over the doped channel region is exposed and a gate insulator and a gate electrode are formed over the portion of the surface.

According to another embodiment of the present invention there is provided a method for manufacturing a MOS device, the method comprising forming a mask defining a gate region on a surface of a semiconductor substrate. Source and drain regions are aligned in the gate region and formed in the semiconductor substrate, and an enhanced doping sub-surface impurity region is formed in the semiconductor substrate using the mask as a doping mask. A gate electrode aligned with the gate region is formed on the semiconductor substrate using the mask as a gate alignment mask.

According to another embodiment of the present invention, a MOS device is provided, which includes a gate electrode on a semiconductor substrate, and which is spaced apart sources aligned with the gate electrode and formed in the semiconductor substrate. And drain regions. An impurity doped channel region is under the gate electrode and is spaced apart from the source and drain regions.

DETAILED DESCRIPTION Hereinafter, the present invention will be described with reference to the accompanying drawings, in which like reference numerals designate like elements.
1 is a graphical illustration of impurity doping found in a well region or substrate region under a gate electrode of a conventional MOS device.
2 through 10 are cross-sectional views illustrating a portion of a MOS integrated circuit device and a fabrication method in accordance with various embodiments of the present invention.

The following detailed descriptions are merely exemplary and are not intended to limit the invention or its application or use. In addition, the present invention is directed to any theory expressly or implied provided in the technical field as described above, the background technology, the problem to be solved and the means for solving the problem or in the following detailed description of the invention. It is not limited.

1 is a graphical illustration of impurity doping found in the well region or substrate region under the gate electrode of a conventional MOS device, illustrating the problems involved in this conventional structure. The vertical axis 30 represents the impurity doping concentration in the well region and the horizontal axis 32 represents the distance from the substrate surface. Graphic line 34 shows that the impurity doping concentration increases from a predetermined value 36 at the substrate surface to a peak value 38 at a predetermined location near the surface below. Peak value 38 represents impurity doping concentration due to threshold adjust ion implantation. Further entering the well region, the impurity doping concentration begins to decrease from the peak value 38 and then increases again up to the new peak value 40, where the new peak value 40 is determined by ion implantation designed to counteract the punch through state. Punch through implant: Impurity doping concentration resulting from punch through implant. The peak value of the punch-through ion implantation is found at position 42, which corresponds to the junction depth x _j of the source and drain regions. Thus, the punch-through implant positioned to correspond to the source / drain junction depth will be located at the most problematic depth with respect to the increased junction capacitance. The impurity doping concentration decreases below the punch-through ion implantation concentration, down to the general well impurity doping concentration 44, and may then increase again as illustrated in 46, in which case a buried layer is used under the wells. . Buried layers are sometimes used, especially in CMOS circuits to prevent latch-up.

2-10 are cross-sectional views illustrating portions of a MOS integrated circuit device and various embodiments for fabricating the same that may avoid problems due to impurity doping distributions as previously illustrated. A portion of the illustrated IC device 50 is one MOS transistor. According to various embodiments to be described later, this one transistor may be an n-channel MOS transistor or a p-channel MOS transistor, but for illustrative purposes only, an n-channel transistor will be described. The completed IC may include an n-channel transistor, a p-channel transistor, or it may be a CMOS IC containing two types. Embodiments of the invention can be applied to any or all transistors of such an IC.

Various steps relating to MOS transistor fabrication are well known and, for the sake of simplicity, many conventional steps will be omitted herein without mentioning only briefly or providing well known process details. Although the term "MOS device" strictly refers to a device having a metal gate electrode and an oxide gate insulator, the term herein refers to a conductive material placed over a gate insulator (oxide or other insulator) placed on a semiconductor substrate. It will be used to collectively refer to any semiconductor device including a gate electrode (metal or other conductive material).

A method for manufacturing an IC device 50 according to one embodiment of the present invention is disclosed by providing a semiconductor substrate 60 having a surface 62, as shown in FIG. The semiconductor substrate may be silicon, silicon mixed with germanium, or other semiconductor materials commonly used in the semiconductor industry. Isolation regions 64, such as shallow trench isolation (STI), extend from the surface into the substrate and are formed in the semiconductor substrate, and serve to help define the well region 66. Isolation regions 64 provide electrical isolation between devices formed in well region 66 and devices formed in adjacent well regions. Although not used in all ICs, a buried layer 68 may be formed below the well region. In the case of an n-channel MOS transistor, the well region is doped with p-type impurities. According to one embodiment of the invention, initially the semiconductor substrate is a lightly doped impurity doped p-type wafer, in which the p-type well region having a suitable impurity doping concentration is formed by ion implantation. Although not shown, similar n-type well regions can be formed by ion implantation to facilitate the fabrication of p-channel transistors. In an alternate embodiment, well region 66 may be formed by epitaxially growing a layer of semiconductor material over buried layer 68 and doping the well region by out diffusion from the buried layer. have. In order to adjust the impurity doping concentration in the well 66, one or more ion implantations may be used if necessary.

Next, the method for manufacturing a semiconductor device in accordance with one embodiment of the present invention continues by forming a thin insulating layer 70 on the surface 62 as shown in FIG. For example, a layer of dummy gate material 72, such as a polycrystalline silicon layer, is formed over the thin insulating layer 70.

Next, as shown in FIG. 4, the layer of dummy gate material is patterned to form a dummy gate 74. The dummy gate can be formed by conventional photolithography patterning and anisotropic etching, such as reactive ion etching (RIE). According to one embodiment of the present invention, by using a dummy gate as an ion implantation mask, by implanting n-type conductivity determining ions such as arsenic ions into the surface of the well region, the source and Drain extension 76 is formed. Thus, the source and drain extensions are self aligned to the dummy gate.

According to one embodiment, sidewall spacers 78 are formed on the edges of the dummy gate 74, as shown in FIG. 5. For example, sidewall spacers can be formed by depositing a layer of dielectric material, such as an oxide or nitride, over the dummy gate. The dielectric material is anisotropically etched by the anisotropic etching method which continuously etches the exposed portion of the thin insulating layer 70. Deep source and drain regions 80 by ion implanting n-type conductivity crystal ions, such as arsenic or phosphorous, into the surface of well region 66 using dummy gate and sidewall spacers as ion implantation masks. Is formed. Thus, deep source and drain regions are self-aligned to the sidewall spacers and also self-aligned to the dummy gate and spaced apart from the dummy gate. In order to activate the implanted source and drain implant ions, the device structure is thermally annealed, for example, by rapid thermal annealing (RTA).

A layer of gap fill material 82 is deposited over the dummy gate 74 and the surface 62 of the substrate 60. The layer of gapfill material may be a layer of dielectric material, for example, and should be a different material from the dummy gate material. As shown in FIG. 6, the layer of gapfill material is planarized by, for example, chemical mechanical planarization, which provides a flat top surface 84 of the layer of gapfill material and the dummy gate 74. To expose the top surface 86 of the substrate.

Although this description of the various embodiments focuses solely on the fabrication of n-channel MOS transistors, one of ordinary skill in the art will appreciate that while the source and drain impurity doping process steps as described above are performed, It will be appreciated that a layer of mask material may be applied to cover and protect p-channel devices that may be part of an IC device. After the n-type source and drain regions are completed, this mask layer can be removed and another mask layer applied to cover and protect the n-channel devices. The p-channel devices can then be processed in a manner similar to that described for n-channel devices, with the obvious change in the impurity doping type. After each of the device types has been implanted or after source and drain implantation has been performed for both device types, thermal annealing may be performed to activate the implanted ions.

After removing any protective mask layer that may have been formed on the n-channel devices during the processing of the p-channel devices, the method according to one embodiment of the present invention proceeds as shown in FIG. The dummy gate 74 is removed to form a recess 88 that extends through the layer of gapfill material 82. The dummy gate may be etched by either wet etching or plasma etching using an etching chemical that preferentially etches the dummy gate material rather than the gapfill material.

According to one embodiment of the method for manufacturing a semiconductor device, localized punch through and threshold implantation ion implantation are performed. As shown in Fig. 8, using the layer and sidewall spacers of the gapfill material as the implantation mask, the conductivity crystal ions pass through the recesses 88 and the localized sub-regions of the well region 66. into a region 90. Implant ions are selected to increase the conductivity of the well region 66 in the region 90. For the n-channel MOS transistor being described, p-type dopant ions are selected. The implanted ions can be for example boron ions. The energy of the implanted ions can be selected to adjust the range of implanted ion distribution peaks at any desired depth below surface 62. For example, the peak of the implanted ion distribution can be located at a depth between 25 nanometers (nm) and 50 nm below the surface. Because ions are implanted through the recesses 88 formed by removing the dummy gate 74, the localized sub-surface region 90 is self-aligned to the original position of the dummy gate and only in the channel region 91. Is optionally located. Also, because the source and drain regions 76, 80 are aligned to the dummy gate, the localized sub-surface region 90 is self-aligned to the source and drain regions and spaced apart from these regions. Localized sub-surface region 90 is located below and spaced apart from source and drain extension 76 and is spaced apart and located to the side of deep source and drain region 80. After most of the thermal processing steps used in the fabrication of the device 50, such as for example source and drain implant annealing, are implanted into the region 90, the implanted ions are implanted in the region 90 Their subsequent heat spread will be very small.

Although not illustrated in the figures, according to another embodiment, the localized sub-surface region 90 may also be formed as follows. After forming the recess 88 as illustrated in FIG. 7, the exposed portions of the thin insulating layer 70 are first removed using a gap fill material 82 and sidewall spacers as an etch mask, and then the semiconductor substrate. A shallow recess is etched into the surface of 60. Such shallow recesses may, for example, be etched to a depth of about 25 nm. The region 90 can be implanted into the surface of the shallow recess by low energy ion implantation. After implanting the region 90, an undoped silicon layer is epitaxially grown inside the shallow recess of the surface of the semiconductor substrate 60 by a selective epitaxial growth process, which covers the region 90 and This is for substantially restoring the surface of the semiconductor substrate 60. The selective epitaxial growth process can be performed at low temperature so that the implanted ions are not substantially redistributed by thermal diffusion. As is well known to those skilled in the art, in epitaxial growth, epitaxial growth process conditions are adjusted so that epitaxial growth is performed only on the exposed crystalline material, in this example only in recesses formed in the semiconductor substrate 60. Epitaxial growth is performed.

Regardless of how the sub-surface region 90 is formed, localization is achieved because the localized sub-surface region 90 with increased impurity doping is not directly in contact with the source region or the drain region. The sub-surface region does not increase the source-substrate capacitance as well as the drain-substrate capacitance, thus not reducing the switching speed of the device and also increasing the band-band leakage. However, because of this location, localized sub-surface regions with increased impurity doping will effectively reduce short channel effects and punch through related problems without increasing halo or source drain doping. Can be.

A localized sub-surface region 90 is formed in the channel region and then the surface of the well region at the bottom of the recess 88 is etched and cleaned. As shown in FIG. 9, a gate insulator layer 92 is formed on the surface 62 of the well region 66 at the bottom of the recess 88. A deposited layer or layers of gate electrode material 94 are formed over the gate insulator layer. According to one embodiment, the gate insulator layer is or includes a high dielectric constant (high-k) insulator. Gate insulator 92 may be, for example, a thermally grown layer of silicon dioxide (possibly mixed with nitrogen), on which a layer of hafnium oxide or other high-k dielectric material may be formed. Composite silicon insulators are high-k insulators because they have a larger dielectric constant than that of silicon dioxide alone. The gate electrode material can be, for example, a metal layer overlying a polycrystalline silicon layer. As is well known to those skilled in the art, the metal layer can be selected so that an appropriate threshold voltage is obtained for the MOS device under manufacture. In alternative embodiments, gate insulator layer 92 may be, for example, a layer of thermally grown silicon dioxide and gate electrode material 94 may be a layer of polycrystalline silicon or amorphous silicon.

After deposition of the gate electrode material 94, the device structure is planarized, for example by CMP, so that excess gate electrode material overlying the layer of gap fill material 82 is removed, as shown in FIG. This planarization process completes the formation of the gate electrode 96 located above the channel region 91 and the localized sub-surface region 90.

If a CMOS device is fabricated, the p-localized sub-surface region doped with n-type dopant ions may be formed in a manner similar to the manner in which the region 90 is formed for an n-channel device. It may be formed in the channel region of the channel device. With appropriate modifications to set threshold voltages for different device types, the gate dielectric and gate electrode for the p-channel device are formed in a similar manner as for the n-channel device. A metal other than for the n-channel device may be selected as the gate electrode material of the p-channel device.

As will be appreciated by those skilled in the art, device 50 may be completed by conventional intermediate process steps and back end process steps. For example, such process steps may include etching the contact opening through the layer of gapfill material to expose the surface regions of the source and drain regions, forming a silicide and / or extending into the contact opening to extend the surface region. Forming a metal contact reaching them, forming conductive device wires, forming an interlayer dielectric, and the like.

While at least one exemplary embodiment has been provided in the foregoing detailed description, it should be noted that a large number of variations may exist. It should also be noted that these exemplary embodiments are merely exemplary and are not intended to limit the scope, applicability, and configuration of the present invention in any way. Alternatively, the foregoing detailed description of the invention will provide those skilled in the art with a convenient road map in which exemplary embodiments of the invention may be implemented. In addition, it should be noted that various changes may be made in the size, spacing, and doping of components without departing from the scope of the present invention as disclosed in the appended claims and their legal equivalents.

Claims

As a method of manufacturing a MOS device,
Depositing a dummy gate material layer on a surface of a semiconductor substrate and patterning the dummy gate material layer to form a dummy gate;
Implanting impurities into source and drain regions aligned with the dummy gate and spaced apart from each other;
Depositing a gap fill material over the semiconductor substrate and the dummy gate;
Removing a portion of the gapfill material to expose the top surface of the dummy gate;
Removing the dummy gate to form a recess extending through the gapfill material;
Implanting conduction determining ions through the recess and into the semiconductor substrate to form a doped channel region between the spaced source and drain regions;
Exposing a portion of the surface of the semiconductor substrate over the doped channel region; And
Forming a gate insulator and a gate electrode over the portion of the surface
Method of manufacturing a Morse device comprising a.

The method of claim 1,
Depositing the dummy gate material layer,
Depositing a layer of polycrystalline silicon.

The method of claim 1,
Forming sidewall spacers on the dummy gate
The method of manufacturing a Morse device further comprising.

The method of claim 3,
Injecting impurities into the source and drain regions spaced apart from each other,
Implanting impurities into source and drain extensions aligned with the dummy gate; And
Implanting impurities into the dee source and drain regions aligned with the sidewall spacers
Method of manufacturing a MOS device comprising a.

The method of claim 1,
Depositing the gapfill material comprises depositing a dielectric material and removing the portion of the gapfill material comprises chemical mechanical planarization.

The method of claim 1,
Injecting the conductivity crystal ions,
Implanting ions into the semiconductor substrate to have a peak dopant concentration at 25-50 nm below the semiconductor substrate.

The method according to claim 6,
Injecting the conductivity crystal ions,
And implanting one type of ions to locally increase the conductivity of the substrate.

The method of claim 1,
Forming the gate insulator and the gate electrode,
Depositing a high dielectric constant insulator material and a metal layer overlying the dielectric material.

9. The method of claim 8,
Performing chemical mechanical planarization of the metal layer
The method of manufacturing a Morse device further comprising.

As a method of manufacturing a MOS device,
Forming a mask defining a gate region over the surface of the semiconductor substrate;
Forming source and drain regions in the semiconductor substrate aligned with the gate region;
Using the mask as a doping mask to form an enhanced doping sub-surface impurity region in the semiconductor substrate; And
Forming a gate electrode on the semiconductor substrate to be aligned with the gate region using the mask as a gate alignment mask
Method of manufacturing a Morse device comprising a.

The method of claim 10,
Forming the mask,
Depositing a dummy gate material layer;
Patterning the dummy gate material layer;
Forming sidewall spacers on the patterned dummy gate material layer;
Depositing a layer of gapfill material over the patterned dummy gate material layer;
Removing a portion of the gapfill material to expose a top portion of the patterned dummy gate material layer; And
Removing the patterned dummy gate material layer
Method of manufacturing a Morse device comprising a.

The method of claim 11,
Forming the source and drain regions,
Forming a first region aligned with the patterned dummy gate material layer; And
Forming a second region aligned with the sidewall spacers
Method of manufacturing a MOS device comprising a.

The method of claim 10,
Forming the sub-surface impurity region of the enhanced doping,
Using the mask as an ion implantation mask to implant selected conductivity crystal ions to increase the conductivity of the sub-surface impurity region.

The method of claim 13,
Injecting the conductivity crystal ions,
Implanting ions having a range selected to locate the peak concentration of the sub-surface impurity region at 25-50 nm below the substrate.

The method of claim 10,
Forming the sub-surface impurity region of the enhanced doping,
Etching a recess into the surface of the semiconductor substrate using the mask as an etch mask;
Doping the semiconductor substrate at the bottom of the recess using the mask as a doping mask; And
Epitaxially growing a layer of substantially undoped semiconductor material to fill the recess
Method of manufacturing a MOS device comprising a.

16. The method of claim 15,
Doping the semiconductor material,
And implanting the semiconductor substrate using the mask as an ion implantation mask.

The method of claim 10,
Forming the gate electrode,
Cleaning a portion of the surface exposed by the mask;
Depositing a layer of gate insulating material over the surface;
Depositing a layer of gate electrode material over the layer of gate insulating material; And
Removing the gate electrode material over the mask
Method of manufacturing a MOS device comprising a.

18. The method of claim 17,
Depositing the layer of gate insulating material comprises depositing a layer of insulating material having a high dielectric constant and depositing the layer of gate electrode material comprises depositing a metal layer. The method of manufacturing the Morse device.

The method of claim 10,
Etching a recess into the surface of the semiconductor substrate using the mask as an etch mask to recess the surface in the gate region
The method of manufacturing a Morse device further comprising.

As a Morse device,
A gate electrode on the semiconductor substrate;
Spaced apart source and drain regions aligned with the gate electrode and formed in the semiconductor substrate; And
An impurity doped channel region under the gate electrode and spaced apart from the source and drain regions
Morse device comprising a.