KR20120109196A - Delay locked loop and semiconductor device including the same - Google Patents

Abstract

A delay locked loop and a semiconductor device including the same are disclosed. The delay lock loop may include a delay unit for delaying an input clock by a first delay amount to generate an output clock, a replica control unit for generating a control signal for adjusting a replica delay amount corresponding to a level of a power supply voltage, and responding to the control signal. And a replica delay unit for generating a feedback clock by delaying the output clock by the adjusted replica delay amount, and a phase comparison unit for adjusting the first delay amount by comparing a phase of the input clock and the feedback clock.

Description

Delay locked loop and semiconductor device including the same {DELAY LOCKED LOOP AND SEMICONDUCTOR DEVICE INCLUDING THE SAME}

The present invention relates to a delay locked loop and a semiconductor device including the same.

Semiconductor devices such as DDR SDRAM (Double Data Rate Synchronous DRAM) transfer various signals and data using an internal clock synchronized with an external clock used in an external system. At this time, the clock input to the circuit element is initially applied in a state of being synchronized with an external clock, but when it is delayed through various components in the device and output to the outside of the device, the clock is not synchronized with the external clock. Therefore, for stable transmission of signals and data, the internal and external clocks must be accurately synchronized in the external system by compensating the internal clock for the time that data is carried on the bus in the circuit element. To accomplish this role, a delayed locked loop (DLL) is used.

1 is a block diagram of a delay lock loop according to the prior art.

Referring to FIG. 1, the delay locked loop includes a delay unit 101, a replica delay unit 103, and a phase comparator 105.

The delay unit 101 delays the input clock INCLK by a first delay amount to generate an output clock OUTCLK. In general, the delay unit 101 includes a plurality of delay cells having a unit delay amount.

The replica delay unit 103 generates a feedback clock FBCLK by delaying the output clock OUTCLK by a replica delay amount. Here, the replica delay amount is a value for modeling delay elements that the output clock OUTCLK of the delay locked loop will pass through in the semiconductor device.

The phase comparator 105 detects a phase difference between the input clock INCLK and the feedback clock FBCLK and adjusts the first delay amount such that both clocks INCLK and FBCLK have the same phase. Create

The delay unit 101 determines the first delay amount in response to the control signal CTRL, and generates the output clock OUTCLK again.

As a result, the semiconductor device including the delay locked loop may operate in precise synchronization with an external system.

Meanwhile, various circuit elements in the semiconductor device may be driven by receiving a power supply voltage through different paths. For example, a clock buffer in a memory device may receive a first power supply voltage VDD, and a delay locked loop may receive a second power supply voltage VPERI. Here, the first power supply voltage VDD and the second power supply voltage VPERI have power supply voltages having the same voltage level or different circuits due to voltage noise generated in the respective paths because the supplied paths are different from each other. Voltage levels applied to the device may vary.

In this case, during a read operation of outputting data stored in the memory device, voltage noise occurs in the first power supply voltage VDD, so that the first power supply voltage VDD is significantly changed compared to the second power supply voltage VPERI. In this case, the phase difference between the data strobe signal DQS and the external clock of the data output unit DQ generated by using the output clock of the delay locked loop increases. Therefore, a problem may occur in which a condition specified in a spec such as tDQSCK (DQS edge to clock edge skew) is not satisfied.

The present invention has been proposed to solve the above problems, and an object of the present invention is to provide a delay fixing loop capable of adjusting a delay amount according to a level of a power supply voltage and a semiconductor device including the same.

The semiconductor device according to the present invention for achieving the above object is driven by receiving a first power supply voltage and being driven by receiving a clock buffer and a second power supply voltage for transferring an external clock to an input clock and corresponding to the first power supply voltage. And a delay lock loop for delaying the input clock to generate an output clock.

The delay lock loop may include a delay unit configured to delay the input clock by a first delay amount to generate the output clock, and generate a control signal for adjusting a replica delay amount corresponding to the level of the first power supply voltage. A replica delay unit for generating a feedback clock by delaying the output clock by the adjusted replica delay in response to the control signal, and a phase for adjusting the first delay amount by comparing a phase of the input clock and the feedback clock It includes a comparison unit.

The replica delay unit may include a plurality of delay stages each having a predetermined delay amount, and may generate the feedback clock by bypassing some of the plurality of delay stages in response to the control signal.

According to the present invention, the clock skew of the semiconductor device caused by the change in the power supply voltage can be reduced by adjusting the delay amount of the replica delay unit in the delay lock loop in accordance with the level of the power supply voltage.

1 is a block diagram of a delay lock loop according to the prior art.
2 is a configuration diagram of an embodiment of a semiconductor device according to the present invention.
3 is a block diagram of an embodiment of the replica controller 203 of FIG. 2.
4 is a diagram illustrating an embodiment of the control signal generator 303 of FIG. 3.
FIG. 5 is a diagram illustrating an embodiment of the replica delay unit 201 of FIG. 2.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

2 is a configuration diagram of an embodiment of a semiconductor device according to the present invention.

Referring to FIG. 2, the semiconductor device is driven by being supplied with a first power supply voltage VDD, and a clock buffer 210 and a second power supply voltage VPERI that transfer an external clock CLK to an input clock INCLK. It is driven by being applied to, and includes a delay locked loop 200 for delaying the input clock (INCLK) to generate an output clock (OUTCLK) by a delay amount corresponding to the first power supply voltage (VDD).

The delay lock loop 200 includes a delay unit 101 which delays the input clock INCLK by a first delay amount to generate an output clock OUTCLK, and a replica delay amount corresponding to the level of the first power supply voltage VDD. The replica control unit 203 which generates the control signal DL <0: 3> for adjusting the output signal delays the output clock OUTCLK by the adjusted replica delay in response to the control signal DL <0: 3>. A replica delay unit 201 for generating the feedback clock FBCLK and a phase comparison unit 105 for adjusting the first delay amount by comparing the phase of the input clock INCLK and the feedback clock FBCLK.

The delay locked loop 200 adjusts the delay amount of the replica delay unit 201 according to the level of the first power supply voltage VDD to minimize the occurrence of skew due to the change of the first power supply voltage VDD. . Specifically, assuming that the second power supply voltage VPERI is maintained at a constant level, when the first power supply voltage VDD is lowered, the replica delay amount of the replica delay unit 103 is increased, and the first power supply voltage (VPERI) is increased. If VDD) is increased, the operation may be performed by reducing the replica delay amount.

For example, if the semiconductor device according to the present invention is a memory device, in the conventional memory device, when the first power voltage VDD applied to the clock buffer 210 is greatly shaken during the read operation, the delay locked loop 200 may be removed. A problem arises in that the phase difference between the data strobe signal DQS and the external clock CLK of the data output circuit generated using the output clock OUTCLK is larger than the tDQSCK value specified in the specification. However, in the present invention, this problem can be solved by flexibly adjusting the delay amount of the replica delay unit 201 according to the level of the first power supply voltage VDD.

In addition, the present invention may be applied to a central processing unit (CPU), a graphics processing unit (GPU), a high speed interface circuit and various controllers in which a delay locked loop is used in addition to a memory device.

3 is a block diagram of the replica controller 203 of FIG. 2, and FIG. 4 is a block diagram of the control signal generator 303 of FIG. 3.

Referring to FIG. 3, the replica controller 203 may include a power supply voltage detector 301 for detecting a level of the first power supply voltage VDD, and a detection result of the power supply voltage detector 301 (ZVDD <0: 1). And a control signal generator 303 for generating a control signal DL <0: 3> for adjusting the replica delay amount in response to &quot;).

The power supply voltage detector 301 may generate a 2-bit sensing signal ZVDD <0: 1> corresponding to the level of the first power supply voltage VDD. For example, if the level of the first power supply voltage VDD is 2V in normal operation, the value of ZVDD <0: 1> is "00" when VDD <1.6V, and "01" when 1.6V <VDD <1.8V. "," 10V when 1.8V <VDD <2.0V, and "11" when VDD> 2.0V.

As illustrated in FIG. 4, the control signal generator 303 may include a plurality of NAND gates 401 to 404 and inverters 411 to 418, and may detect the power voltage detector 301. The control signals DL <0> to DL <3> may be generated by decoding the result ZVDD <0: 1>. For example, if ZVDD <0: 1> = "00", enable DL <0> as "High"; if ZVDD <0: 1> = "01", make DL <1> as "High". Activate, and activate DL <2> as "high" if ZVDD <0: 1> = "10", activate DL <3> as "high" if ZVDD <0: 1> = "11". .

FIG. 5 is a diagram illustrating an embodiment of the replica delay unit 201 of FIG. 2.

Referring to FIG. 5, the replica delay unit 201 includes a plurality of delay stages 501, 503, 505, and 507 having a unit delay amount, and each of the delay stages 501, 503, 505, and 507 has a delay. It can be composed of two NAND gates. Here, only four delay stages 501, 503, 505, and 507 are shown for convenience of description, and it is apparent that the replica delay unit 201 may include more delay stages.

The delay stages 501, 503, 505, and 507 receive the outputs of the first power supply voltage VDD and the corresponding NAND gates 511, 513, 515, and 517, respectively. The NAND gates 511, 513, 515, and 517 have the output clock OUTCLK and the control signals DL <3>, DL <2>, DL <1>, and DL <0> generated by the delay unit 101, respectively. When the control signal is activated as "high", the output clock OUTCLK is transferred to the corresponding delay stage.

For example, if DL <3>, DL <2>, DL <0> are "low" and DL <1> is "high", as shown, the output clock OUTCLK is first. The two delay stages 501 and 503 are bypassed, are input to the third delay stage 505 through the NAND gate 515, and are output to the feedback clock FBCLK through the delay stages 505 and 507. do. In this way, the amount of delay of the replica delay unit 201 may be adjusted according to the level of the first power voltage VDD.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

Claims (7)

A delay unit generating an output clock by delaying the input clock by a first delay amount;
A replica controller configured to generate a control signal for adjusting a replica delay amount corresponding to the level of the power supply voltage;
A replica delay unit configured to delay the output clock by the adjusted replica delay in response to the control signal to generate a feedback clock; And
A phase comparator configured to compare the phase of the input clock and the feedback clock to adjust the first delay amount
Delay fixed loop comprising a.
The method of claim 1,
The replica delay unit
A plurality of delay stages each having a predetermined delay amount
Delayed fixed loop.
The method of claim 2,
The replica delay unit
Generating a feedback clock by bypassing a part of the plurality of delay stages in response to the control signal;
Delayed fixed loop.
A clock buffer driven by a first power supply voltage and transferring an external clock to an input clock; And
A delay locked loop driven by receiving a second power supply voltage and delaying the input clock by a delay amount corresponding to the first power supply voltage to generate an output clock;
.
6. The method of claim 5,
The delay lock loop
A delay unit generating the output clock by delaying the input clock by a first delay amount;
A replica controller configured to generate a control signal for adjusting a replica delay amount corresponding to the level of the first power supply voltage;
A replica delay unit configured to delay the output clock by the adjusted replica delay in response to the control signal to generate a feedback clock; And
A phase comparator configured to compare the phase of the input clock and the feedback clock to adjust the first delay amount
.
6. The method of claim 5,
The replica delay unit
A plurality of delay stages each having a predetermined delay amount
Semiconductor device.
The method of claim 8,
The replica delay unit
Generating a feedback clock by bypassing a part of the plurality of delay stages in response to the control signal;
Semiconductor device.

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