KR20120043336A - Thin film transistor array substrate and method for manufacturing of the same - Google Patents

Abstract

PURPOSE: A thin film transistor array substrate and a manufacturing method thereof are provided to prevent optical currents of an active layer due to light irradiation. CONSTITUTION: A gate insulating film(125) is located on a gate electrode(120a). An active layer(130) is located on the gate insulating film. An etch stopper(135) is located on the active layer. A source electrode(140a) and a drain electrode(140b) are located on the active layer and the etch stopper. A passivation film(145) is located on the source electrode and the drain electrode. A pixel electrode(150a) is located on the passivation film. A light blocking pattern(160) is located on the pixel electrode.

Description

Thin Film Transistor Array Substrate And Method For Manufacturing Of The Same

The present invention relates to a thin film transistor array substrate and a method for manufacturing the same, and more particularly, to a thin film transistor array substrate for forming a pixel electrode and a light shielding pattern using a diffraction exposure mask and a method of manufacturing the same.

The present invention relates to a thin film transistor and a display device including the same.

Recently, the importance of the flat panel display (FPD) has increased with the development of multimedia. In response, such as liquid crystal display (LCD), plasma display panel (PDP), field emission display (FED), organic light emitting device (Organic Light Emitting Device) Various displays have been put into practical use.

Among them, the liquid crystal display device has better visibility than the cathode ray tube, the average power consumption and the heat generation amount are small, and the electroluminescent display device has a response speed of 1 ms or less, high response speed, low power consumption, Since it is self-luminous, there is no problem in viewing angle, and thus it is attracting attention as a next generation display device.

There are two methods of driving the display device, a passive matrix method and an active matrix method using a thin film transistor. The passive matrix method forms the anode and the cathode so as to be orthogonal and selects a line, whereas the active matrix method drives the thin film transistor to each pixel electrode and is driven according to the voltage maintained by the capacitor capacitance connected to the gate electrode of the thin film transistor. That's the way it is.

In the thin film transistor, not only the characteristics of the basic thin film transistor such as mobility and leakage current, but also durability and electrical reliability for maintaining a long life is very important. Here, the active layer of the thin film transistor is mainly formed of amorphous silicon or polycrystalline silicon, the amorphous silicon has the advantage that the film forming process is simple and the production cost is low, but the electrical reliability is not secured. In addition, polycrystalline silicon is very difficult to apply a large area due to the high process temperature, there is a problem that the uniformity according to the crystallization method is not secured.

On the other hand, when the active layer is formed of oxide, high mobility can be obtained even when the film is formed at a low temperature, and since the resistance change is large depending on the oxygen content, it is very easy to obtain the desired physical properties. It's attracting great attention. In particular, examples thereof include zinc oxide (ZnO), indium zinc oxide (InZnO), indium gallium zinc oxide (InGaZnO ₄ ), and the like.

However, the conventional thin film transistor including the oxide active layer has an unstable characteristic in which photocurrent is generated by an external light source, and thus there is a problem in that reliability is lowered.

Accordingly, the present invention provides a thin film transistor array substrate and a method for manufacturing the same, which can prevent the light source from being irradiated to the active layer to prevent photocurrent from occurring.

In order to achieve the above object, a thin film transistor array substrate according to an embodiment of the present invention is a substrate, a gate electrode located on the substrate, a gate insulating film located on the gate electrode, an active positioned on the gate insulating film A layer, an etch stopper positioned on the active layer, a source electrode and a drain electrode positioned on the active layer and the etch stopper, a passivation layer positioned on the source electrode and the drain electrode, and a pixel positioned on the passivation layer. The light blocking pattern may include an electrode and a light blocking pattern on the pixel electrode.

The light blocking pattern may have a structure covering all of the active layers.

The pixel electrode may cover all of the active layer and be formed to a region outside the active layer.

The light blocking pattern may be made of any one or an alloy thereof selected from the group consisting of aluminum (Al), neodymium (Nd), molybdenum (Mo), chromium (Cr), and titanium (Ti).

The semiconductor device may further include a gate pad and a data pad spaced apart from the gate electrode, and pad electrodes may be connected to the gate pad and the data pad, respectively.

The thin film transistor array substrate may be used as a substrate of a liquid crystal display device or an organic light emitting display device.

In addition, according to an embodiment of the present invention, a method of manufacturing a thin film transistor array substrate includes forming a gate electrode on a substrate, forming a gate insulating film on the gate electrode, and forming an active layer on the gate insulating film. Forming an etch stopper on the active layer, forming a source electrode and a drain electrode on the active layer and the etch stopper, forming a passivation film on the substrate including the source electrode and the drain electrode The method may include forming a transparent conductive film and a light shielding film on the passivation film, and patterning the transparent conductive film and the light shielding film using a diffraction exposure mask to form a pixel electrode and a light shielding pattern.

The method may further include forming a gate pad at the same time as forming the gate electrode. The method may further include forming a data pad at the same time as forming the source electrode and the drain electrode.

The patterning of the transparent conductive film and the light shielding film using a diffraction exposure mask comprises: aligning a diffraction exposure mask on the transparent conductive film and the light shielding film, applying the photosensitive film on the light shielding film, and then applying the diffraction exposure mask. Forming a first photoresist layer pattern and a second photoresist layer pattern having a thickness step by using the first conductive photoresist layer; and forming the transparent conductive layer pattern and the light shielding layer pattern by etching the transparent conductive layer and the light shielding layer, wherein the first photoresist layer pattern and the second photoresist layer are formed. Ashing the pattern to reduce the thickness of the first photoresist pattern and removing the second photoresist pattern; etching the exposed light shielding pattern by removing the second photoresist pattern to form a pixel electrode and a pad electrode; The light blocking pattern may be formed by removing the first photoresist pattern.

The method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the present invention has an advantage of forming a light shielding pattern on the active layer to prevent photocurrent generation of the active layer due to light irradiation. In addition, since the light shielding pattern may be formed using a diffraction exposure technique without the addition of a mask, there is an advantage in that the process is easy and the manufacturing cost is reduced.

1 is a cross-sectional view showing a thin film transistor array substrate according to an embodiment of the present invention.
2A to 2H are diagrams illustrating processes for manufacturing a thin film transistor array substrate according to an embodiment of the present invention.
3 is a view illustrating an organic light emitting display device according to an embodiment of the present invention.
4 illustrates a liquid crystal display according to an exemplary embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a thin film transistor array substrate according to an embodiment of the present invention.

Referring to FIG. 1, a thin film transistor array substrate 100 according to an embodiment of the present invention is a substrate used for a liquid crystal display device or an organic light emitting display device, and a plurality of thin film transistors are formed.

In more detail, the gate electrode 120a is positioned on the substrate 110, and the gate pad 120b is positioned in a region spaced apart from the gate electrode 120a. In addition, a gate insulating layer 125 that insulates the gate electrode 120a and the gate pad 120b is positioned.

The active layer 130 is positioned on the gate insulating layer 125 corresponding to the gate electrode 120a. The etch stopper 135 is positioned on a predetermined region of the active layer 130.

A source electrode 140a and a drain electrode 140b are disposed on the etch stopper 135 to cover both ends of the active layer 130. The data pad 140c is positioned in an area spaced apart from the source electrode 140a and the drain electrode 140b.

Accordingly, a thin film transistor TFT including the gate electrode 120a, the active layer 130, the source electrode 140a, and the drain electrode 140b is formed.

The passivation layer 145 is positioned on the entire surface of the substrate 110 including the thin film transistor TFT. The pixel electrode 150a is positioned on the passivation layer 145. The pixel electrode 150a is formed over an area corresponding to the active layer 130, and pad electrodes 150b connected to the gate pad 120b and the data pad 140c are formed, respectively.

The light blocking pattern 160 is positioned on the pixel electrode 150a corresponding to the active layer 130. The light blocking pattern 160 is formed to cover at least the active layer 130 to prevent light from being irradiated onto the active layer 130.

Hereinafter, a method of manufacturing a thin film transistor array substrate according to an embodiment of the present invention described above is as follows.

2A to 2H are views illustrating a method of manufacturing a thin film transistor array substrate according to an embodiment of the present invention.

Referring to FIG. 2A, a gate electrode 220a and a gate pad 220b are formed on a substrate 210 including glass, plastic, or metal. The gate electrode 220a and the gate pad 220b may be formed of chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), or the like.

Subsequently, a gate insulating film 225 is formed on the substrate 210 including the gate electrode 220a and the gate pad 220b. The gate insulating layer 225 may be formed of silicon oxide (SiOx), silicon nitride (SiNx), or multiple layers thereof.

Next, an active layer 230 is formed on the gate insulating layer 225 in a region corresponding to the gate electrode 220a. The active layer 230 may be formed of an oxide, and may be formed of zinc oxide (ZnO), indium zinc oxide (InZnO), zinc tin oxide (ZnSnO), or indium gallium zinc oxide (InGaZnO ₄ ).

The etch stopper 235 is formed by depositing and patterning silicon oxide or silicon nitride on the active layer 230. The etch stopper 235 may prevent the active layer 230 disposed below when the source and drain electrodes are patterned.

Next, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) on the substrate 210 including the etch stopper 235. One or more alloys selected from the group consisting of one or more alloys are stacked and patterned to form a source electrode 240a, a drain electrode 240b, and a data pad 240c.

In this case, the source electrode 240a and the drain electrode 240b are formed to be connected to both ends of the active layer 230 over a portion of the etch stopper 235, respectively. Accordingly, a thin film transistor TFT including the gate electrode 220a, the active layer 230, the source electrode 240a, and the drain electrode 240b is formed.

Next, referring to FIG. 2B, a passivation film 245 is formed on the entire surface of the substrate 210 including the thin film transistor TFT. The passivation layer 245 protects the thin film transistor TFT below, and may be formed of silicon oxide (SiOx), silicon nitride (SiNx), or multiple layers thereof.

Subsequently, the passivation layer 245 may be etched to form a first via hole 247a exposing the drain electrode 240b, and the passivation layer 245 or the gate insulating layer 225 may be etched to form a gate pad 220b. The second via hole 247b exposing the second via hole 247b and the third pad hole 247c exposing the data pad 220c are formed.

Next, the transparent conductive film 250a is laminated on the entire surface of the substrate 210. The transparent conductive film 250a serves as a pixel electrode later, and may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

In this case, the transparent conductive film 250a is connected to the drain electrode 240b through the first via hole 247a, connected to the gate pad 220b through the second via hole 247b, and through the third via hole 247c. It is connected to the data pad 240c.

Then, the light shielding film 250b is laminated on the transparent conductive film 250a. The light blocking film 250b serves to block light from being irradiated to the active layer 230 later, and has high reflectance of aluminum (Al), neodymium (Nd), molybdenum (Mo), chromium (Cr), and titanium (Ti). Any one selected from the group consisting of) or these may be formed of an alloy. Alternatively, it may be formed of a black matrix material.

Next, referring to FIG. 2C, the photosensitive film 260 is coated on the substrate 210 including the transparent conductive film 250a and the light blocking film 250b by spin coating. The photoresist layer 260 may be a material that is later decomposed and removed when light is irradiated with a positive photoresist.

Subsequently, the diffraction exposure mask 270 including the transmission part 270a, the transflective part 270b, and the blocking part 270c is aligned on the substrate 210 on which the photoresist film 260 is formed, and then irradiated with ultraviolet (UV) light.

Next, referring to FIG. 2D, the first photoresist layer pattern 260a and the second photoresist layer pattern 260b having a thickness step may be formed by using a diffraction exposure technique through the diffraction exposure mask 270.

More specifically, by using a diffraction exposure technique using the diffraction exposure mask 270, the blocking part 270c is applied to the first photoresist pattern 260a in which the photoresist film 260 facing the blocking part 270c is left as it is. ) And a second photoresist film having a thickness of less than half of the first photoresist pattern 260a by light that is applied by the transflective part 270b so that the photosensitive film 260 facing the transflective part 270b is diffracted and transmitted. The pattern 260b is formed. The photosensitive film 260 facing the transmission part 270a is decomposed and removed during development, thereby exposing the surface of the light blocking film 250b.

In this case, the first photoresist layer pattern 260a is formed in the region where the light shielding pattern covering the active layer 230 is to be formed, and the second photoresist layer pattern 260b is formed in the region where the pixel electrode and the pad electrode are to be formed.

Next, referring to FIG. 2E, the transparent conductive film 250a and the light shielding film 250b are etched using the first photoresist film pattern 260a and the second photoresist film pattern 260b to form the transparent conductive film pattern 250c and the light shielding film pattern. Each 250d is formed.

Next, referring to FIG. 2F, the second photoresist layer pattern 260b is removed by an ashing process, and the thickness of the first photoresist layer pattern 260a is reduced by the removed thickness of the second photoresist layer pattern 260b.

Next, referring to FIG. 2G, the light shielding layer pattern may be formed by using an etching solution capable of etching the light shielding layer pattern 250d among the transparent conductive layer pattern 250c and the light shielding layer pattern 250d in the region where the second photoresist layer pattern 260b is removed. The pixel electrode 280a, the pad electrode 280b, and the light shielding pattern 260a are formed by etching 250d.

Then, the first photoresist pattern 260a remaining on the substrate 210 is stripped and removed to manufacture a thin film transistor array substrate according to an embodiment of the present invention, as shown in FIG. 2H.

As described above, the method of manufacturing the thin film transistor array substrate according to the exemplary embodiment of the present invention has the advantage of preventing the photocurrent generation of the active layer due to light irradiation by forming a light shielding pattern on the active layer.

In addition, since the light shielding pattern may be formed using a diffraction exposure technique without the addition of a mask, there is an advantage in that the process is easy and the manufacturing cost is reduced.

The thin film transistor array substrate according to an embodiment of the present invention described above may be used as a substrate of an organic light emitting display device and a liquid crystal display device.

3 is a view showing an organic light emitting display device according to an embodiment of the present invention, Figure 4 is a view showing a liquid crystal display device according to an embodiment of the present invention. Hereinafter, the same reference numerals as in FIG. 1 will be omitted.

Referring to FIG. 3, in the organic light emitting display device 300 according to an exemplary embodiment, the bank layer 310 is positioned on the pixel electrode 150a. The bank layer 310 flattens the lower step and defines a pixel area, and includes an opening 310 exposing the pixel electrode 150a.

The organic layer 320 including the emission layer is positioned on the pixel electrode 150a exposed by the opening 310. The organic layer 320 may include at least one of a hole injection layer, a hole transport layer, an electron transport layer, or an electron injection layer. The opposite electrode 330 is positioned on the substrate 110 on which the organic layer 320 is formed to form the organic light emitting display device 300 according to the present invention.

Meanwhile, referring to FIG. 4 illustrating a liquid crystal display device 400 according to an exemplary embodiment, the liquid crystal layer 410 is positioned on the thin film transistor array substrate including the pixel electrode 150a.

In addition, an upper substrate 420 facing the thin film transistor array substrate is positioned. The black matrix 430 disposed between the pixel areas is positioned on the upper substrate 420. Color filters 440 corresponding to R, G, and B are disposed with the black matrix 430 interposed therebetween. The color filter 440 converts white light passing through the liquid crystal layer 410 from the light source into light corresponding to R, G, and B.

The overcoat layer 450 is positioned on the upper substrate 420 on which the color filter 440 is formed, and the common electrode 460 is positioned on the overcoat layer 450, thereby providing a liquid crystal display device according to an embodiment of the present invention. 400).

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. Therefore, the embodiments described above are to be understood as illustrative and not restrictive in all aspects. In addition, the scope of the present invention is shown by the claims below, rather than the above detailed description. Also, it is to be construed that all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention.

Claims (9)

Board;
A gate electrode on the substrate;
A gate insulating layer on the gate electrode;
An active layer on the gate insulating layer;
An etch stopper located on the active layer;
Source and drain electrodes disposed on the active layer and the etch stopper;
A passivation film on the source electrode and the drain electrode;
A pixel electrode on the passivation film; And
A thin film transistor array substrate comprising a light blocking pattern on the pixel electrode.
The method of claim 1,
The light blocking pattern is a thin film transistor array substrate having a structure covering all the active layer.
The method of claim 1,
The pixel electrode covers all of the active layer and is formed to a region outside the active layer.
The method of claim 1,
The light shielding pattern is a thin film transistor array substrate made of any one or an alloy thereof selected from the group consisting of aluminum (Al), neodymium (Nd), molybdenum (Mo), chromium (Cr) and titanium (Ti).
The method of claim 1,
A gate pad and a data pad spaced apart from the gate electrode;
And a pad electrode connected to the gate pad and the data pad, respectively.
The method of claim 1,
The thin film transistor array substrate is used as a substrate of a liquid crystal display device or an organic light emitting display device.
Forming a gate electrode on the substrate;
Forming a gate insulating film on the gate electrode;
Forming an active layer on the gate insulating film;
Forming an etch stopper on the active layer;
Forming a source electrode and a drain electrode on the active layer and the etch stopper;
Forming a passivation film on the substrate including the source electrode and the drain electrode;
Forming a transparent conductive film and a light shielding film on the passivation film; And
And forming a pixel electrode and a light shielding pattern by patterning the transparent conductive layer and the light shielding layer using a diffraction exposure mask.
The method of claim 7, wherein
And forming a gate pad simultaneously with forming the gate electrode, and forming a data pad simultaneously with forming the source electrode and the drain electrode.
The method of claim 7, wherein
The patterning of the transparent conductive film and the light shielding film using a diffraction exposure mask may include:
Arranging a diffraction exposure mask on the transparent conductive film and the light shielding film;
After applying the photoresist on the light shielding layer, forming a first photoresist pattern and a second photoresist pattern having a thickness step using the diffraction exposure mask;
Etching the transparent conductive film and the light shielding film to form a transparent conductive film pattern and a light shielding film pattern;
Ashing the first photoresist pattern and the second photoresist pattern to reduce the thickness of the first photoresist pattern and to remove the second photoresist pattern;
Etching the exposed light shielding pattern by removing the second photoresist pattern to form a pixel electrode and a pad electrode; And
And removing the first photoresist pattern to form a light shielding pattern.

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