KR20120030873A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A semiconductor device and a manufacturing method thereof are provided to stably implement a process by preventing a bowing defect on the upper side of an active area in an etch back process of a gate electrode material. CONSTITUTION: A device isolation area(220) is formed on a semiconductor substrate to define an active area. A first gate area is formed by etching the device isolation area and the active area. A capping layer is formed between the first gate area and the semiconductor substrate. A second gate area(300) is formed by etching the capping layer and the semiconductor substrate. A gate electrode material is formed on the second gate area.

Description

Semiconductor device and method for manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly integrated semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a buried word line structure which operates stably in a highly integrated semiconductor memory device and a method of manufacturing the same.

The semiconductor memory device includes a plurality of unit cells composed of a capacitor and a transistor, and a double capacitor is used to temporarily store data, and a transistor is used to control signals (word lines) by using a property of a semiconductor whose electrical conductivity varies depending on the environment. Correspondingly used to transfer data between the bit line and the capacitor. A transistor is composed of three regions: a gate, a source, and a drain. Charge occurs between a source and a drain in accordance with a control signal input to the gate. The transfer of charge between the source and drain occurs through the channel region.

When conventional transistors are made in a semiconductor substrate, a gate is formed on the semiconductor substrate and doped with impurities on both sides of the gate to form a source and a drain. As the data storage capacity of the semiconductor memory device increases and the degree of integration increases, the size of each unit cell is required to be made smaller and smaller. That is, the design rules of the capacitors and transistors included in the unit cell have been reduced. As a result, the channel length of the cell transistors has gradually decreased, resulting in short channel effects and drain induced barrier lower (DIBL). The reliability of the operation was lowered. Phenomena that occur as the channel length decreases can be overcome by maintaining the threshold voltage so that the cell transistor can perform normal operation. Typically, the shorter the channel of the transistor, the higher the doping concentration of impurities in the region where the channel is formed.

However, as the design rule decreases to less than 100 nm, the increase in doping concentration in the channel region further increases the electric field at the storage node (SN) junction, thereby degrading the refresh characteristics of the semiconductor memory device. Cause. To overcome this problem, a cell transistor having a three-dimensional channel structure having a long channel length in the vertical direction is used to maintain the channel length of the cell transistor even if the design rule is reduced. That is, even if the channel width in the horizontal direction is short, the doping concentration can be reduced by securing the channel length in the vertical direction, thereby preventing the refresh characteristics from deteriorating.

In addition, as the degree of integration of the semiconductor device increases, the distance between the word line and the bit line connected to the cell transistor is closer. As the parasitic capacitance increases, the operating margin of the sense amplifier, which amplifies the data transmitted through the bit line, is deteriorated, which adversely affects the operation reliability of the semiconductor device. In order to overcome this problem, a buried word line structure has been proposed in which word lines are formed only in recesses, not on top of a semiconductor substrate, in order to reduce parasitic capacitance between bit lines and word lines. The buried word line structure is formed with a bit line formed on a semiconductor substrate on which a source / drain is formed by forming a conductive material in a recess formed in the semiconductor substrate and covering the upper portion of the conductive material with an insulating film so that the word line is buried in the semiconductor substrate. Electrical isolation can be clarified.

1A to 1C are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to the prior art.

Referring to FIG. 1A, an isolation region 120 defining an active region 110 is formed in a semiconductor substrate 100. In this case, the active region 110 is formed in a line type. The isolation region 120 may be formed by a shallow trench isolation (STI) method. First, a pad insulating film (not shown) is deposited on the semiconductor substrate 100. Thereafter, a photoresist film (not shown) is deposited on the pad insulating film and an exposure process is performed using a mask defining the active region 110. Next, the liner oxide layer 130, the liner nitride layer 140, and a spin on dielectric (SOD) material 150 are embedded in a trench (not shown) formed by etching the exposed pad insulating layer and the semiconductor substrate 100. The device isolation region 120 is completed by chemical mechanical polishing until the exposed portion.

Next, a hard mask layer 160 is deposited on the active region 110 and the device isolation region 120. In this case, the hard mask layer 160 is formed of a nitride film (Nitride). After forming a photoresist film (not shown) on the hard mask layer 160, the hard mask layer 160 is patterned by performing an exposure process using a mask defining a buried gate. Thereafter, the active region 110 and the device isolation region 120 are etched using the patterned hard mask layer 160 as an etch mask to form the gate region 170. In this case, an etching process for forming the gate region 170 uses an anisotropic etching process.

Referring to FIG. 1B, a gate region (eg, due to a difference in etching selectivity of an oxide such as a hard mask layer 160 and an SOD material 150 during a cleaning process for interfacial treatment of the gate region 170) may be formed. Bowing defects, such as 'A' on the upper portion of 170 occurs. Due to the defect of the bowing 180, the etching degree of the gate region 170 in the active region 110 and the gate region 170 in the device isolation region 120 are non-uniform, resulting in deterioration of characteristics.

Referring to FIG. 1C, an oxidation process is performed on the gate region 170, the gate electrode layer 190 is buried, and the gate electrode layer 190 is etched back. In this case, after the gate electrode layer 190 is buried in the gate region 170, the etching degree of the gate electrode layer 190 during etching is non-uniform, such as 'B' and 'C' (see FIG. 2). There is a problem in that a short defect occurs between the gate electrode layer 190 and the gate electrode layer 190.

In order to solve the above-mentioned problems, the present invention uses the buried gate predetermined mask to pattern the active region and the device isolation film, and then expands the insulating film of the device isolation film by a cleaning process and applies a capping film to the patterned area. After the filling, the buried gate mask is etched using the buried gate mask to form the buried gate region. Thereafter, the insulating layer exposed to the lower portion of the buried gate region is extended to the cleaning process, and then the gate electrode material is deposited and the gate electrode material is etched back to etch back the gate electrode material. The present invention provides a semiconductor device and a method of manufacturing the same, which can prevent a bowing defect and proceed a stable process, and prevent short failing between the landing plug and the buried gate in a subsequent process.

The present invention provides a method for forming a semiconductor device, the method comprising: forming a device isolation region defining an active region in a semiconductor substrate, forming a first gate region by etching the device isolation region and the active region, on the first gate region and the semiconductor substrate Forming a capping layer, etching the capping layer and the semiconductor substrate to form a second gate region, and depositing a gate electrode material on the second gate region; It provides a method for producing.

Preferably, the forming of the first and second gate regions is performed by anisotropically etching the semiconductor substrate.

The forming of the first gate region may include etching the active region and the device isolation region by using a buried gate predetermined region mask as an etching mask.

Preferably, the etching depth of the active region and the device isolation region by using the buried gate predetermined region mask as an etch mask is etched to be 400 Å to 800 Å.

Preferably, the method further includes forming a hard mask layer on the semiconductor substrate between forming an isolation region defining an active region in the semiconductor substrate and forming the first gate region. It is done.

Preferably, the hard mask layer is characterized in that it comprises a nitride (Nitride).

Preferably, the method further comprises: cleaning the first gate region between the forming of the first gate region and the forming of the capping layer to extend a lower portion of the first gate region. It is done.

Preferably, after the forming of the second gate region, the method further comprises cleaning the second gate region to extend a lower portion of the second gate region.

Preferably, after the step of expanding the lower portion of the second gate region, further comprising the step of oxidizing the second gate region (Oxidation).

Preferably, the capping film is characterized in that it comprises a nitride film (Nitride).

Preferably, the gate electrode material comprises polysilicon, aluminum (Al), tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN) or titanium nitride (TiN) And it is characterized in that it comprises a laminated structure of tungsten (W).

The forming of the second gate region may include etching the capping layer, the active region, and the device isolation region by using the buried gate mask as an etch mask.

Preferably, after the depositing the gate electrode material, the method further comprises etching the gate electrode material.

In addition, the present invention features a buried gate including a buried gate region provided in a semiconductor substrate, a capping layer provided on an upper side of the semiconductor substrate and sidewalls of the buried gate region, and a gate electrode material formed in the buried gate region. A semiconductor device is provided.

Preferably, the capping film is characterized in that it comprises a nitride film (Nitride).

Preferably, the gate electrode material comprises polysilicon, aluminum (Al), tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN) or titanium nitride (TiN) And it is characterized in that it comprises a laminated structure of tungsten (W).

Preferably, the gate electrode material is provided in the buried gate region, and positioned below the capping layer provided on the sidewall of the buried gate region.

According to the present invention, after the active region and the device isolation layer are patterned using the buried gate predetermined mask, the insulating layer of the device isolation layer is expanded by a cleaning process, and a capping layer is embedded in the patterned region, and then the buried gate mask is used. The capping layer, the active region and the device isolation layer are etched to form a buried gate region. Thereafter, the insulating layer exposed to the lower portion of the buried gate region is extended to the cleaning process, and then the gate electrode material is deposited and the gate electrode material is etched back to etch back the gate electrode material. A stable bowing process can be performed to prevent bowing defects, and a short fail between the landing plug and the buried gate can be prevented in a subsequent step.

1A to 1C are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to the prior art.
Figure 2 is a photograph showing a problem of a semiconductor device and a manufacturing method according to the prior art.
3A to 3G are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3G are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to the present invention.

Referring to FIG. 3A, an isolation region 220 defining an active region 210 is formed in the semiconductor substrate 200. In this case, the active region 210 may be formed in a line or island type. The device isolation region 220 may be formed by a shallow trench isolation (STI) method. First, a pad insulating film (not shown) is deposited on the semiconductor substrate 200. Thereafter, a photoresist film (not shown) is deposited on the pad insulating film and an exposure process is performed using a mask defining the active region 210. Next, the liner oxide film 230, the liner nitride film 240, and the SOD (Spin On Dielectric) material 250 are buried in a trench (not shown) formed by etching the exposed pad insulating film and the semiconductor substrate 200. The device isolation region 220 is completed by planarization (Chemical Mechanical Polishing) until the exposed.

Next, a hard mask layer 260 is deposited on the active region 210 and the device isolation region 220. In this case, the hard mask layer 260 is preferably formed of a nitride film (Nitride).

Referring to FIG. 3B, after forming a photoresist film (not shown) on the hard mask layer 260, a photoresist pattern (not shown) is formed by an exposure and development process using a buried gate predetermined mask. The first gate region 270 is formed by etching the SOD material 250 of the hard mask layer 260, the active region 210, and the device isolation region 220 using the photoresist pattern as an etching mask. Here, the depth of the first gate region 270 formed by etching the hard mask layer 260, the device isolation region 220, and the active region 210 is 400 Å to 800 깊이 from the hard mask layer 260. It is preferably formed by etching, and most preferably, the hard mask layer 260 is formed to a depth of 600 kPa to 650 kPa.

Referring to FIG. 3C, a cleaning process is performed on the first gate region 270 to extend the lower portion 280 of the first gate region 270. In this case, since the material components of the active region 210 and the device isolation region 220 are different, selective etching ratios of different materials are used, but silicon (Si) of the active region 210 is hardly etched, and the device isolation region is used. Preferably, the SOD material 150 of 220 is sufficiently etched.

Referring to FIG. 3D, a capping layer 290 is formed on the first gate region 270, the extended lower portion 280 of the first gate region 270, and the hard mask layer 260. In this case, the capping film 290 preferably includes a nitride film.

Referring to FIG. 3E, after forming a photoresist film (not shown) on the capping layer 290, an exposure and development process is performed using a mask defining a buried gate to form a photoresist pattern (not shown). do. The second gate region 300 is formed by etching the capping layer 290, the device isolation region 220, and the active region 210 using the photoresist pattern as an etching mask. In this case, it is preferable to use an anisotropic etching process for forming the second gate region 300.

Referring to FIG. 3F, a cleaning process is performed to interface the second gate region 300 to form an extended second gate region 310. At this time, during the cleaning process, only the SOD material 250 under the second gate region 310 is etched. In this cleaning process, the lower portion of the second gate region 300, rather than the upper portion, may be etched to prevent bowing defects occurring adjacent to the active region 210. In addition, due to the capping layer 290 deposited on the sidewall of the second gate region 300, the etching degree of the gate region 300 of the device isolation region 220 may be uniformly controlled, and the occurrence of characteristic degradation may be prevented. Can be.

Referring to FIG. 3G, an oxidation process is performed in the gate region 300, the gate electrode layer 320 is embedded in the gate region 300, and the gate electrode layer 320 is etched back. At this time, after the gate electrode layer 320 is buried in the gate region 300, the etching degree of the gate electrode layer 320 is etched uniformly to prevent short defects between the landing plug (not shown) and the gate electrode layer 190. have.

As described above, according to the present invention, after the active region and the device isolation layer are patterned using the buried gate predetermined mask, the insulating film of the device isolation layer is extended to a cleaning process, and the capping layer is embedded in the patterned area. The buried gate region is formed by etching the capping layer, the active region and the device isolation layer using the gate mask. Thereafter, the insulating layer exposed to the lower portion of the buried gate region is extended to the cleaning process, and then the gate electrode material is deposited and the gate electrode material is etched back to etch back the gate electrode material. A stable bowing process can be performed to prevent bowing defects, and a short fail between the landing plug and the buried gate can be prevented in a subsequent step.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

Claims (17)

Forming an isolation region defining an active region in the semiconductor substrate;
Etching the device isolation region and the active region to form a first gate region;
Forming a capping layer on the first gate region and the semiconductor substrate;
Etching the capping layer and the semiconductor substrate to form a second gate region; And
Forming a gate electrode material in the second gate region
And forming a second insulating film on the semiconductor substrate. The method of claim 1,
The forming of the first and second gate regions may be performed by anisotropically etching the semiconductor substrate. The method of claim 1,
Forming the first gate region
And etching the active region and the device isolation region to a predetermined depth by using a buried gate predetermined region mask as an etch mask. The method of claim 3, wherein
And etching the active region and the device isolation region by using the buried gate planar region mask as an etch mask. The method of claim 1,
And forming a hard mask layer over the active region and the device isolation region after forming the device isolation region defining an active region on the semiconductor substrate. The method of claim 5, wherein
The hard mask layer includes a nitride film (Nitride) characterized in that the manufacturing method of the semiconductor device. The method of claim 1,
After the forming of the first gate region,
Cleaning the first gate area to extend a lower portion of the first gate area. The method of claim 1,
After forming the second gate region,
And cleaning the second gate area to extend a lower portion of the second gate area. The method of claim 8,
And after the lowering of the second gate region, oxidizing the second gate region. The method of claim 1,
The capping film manufacturing method of a semiconductor device characterized in that it comprises a nitride film (Nitride). The method of claim 1,
The gate electrode material includes polysilicon, aluminum (Al), tungsten (W), tungsten nitride (WN), titanium (Ti) or titanium nitride (TiN). The method of claim 1,
Forming the second gate region
And etching the capping layer, the active region, and the device isolation region by using the buried gate mask as an etch mask. The method of claim 1,
After depositing the gate electrode material,
And etching back the gate electrode material. A buried gate region provided in the semiconductor substrate;
A capping layer formed on the semiconductor substrate and on sidewalls of the buried gate region; And
A buried gate comprising a gate electrode material formed in the buried gate region
A semiconductor device characterized in that. The method of claim 14,
The capping layer is a semiconductor device, characterized in that it comprises a nitride (Nitride). The method of claim 14,
The gate electrode material comprises polysilicon, aluminum (Al), tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN). The method of claim 14,
And the gate electrode material is disposed in the buried gate region, and is located below the capping layer provided on the sidewall of the buried gate region.

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