KR20120000040A - Method for setting number of iterative decoding, apparatus and method for ldpc decoding - Google Patents

Abstract

PURPOSE: A method for setting the number of iterative decoding, an LDPC decoding apparatus, and a decoding method thereof are provided to omit test decoding and parity check calculation by determining the times of repetitive decoding which is below minimum repetitive decoding number. CONSTITUTION: A decoding unit(210) restores a valid code word from a received signal by repetitively decoding the received signal. A decoding process, which is repetitively operated, includes test decode and error check. A SNR(Signal to Noise Ratio) estimation unit(220) estimates the SNR of a received signal. The SNR estimating unit estimates the SNR of the received signal according to an arbitrary SNR estimating method which is publicly known. A repetitive decode number setting unit(230) sets a minimum repetitive decode number about the received signal based on a measured SNR. A storage unit(240) stores one or more minimum repetitive decode numbers and one or more SNRs.

Description

Method for setting an iterative decoding number, LDPC decoding apparatus and method therefor {Method for setting number of iterative decoding, Apparatus and Method for LDPC decoding}

Embodiments of the present invention relate to an iterative decoding number setting method, an LDPC decoding apparatus, and a method thereof, and more particularly, an iterative decoding number setting method for reducing the amount of computation and power consumption required for performing iterative decoding, and using the same. The present invention relates to an LDPC decoding apparatus and a method thereof.

4G wireless mobile communication systems require high data transfer rates and low error rates to provide various multimedia services to users. More specifically, the fourth generation wireless mobile communication requires a data transfer rate of up to 100 Mbps at high speed and up to 155 Mbps to 1 Gbps at low speed or stop. Therefore, in order to perform high quality and high reliability communication in a poor transmission environment, channel encoding / decoding techniques must be accompanied.

The channel encoding technique may be modified and used in various forms according to the characteristics of the channel. Basically, a technique of encoding / decoding a signal using an error correcting code is commonly used.

The error correction code is used to achieve reliable communication on an unreliable channel. A typical example is an encoding / decoding technique using a Low Density Parity Check (LDPC) code (hereinafter referred to as 'LDPC coding'). There is).

LDPC coding is a coding technique using a simple probabilistic decoding method and decodes a received signal through iterative decoding. In LDPC coding, most elements have a zero value, and a small number of elements other than those with a zero value have a non-zero value (eg, a value of 1). Defined by the Parity Check Matrix.

In the LDPC coding scheme, in each iterative decoding step, a tentative code is generated to generate a tentative code, and whether a test code generated through a parity check is a valid codeword. Check it. If the generated test code is not a valid codeword, decoding is repeatedly performed. If the generated test code is a valid codeword, decoding is stopped. At this time, as the number of decoding increases, the probability that the generated test code is a valid codeword increases.

Therefore, in the case of a received signal having a large number of repeated decoding operations, the probability that the test code generated in the initial decoding step is a valid codeword is low, and therefore, error checking in the initial decoding step may be unnecessary. Accordingly, a problem arises in that the amount of calculation increases during decoding, delaying decoding, and increasing power consumption.

In order to solve the problems of the prior art as described above, the present invention proposes an LDPC decoding apparatus and method that can reduce the amount of computation required and the amount of power consumed when decoding a received signal.

According to a preferred embodiment of the present invention to achieve the above object, a signal quality estimator for estimating the signal quality of the received signal encoded according to the LDPC encoding algorithm; An iterative decoding setter which adaptively sets a minimum iterative decoding number for the received signal in inverse proportion to the estimated signal quality; And a check node operation that is decryption performed on check nodes, a variable node operation that is decryption performed on variable nodes, and a decryption test decryption performed on test code. And a decoder that repeatedly decodes the received signal using a parity check, wherein the decoder performs the check node operation and the variable node operation when the number of times of the iterative decoding is less than or equal to the minimum iterative decoding number. An LDPC decoding apparatus is provided which does not perform the test decoding and the parity check operation.

According to another embodiment of the present invention, an iterative decoding number of an LDPC decoding apparatus repeatedly decoding a received signal encoded according to an LDPC encoding algorithm by using a check node operation, a variable node operation, a test decoding, and a parity check. A setting method, comprising: estimating a signal quality of the received signal; And adaptively setting a minimum repetition number for the received signal in inverse proportion to the estimated signal quality, wherein the minimum repetition number determines whether the LDPC decoding apparatus performs the test decoding and the parity check. As the iterative decoding number used for determining, the LDPC decoding apparatus performs the check node operation and the variable node operation when the number of times of the iterative decoding is less than or equal to the minimum iterative decoding number, and performs the test decoding and the parity check. A method of setting an iterative decoding number for LDPC decoding, which does not perform an operation, is provided.

Further, according to another embodiment of the present invention, an iterative decoding number setting unit for adaptively setting the minimum iterative decoding number for a received signal encoded according to the LDPC encoding algorithm in inverse proportion to the signal quality of the received signal; And a check node operation that is decryption performed on check nodes, a variable node operation that is decryption performed on variable nodes, and a decryption test decryption performed on test code. And a decoder that repeatedly decodes the received signal using a parity check, wherein the decoder performs the check node operation and the variable node operation when the number of times of the iterative decoding is less than or equal to the minimum iterative decoding number. An LDPC decoding apparatus is provided which does not perform the test decoding and the parity check operation.

According to the present invention, it is possible to reduce the amount of computation required and the amount of power consumed when iteratively decoding a received signal.

1 is a diagram for explaining a concept of LDPC coding.
2 is a block diagram showing a detailed configuration of an iterative decoding apparatus according to an embodiment of the present invention.
3 is a flowchart illustrating a method for setting an iterative decoding number and an iterative decoding method according to an embodiment of the present invention.
4 is a diagram illustrating an algorithm of an LDPC decoding method which is an example of an iterative decoding method according to an embodiment of the present invention.
5 is a diagram illustrating an algorithm of an LDPC decoding method as an example of an iterative decoding method according to an embodiment of the present invention.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Like reference numerals are used for like elements in describing each drawing.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Before describing the iterative decoding apparatus and its method according to the present invention, the LDPC coding technique, which is an example of an iterative coding technique, will be briefly described. It will be described in detail. In the following description of the present invention, the same reference numerals will be used for the same means regardless of the reference numerals in order to facilitate the overall understanding.

1 is a diagram for explaining a concept of LDPC coding.

1 illustrates an example of a parity check matrix and a factor graph corresponding to the parity check matrix.

One LDPC code, which is a block code, is defined by a parity check matrix. The LDPC code uses a parity check matrix including a small number of '1' to reduce the complexity of decoding. In the LDPC code, decoding may be performed using a sum-product algorithm, a min-sum algorithm, or the like, which is a soft decision decoding algorithm.

Here, it is assumed that the (source) data is k bits and the data encoded according to the LDPC code is n bits. At this time, n bits of encoded data include k bits of data and (n-k) bits of parity. In this case, when it is assumed that k bits of data and (nk) bits of parity correspond to variable nodes and check bits correspond to check nodes, the parity check matrix is variable. It may be defined based on the connection relationship between nodes and check nodes.

The LDPC encoding apparatus may generate encoded data with a constraint of Equation 1 below.

Where H is a parity check matrix of dimension mxn, m is the number of check nodes, X is n bits of encoded data (codeword), u is k bits of (source) data, and G is nxk dimension Means a generating matrix, respectively.

The number of 1s included in each column of the parity check matrix is called a variable node order. In addition, the number of 1s included in each row of the parity check matrix is called a check node order. If the variable node orders for each column are all the same and the check node orders for each row are all the same, then the LDPC code is a regular LDPC code and the variable node orders for each column are different, or checks for each row If the node orders are different, the LDPC code is a nonuniform LDPC code.

Referring to FIG. 1, the parity check matrix H is connected to the variable nodes v ₁ , v ₂ ,..., V ₁₀ and the check nodes c ₁ , c ₂ , c ₃ ,..., C ₅ . Defined based on the relationship. The variable nodes v ₁ , v ₂ ,..., V ₁₀ correspond to coded data, and the coded data includes data bits and parity bits. In addition, the check nodes correspond to check bits. The dimension of the parity check matrix H is 5 × 10 depending on the number of variable nodes and the number of check nodes.

On the factor graph showing the connection relationship between the variable nodes and the check nodes, since v ₁ is connected to c ₁ and c ₃ , the element 1 row 1 and element 3 3 of the parity check matrix H '1' and all remaining elements in column 1 are determined to be zero. Similarly, since v ₂ is connected to c ₁ and c ₂ , it can be seen that the two-row, one-row and two-row elements are '1' and the remaining elements of the second column are all '0'. In the manner described above, all elements of the parity check matrix are determined as either '1' or '0'.

In addition, the variable node order is equal to the number of lines connected to each variable node, and the check node order is equal to the number of lines connected to each check node. That is, referring to the factor graph of FIG. 1, since two lines are connected to each of the variable nodes, the variable node order is '2'. Also, the check node order is '4'.

When decoding data encoded according to the above encoding method, each of the variable nodes and the check nodes transmit their decoding results to other connected nodes or receive decoding results of other nodes. That is, when one node receives a decoding result of another node from another node, the one node performs decoding using the decoding result of the other node and transmits its decoding result to another node connected to the node. .

In this case, a decoding operation performed on the check nodes is called a check node operation, and a decoding operation performed on the variable nodes is called a variable node operation.

A test code is generated through a check node operation and a variable node operation, and the generated test code is checked whether it is a valid codeword through parity check.

If the generated test code is a valid codeword, the decoding operation is terminated. If the generated test code is not a valid codeword, the decoding operation is repeatedly performed.

2 is a block diagram showing a detailed configuration of an iterative decoding apparatus 200 according to an embodiment of the present invention.

The iterative decoding apparatus 200 according to an embodiment of the present invention may include a decoder 210, an SNR estimator 220, and an iterative decoder set unit 230. Hereinafter, the function of each component will be described in detail.

The decoder 210 repeatedly decodes the received signal to recover valid codewords from the received signal.

At this time, each decoding operation repeatedly performed includes tentative decoding and error check.

Test decoding refers to an operation of decoding a received signal or a tentative code decoded in a previous step, and error checking refers to an operation of checking whether a decoded test code is a valid codeword.

For example, when the iterative decoding apparatus 200 is an LDPC decoding apparatus that decodes a received signal by using an LDPC decoding technique, the test decoding includes a check node operation and a variable node operation, and the error check includes a parity check. .

According to an embodiment of the present invention, the decoder 210 may selectively perform error checking based on the minimum repetitive decoding number. This will be described in more detail below.

The SNR estimator 220 estimates a signal-to-noise ratio (SNR) of the received signal.

In this case, the SNR estimator 220 may estimate the SNR of the received signal according to a known SNR estimation method.

The iterative decoding number setting unit 230 sets a minimum iterative decoding number for the received signal based on the measured SNR.

In general, the number of iterative decodings performed to recover a valid codeword from a received signal, that is, the number of repeated decodings, has a different value depending on the SNR of the received signal.

Hereinafter, referring to Table 1, the correlation between the number of iterative decoding and the SNR of the received signal when the decoder 210 decodes the received signal based on the LDPC decoding scheme will be described.

S NR
( dB ) Number of Iteration Decoding S NR
( dB ) Number of Iteration Decoding Min Max Avg Min Max Avg -One 50 50 50 6 2 4 2.16 -0.5 50 50 50 6.5 One 3 2.02 0 50 50 50 7 One 3 1.86 0.5 50 50 50 7.5 One 3 1.48 One 42 50 49.88 8 One 2 1.16 1.5 10 50 21.51 8.5 One 2 1.04 2 6 19 10.94 9 One 2 1.01 2.5 4 11 7.75. 9.5 One 2 One 3 4 9 6.03 10 One 2 One 3.5 4 7 4.91 10.5 One 2 One 4 3 6 4.1 11 One One One 4.5 2 5 3.45 11.5 One One One 5 2 4 3.02 12 One One One 5.5 2 4 2.6

In Table 1, a received signal encoded using an LDPC code having a code rate of 1/2 for 1,000,000 symbols and an information block having a length and a dimension of 4608 and 9216, respectively. In the case of performing iterative decoding on, the maximum value Max, minimum value Min, and average value avg of the repeated decoding number according to the SNR of the received signal are displayed.

Referring to Table 1, it can be seen that as the SNR of the received signal increases, the maximum number, minimum number, and average number of repeated decoding operations decrease.

That is, when the SNR of the received signal is large, the decoder 210 may repeat only a small number of decryptions, but if the SNR of the received signal is small, the decoder 210 must repeatedly perform a large number of decryptions. .

As an example, referring to Table 1, when the SNR of the received signal has a value of 2 dB, the decoder 210 should repeatedly perform a minimum of six times and a maximum of 19 times of decoding.

Therefore, the test code reconstructed through the trial decoding in the number of decryption steps less than the minimum number of iterative decoding (hereinafter referred to as 'initial stage' for convenience) is unlikely to satisfy the error check (that is, the test code). Is unlikely to be a valid codeword), so error checking performed at an early stage is redundant.

Therefore, the decoder 210 selectively performs an error check based on the minimum iterative decoding number set by the iterative decoding number setting unit 230. In this case, referring to Table 1, the set minimum repetition number may be inversely proportional to the SNR of the received signal.

According to an embodiment of the present invention, when the number of repetitions of the test decoding is less than or equal to the minimum repetition number set in the iterative decoding number setting unit 230, the decoder 210 does not perform error checking (that is, only test decoding is performed. And, if the number of repetitions of the test decoding exceeds the minimum number of repeated decoding, both the test decoding and the error check may be performed.

For example, when the SNR of the received signal has a value of 2 dB, since the minimum number of decoding times for restoring a valid codeword is '6', the decoder 210 performs only trial decoding in the first to fifth decoding steps. After the sixth decoding step, both test decoding and error checking can be performed.

Accordingly, since unnecessary error checking performed in the initial stage is omitted, the amount of decoding operations is reduced, the time required is shortened, and power consumption is reduced. In particular, when the SNR of the received signal is low, since the minimum value Min of the repetitive decoding number is large, the efficiency of time reduction and power consumption reduction is increased.

Hereinafter, referring to FIG. 3, the power consumption of the iterative decoding apparatus 200 and the general iterative decoding apparatus according to an embodiment of the present invention will be described.

3 is a diagram illustrating a correlation between an SNR of a received signal and power consumed when decoding a received signal using the iterative decoding apparatus 200 according to an embodiment of the present invention.

3 illustrates the correlation between the SNR of the received signal and the power consumption when the received signal is decoded using the LDPC decoding technique.

For example, when the SNR of the received signal is 2.5dB, when the parity check is selectively performed (With Adaptive Parity Check) as in the present invention, power of 557mW is consumed, but the parity check is always performed (No Adaptive Parity). Check consumes 766 mW of power. This saves 208mW of power.

In addition, referring to FIG. 3, when the SNR of the received signal is 2 dB to 6.5 dB, a difference in power consumption may occur. However, when the SNR of the received signal is greater than 6.5 dB, there is no difference in power consumption. This is due to the fact that when the SNR of the received signal is large, a valid codeword can be recovered only by a small number of iterative decoding.

Referring to FIG. 2 again, an iterative decoding apparatus 200 according to an embodiment of the present invention will be described in detail.

According to an embodiment of the present invention, the iterative decoding apparatus 200 may further include a storage unit 240.

The storage unit 240 stores at least one SNR and at least one minimum repetitive decoding number in correspondence with each other.

In this case, the iterative decoding number setting unit 230 reads from the storage unit 240 a minimum iterative decoding number corresponding to (ie, most similar to) the SNR of the received signal measured by the SNR measuring unit 220. This can be set as the minimum repetition number of the received signal.

In this case, the minimum repetitive decoding number corresponding to the SNR may be determined experimentally.

As an example, when iterative decoding is performed on a received signal encoded using an LDPC code having an information block having a code rate of 1/2 and a length and a dimension of 4608 and 9216 for 1,000,000 symbols, respectively, The unit 240 may store a look up table (LUT) as shown in Table 2 below. In this case, the iterative decoding number setting unit 230 may set a minimum iterative decoding number for the received signal based on the lookup table.

SNR ( dB ) 0.5 or less One 1.5 2 2.5 3 3.5 Minimum repetition Decoders 49 41 9 5 3 3 3 SNR ( dB ) 4 4.5 5 5.5 6 6.5 and above Minimum repetition Decoders 2 One One One One 0

In the above, the case where the iterative decoding apparatus decodes the received signal by using the LDPC decoding technique has been described as an example, but for convenience of description, the present invention repeatedly performs decoding through a test decoding process and an error checking process. It will be apparent to those skilled in the art that the present invention can be applied to a decoding apparatus.

Hereinafter, referring to FIG. 4, an iterative decoding method setting method and an iterative decoding method according to an embodiment of the present invention will be described in detail.

4 is a flowchart illustrating a iterative decoding method setting method and an iterative decoding method according to an embodiment of the present invention.

As shown in FIG. 4, the iterative decoding method according to an embodiment of the present invention includes steps S410 to S430, wherein steps S410 and S420 are performed according to the present invention. A method of setting a repetitive decoding number according to an embodiment may be configured.

First, in step S410, the SNR of the received signal is estimated.

Next, in step S420, a minimum iterative decoding number is set based on the estimated SNR.

Finally, in step S430, the received signal is repeatedly decoded by using test decoding and error checking. In this case, in operation S430, error checking may be selectively performed based on the minimum repetitive decoding number.

For example, when the number of repetitions of the test decoding is less than or equal to the minimum repetition number, in step S430, error checking is not performed, and when the number of repetitions of the test decoding exceeds the minimum repetition number, in step S430, the test decoding is performed. And error checking can be performed.

In this case, according to an embodiment of the present invention, the minimum repetitive decoding number may be inversely proportional to the SNR of the received signal.

Further, according to an embodiment of the present invention, in step S420, the minimum repetitive decoding number may be set using a storage unit that stores the SNR and the minimum repetitive decoding number in correspondence. In this case, in step S430, the minimum repetition number may be set by reading the minimum repetition number corresponding to the SNR estimated in step S410 from the storage unit.

In addition, as mentioned above, the iterative decoding method according to an embodiment of the present invention may be applied to an LDPC decoding method based on an LDPC decoding technique.

The embodiments of the iterative decoding method according to the present invention have been described so far, and the configuration of the iterative decoding apparatus 200 described with reference to FIG. 2 is also applicable to the present embodiment. Therefore, more detailed description will be omitted.

5 is a diagram illustrating an algorithm of an LDPC decoding method which is an example of an iterative decoding method according to another embodiment of the present invention.

수신신호에 포함된 심볼 데이터,

은 패리티 검사 행렬의 행렬 원소,

은 배리어블 노드의 데이터 행렬 원소,

는 최대 반복 복호수,

은 최소 반복 복호수,

은 체크 노드의 데이터 행렬 원소,

은 시험 코드,

은

를 생성하기 위한 임시값을 각각 의미한다. In the LDPC decoding algorithm shown in FIG. 5, line 3 to line 4 are check node calculation steps, line 5 to line 6 are variable node calculation steps, line 8 to line 9 are test decoding steps, and line 10 to line 11 are Each parity check step. In addition, i is a repetitive decoder,

Symbol data included in the received signal,

Is the matrix element of the parity check matrix,

Is the data matrix element of the variable node,

Is the maximum iteration decoder,

Is the minimum iteration decode,

Is the data matrix element of the check node,

Silver test code,

silver

Each temporary value to create a.

The LDPC decoding algorithm shown in FIG. 5 is the same as the conventional LDPC decoding algorithm except that line 7 and line 12 are added.

)보다 큰지를 판단한다. 앞서 언급한 바와 같이 최소 반복 복호수(

)는 수신신호의 수신 품질인 SNR 값에 따라 결정된다. Lines 7 and 12 are added to selectively perform trial decoding and parity checking. In line 7, the number of current decoding steps (i.e., i) is the minimum iterative decoding number (

Determine if greater than As mentioned earlier, the minimum iterative decoding number (

) Is determined according to the SNR value, which is the reception quality of the received signal.

If the value of i is smaller than the minimum iterative decoding number, line 8 to line 11 is not performed (that is, no trial decoding and parity check is performed), and if the value of i is larger than the minimum iterative decoding number, line 11 is all performed (ie, both test decoding and parity check are performed). Accordingly, no parity check is performed in the decoding step below the minimum iterative decoding number.

In addition, embodiments of the present invention may be implemented in the form of program instructions that may be executed by various computer means to be recorded on a computer readable medium. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. Program instructions recorded on the media may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well-known and available to those having skill in the computer software arts. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tape, optical media such as CD-ROMs, DVDs, and magnetic disks, such as floppy disks. Examples of program instructions such as magneto-optical, ROM, RAM, flash memory, etc. may be executed by a computer using an interpreter as well as machine code such as produced by a compiler. Contains high-level language codes. The hardware device described above may be configured to operate as one or more software modules to perform the operations of one embodiment of the present invention, and vice versa.

As described above, the present invention has been described by specific embodiments such as specific components and the like. For those skilled in the art to which the present invention pertains, various modifications and variations are possible. Therefore, the spirit of the present invention should not be limited to the described embodiments, and all of the equivalents or equivalents of the claims as well as the claims to be described later will belong to the scope of the present invention. .

Claims (5)

A signal quality estimator for estimating a signal quality of a received signal encoded according to an LDPC encoding algorithm;
An iterative decoding setter which adaptively sets a minimum iterative decoding number for the received signal in inverse proportion to the estimated signal quality; And
A check node operation that is decryption performed on check nodes, a variable node operation that is decryption performed on variable nodes, a tentative decryption operation that is performed on test code, and It includes a decoder for repeatedly decoding the received signal using a parity check,
And the decoding unit performs the check node operation and the variable node operation when the number of times of the iterative decoding is less than or equal to the minimum iterative decoding number, and does not perform the test decoding and the parity check operation. . The method of claim 1,
The signal quality comprises an SNR,
The LDPC decoding apparatus further includes a storage unit for storing at least one SNR and at least one minimum repetitive decoding number in correspondence with each other.
The iterative decoding number setting unit reads the minimum iterative decoding number corresponding to the estimated SNR from the storage unit and sets the minimum iterative decoding number. In the method for setting the iterative decoding number of the LDPC decoding apparatus for repeatedly decoding the received signal encoded according to the LDPC encoding algorithm using a check node operation, a variable node operation, a test decoding and a parity check,
Estimating a signal quality of the received signal; And
Adaptively setting a minimum iterative decoding number for the received signal in inverse proportion to the estimated signal quality;
The minimum iterative decoding number is an iterative decoding number used by the LDPC decoding apparatus to determine whether to perform the trial decoding and the parity check, and the LDPC decoding apparatus is the number of times of the iterative decoding is less than or equal to the minimum iterative decoding number. And performing the check node operation and the variable node operation and not performing the test decoding and the parity check operation. An iterative decoding setter adapted to adaptively set a minimum iterative decoding number for a received signal encoded according to an LDPC encoding algorithm in inverse proportion to the signal quality of the received signal; And
A check node operation that is decryption performed on check nodes, a variable node operation that is decryption performed on variable nodes, a tentative decryption operation that is performed on test code, and Including a decoder for repeatedly decoding the received signal using a parity check,
And the decoding unit performs the check node operation and the variable node operation when the number of times of the iterative decoding is less than or equal to the minimum iterative decoding number, and does not perform the test decoding and the parity check operation. . The method of claim 4, wherein
The signal quality comprises an SNR,
The LDPC decoding apparatus further includes a storage unit for storing at least one SNR and at least one minimum repetitive decoding number in correspondence with each other.
The iterative decoding number setting unit reads the minimum iterative decoding number corresponding to the estimated SNR from the storage unit and sets the minimum iterative decoding number.

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