KR20110131710A - Output buffer - Google Patents

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KR20110131710A
KR20110131710A KR1020100051287A KR20100051287A KR20110131710A KR 20110131710 A KR20110131710 A KR 20110131710A KR 1020100051287 A KR1020100051287 A KR 1020100051287A KR 20100051287 A KR20100051287 A KR 20100051287A KR 20110131710 A KR20110131710 A KR 20110131710A
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South Korea
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pull
signal
output
node
driver
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KR1020100051287A
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Korean (ko)
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최창규
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주식회사 하이닉스반도체
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Priority to KR1020100051287A priority Critical patent/KR20110131710A/en
Publication of KR20110131710A publication Critical patent/KR20110131710A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

The output buffer includes: a pull-up pre-driver that receives the first internal data and generates a pull-up signal enabled in response to the pull-up code; A pull-down free driver which receives the first internal data and generates a pull-down signal enabled in response to a pull-down code; A pre-driver receiving the second internal data and generating a pull-down emphasizing signal enabled in response to the enable signal; A pull-up driver for pull-up driving output data output to an output pad in response to the pull-up signal; And a pull-down driver configured to pull-down the output data in response to the pull-down signal and the pull-down emphasis signal.

Figure P1020100051287

Description

Output buffer {OUTPUT BUFFER}

The present invention relates to an output buffer that performs a de-emphasis function.

In general, a termination resistor having a resistance value equal to a characteristic impedance of a transmission channel is connected to a receiving end or a transmitting end of the semiconductor device. The termination resistor matches the impedance of the receiving end or the transmitting end with the characteristic impedance of the transmitting channel to suppress reflection of signals transmitted through the transmitting channel. Conventional termination resistors are installed outside the semiconductor chip, but recently, an on-die termination circuit (ODT) in which a termination resistor is installed inside the semiconductor chip is mainly used. Since the ODT circuit includes a switching circuit for controlling the current flowing inside by the on / off operation, the power consumption is smaller than the termination resistor installed outside the chip. However, since the resistance value of the ODT circuit changes with the change of PVT (process, voltage, temperature), the resistance value of the ODT circuit must be adjusted before use.

Thus, using a ZQ resistor connected externally by a ZQ calibration circuit, counting the pull-up / pull-downcode signal for calibrating the pull-up / pull-down drive of the output buffer and generating the counting result The pull-up / pull-down code signal is used to correct the resistance value of the pull-up / pull-down driver of the output buffer.

On the other hand, the conventional output buffer emphasis and output the amplitude of the output data when the logic level transition of the output data, and if there is no transition of the logic level of the output data deemphasis (deemphasis) to reduce the amplitude of the highlighted output data The function is being used.

The present invention discloses an output buffer that provides a de-emphasis function while minimizing area and power consumption.

To this end, the present invention includes a pull-up pre-driver for receiving the first internal data and generating a pull-up signal enabled in response to the pull-up code; A pull-down free driver which receives the first internal data and generates a pull-down signal enabled in response to a pull-down code; A pre-driver receiving the second internal data and generating a pull-down emphasizing signal enabled in response to the enable signal; A pull-up driver for pull-up driving output data output to an output pad in response to the pull-up signal; And a pull-down driver configured to pull-down the output data in response to the pull-down signal and the pull-down emphasis signal.

In addition, the present invention includes a pull-up pre-driver for receiving the first internal data and generating a pull-up signal enabled in response to the pull-up code; A pre-driver receiving the second internal data to generate a pull-up emphasizing signal enabled in response to the enable signal; A pull-down free driver which receives the first internal data and generates a pull-down signal enabled in response to a pull-down code; A pull-up driver for pull-up driving output data output to an output pad in response to the pull-up signal and the pull-up emphasis signal; And a pull-down driver configured to pull-down the output data in response to the pull-down signal.

1 is a block diagram showing the configuration of an output buffer according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating in detail the configuration of a pull-up driver and a pull-down driver included in FIG. 1.
FIG. 3 is a timing diagram for describing an operation of the output buffer shown in FIG. 1.
4 is a block diagram showing the configuration of an output buffer according to another embodiment of the present invention.
FIG. 5 is a diagram illustrating in detail the configuration of a pull-up driver and a pull-down driver included in FIG. 4.
6 is a timing diagram for describing an operation of the output buffer shown in FIG. 3.

Hereinafter, the present invention will be described in more detail with reference to Examples. These embodiments are only for illustrating the present invention, and the scope of rights of the present invention is not limited by these embodiments.

1 is a block diagram showing the configuration of an output buffer according to an embodiment of the present invention.

As shown in FIG. 1, the output buffer of this embodiment includes a first multiplexer 10, a pull-up predriver 11, a pull-down predriver 12, a second multiplexer 13, and a predriver 14. ), A pull-up driver 15, a pull-down driver 16, and an output pad 17.

The first multiplexer 10 generates the first internal data IDATA (n) by multiplexing the first to Mth data DATA (n) <1: M> in response to the clock signal CLK.

The pull-up pre-driver 11 receives the first internal data IDATA (n) and receives the first to fourth pull-ups in response to the first to fourth pull-up code signals PU_CAL <1: 4>. Generate the up signals PU <1: 4>. More specifically, the pull-up pre-driver 11 may include the first to fourth pull-up signals PU <which are all disabled at a logic high level when the first internal data IDATA (n) has a logic low level. 1: 4>). Also, the pull-up predriver 11 may include the first to fourth pull-up signals PU <1: 4> when the first internal data IDATA (n) is at a logic high level. Only the signal selected according to the pull-up code signal PU_CAL <1: 4> is enabled at a logic low level and output. For example, when the first pull-up code signal PU_CAL <1> is at a logic high level, the first pull-up signal PU <1> is enabled at a logic low level, and the second pull-up code is enabled. When the signal PU_CAL <2> is at the logic high level, the second pull-up signal PU <2> is enabled at the logic low level, and the third pull-up code signal PU_CAL <3> is at the logic high level. Level, the third pull-up signal PU <3> is enabled at a logic low level, and when the fourth pull-up code signal PU_CAL <4> is at a logic high level, the fourth pull-up signal PU <3> is enabled. PU <4>) is enabled at a logic low level. The combination of the first to fourth pull-up code signals PU_CAL <1: 4> for selectively enabling the first to fourth pull-up signals PU <1: 4> to a logic low level is implemented. Various settings can be made according to the example. The first to fourth pull-up code signals PU_CAL <1: 4> are counted to calibrate the pull-up / pull-down driving of the output buffer 17 using a ZQ resistor in a conventional impedance calibration circuit. Signals.

The pull-down predriver 12 receives the first internal data IDATA (n) and receives the first to fourth pull- in response to the first to fourth pull-down code signals PD_CAL <1: 4>. A down signal PD <1: 4> is generated. More specifically, the pull-down predriver 12 may include the first to fourth pull-down signals PD <which are disabled at the logic low level when the first internal data IDATA (n) is at the logic high level. 1: 4>). In addition, the pull-down predriver 12 may include the first to fourth pull-down signals PD <1: 4> when the first internal data IDATA (n) is at a logic low level. Only signals selected according to the pull-down code signals PD_CAL <1: 4> are enabled at a logic high level and output. For example, when the first pull-down code signal PD_CAL <1> is at a logic high level, the first pull-down signal PD <1> is enabled at a logic high level, and the second pull-down code is enabled. When the signal PD_CAL <2> is at the logic high level, the second pull-down signal PD <2> is enabled at the logic high level, and the third pull-down code signal PD_CAL <3> is at the logic high level. Level, the third pull-down signal PD <3> is enabled at a logic high level, and when the fourth pull-down code signal PD_CAL <4> is at a logic high level, the fourth pull-down signal PD <3> is enabled. PD <4>) is enabled at a logic high level. The combination of the first to fourth pull-down code signals PD_CAL <1: 4> for selectively enabling the first to fourth pull-down signals PD <1: 4> to a logic low level is implemented. Various settings can be made according to the example. The first to fourth pull-down code signals PD_CAL <1: 4> are counted to calibrate the pull-up / pull-down driving of the output buffer 17 using a ZQ resistor in a conventional impedance calibration circuit. Signals.

The second multiplexer 13 multiplexes the first to M-th inversion data DATAB (n + 1) <1: M> in response to the clock signal CLK to generate the second internal data IDATAB (n + 1). Create Here, the first to M-th inversion data DATAB (n + 1) <1: M> are inverted after shifting the first to M-th data DATA (n) <1: M> by one bit. It is a signal. Therefore, the second internal data IDATAB (n + 1) is generated as a signal inverted after shifting the first internal data IDATA (n) by one bit. In the present embodiment, one bit is set to a half period of the clock signal CLK, which may be variously set according to the embodiment.

The predriver 14 receives the second internal data IDATAB (n + 1) to receive the first to second pull-downs in response to the first to second emulation enable signals DEEMP_EN <1: 2>. An emphasis signal PD_EMP <1: 2> is generated. More specifically, the predriver 14 may include the first to second pull-down emphasis signals PD_EMP which are all disabled at a logic low level when the second internal data IDATAB (n + 1) is at a logic high level. <1: 2>). In addition, the predriver 14 may include the first to second ones of the first to second pull-down emphasis signals PD_EMP <1: 2> when the second internal data IDATAB (n + 1) is at a logic low level. 2 Only the signal selected according to the emulation enable signal DEEMP_EN <1: 2> is enabled at a logic high level and output. For example, when the first emulation enable signal DEEMP_EN <1> is at the logic high level, the first pull-down emphasis signal PD_EMP <1> is enabled at the logic high level, and the second emphasis is performed. When the enable signal DEEMP_EN <2> is at the logic high level, the second pull-down emphasis signal PD_EMP <2> is enabled at the logic high level. Combination of the first to second emulation enable signals DEEMP_EN <1: 2> for selectively enabling the first to second pull-down emphasis signals PD_EMP <1: 2> to a logic high level. May be variously set according to an embodiment. Here, the first to second emulation enable signals DEEMP_EN <1: 2> may be externally applied for the de-emphasis function.

As shown in FIG. 2, the pull-up driver 15 is connected between the power supply voltage VDD and the node nd10 and turned on in response to the first pull-up signal PU <1>. P10, a resistor R10 connected between the node nd10 and the node nd100, and a power supply voltage VDD and the node nd11 connected to the second pull-up signal PU <2>. In response to the PMOS transistor P11 turned on, the resistor R11 connected between the node nd11 and the node nd100, and the power supply voltage VDD and the node nd12, are connected to the third pull-up signal ( PMOS transistor P12 which is turned on in response to PU <3>, resistor R12 connected between node nd12 and node nd100, and is connected between power supply voltage VDD and node nd13. And a resistor R13 connected between the node nd13 and the node nd100, and the PMOS transistor P13 turned on in response to the 4 pull-up signal PU <4>.

As shown in FIG. 2, the pull-down driver 16 is connected between the node Rd100 and the node nd14 and between the node nd14 and the ground voltage VSS. NMOS transistor N14 turned on in response to one pull-down signal PD <1>, resistor R15 connected between node nd100 and node nd15, node nd15, and ground voltage VSS. NMOS transistor N15 connected between the NMOS transistor N15 turned on in response to the second pull-down signal PD <2>, a resistor R16 connected between the node nd100 and the node nd16, and the node nd16. ) Is connected between the ground voltage VSS and the NMOS transistor N16 turned on in response to the third pull-down signal PD <3>, and the resistor R17 connected between the node nd100 and the node nd17. NMOS transistor N17 connected between node nd17 and ground voltage VSS and turned on in response to the fourth pull-down signal PD <4>, node nd100 and node nd18. Resistor R18 connected between node, node nd18 and ground The NMOS transistor N18 connected between the voltage VSS and turned on in response to the first pull-down emphasis signal PD_EMP <1>, and the resistor R19 connected between the node nd100 and the node nd19. And an NMOS transistor N19 connected between the node nd19 and the ground voltage VSS and turned on in response to the second pull-down emphasis signal PD_EMP <2>.

The de-emphasis function of the output buffer configured as described above will be described with reference to FIG. 3. However, the timing diagram shown in FIG. 3 includes the first to fourth pull-up code signals PU_CAL <1: 4>, the first to fourth pull-down code signals PD_CAL <1: 4>, and the first to fourth pull-up code signals PU_CAL <1: 4>. It is assumed that all of the second emulation enable signals DEEMP_EN <1: 2> are applied at a logic high level.

First, the first multiplexer 10 generates the first internal data IDATA (n) by multiplexing the input first to M-th data DATA (n) <1: M>. As shown in FIG. 2, the first internal data IDATA (n) has a logic low level from t10 to t12, a logic high level from t12 to t14, a logic low level from t14 to t15, and a logic high level from t15 to t16. , logic low level from t16 to t18, and logic high level from t18 to t19.

Next, the pull-up predriver 11 may include the first to fourth pull-up signals PU <1: all of which are disabled at a logic high level when the first internal data IDATA (n) has a logic low level. 4>). In addition, the pull-up pre-driver 11 may include the first to fourth pull-up signals PU <1: 4, all of which are enabled at a logic low level when the first internal data IDATA (n) has a logic high level. >), Since all of the first to fourth pull-up code signals PU_CAL <1: 4> are applied at a logic high level.

Next, the pull-down predriver 12 may include the first to fourth pull-down signals PD <1: all of which are disabled at a logic low level when the first internal data IDATA (n) has a logic high level. 4>). In addition, the pull-down predriver 12 may include the first to fourth pull-down signals PD <1: 4 that are all enabled at a logic high level when the first internal data IDATA (n) is at a logic low level. >), Since all of the first to fourth pull-down code signals PD_CAL <1: 4> are applied at a logic high level.

Next, the second multiplexer 13 multiplexes the first to M-th inversion data DATAB (n + 1) <1: M> in response to the clock signal CLK, thereby providing the second internal data IDATAB (n +). 1)).

Next, the predriver 14 may disable the first to second pull-down emphasis signals PD_EMP <1 which are all disabled at a logic low level when the second internal data IDATAB (n + 1) is at a logic high level. : 2>). In addition, the predriver 14 may include the first to second pull-down emphasis signals PD_EMP <1, which are all enabled at a logic high level when the second internal data IDATAB (n + 1) is at a logic low level. 2>), since all of the first to second emulation enable signals DEEMP_EN <1: 2> are applied at a logic high level.

Next, the pull-up driver 15 and the pull-down driver 16 drive the output data OUT output to the output pad 17.

Hereinafter, a driving operation of the output data OUT by the pull-up driver 15 and the pull-down driver 16 will be described in detail.

From t10 to t11, the first to fourth pull-down signals PD <1: 4> and the first to second pull-down emphasis signals PD_EMP <1: 2> are all enabled at a logic high level. As a result, all of the NMOS transistors N14 to N19 of the pull-down driver 16 are turned on. Therefore, the output data OUT is pulled down with a large amplitude.

Since there is no level transition of the first internal data IDATA (n) from t11 to t12, the first to second pull-down emphasis signals PD_EMP <1: 2> are disabled to a logic low level to pull-down The NMOS transistors N18 to N19 of the driver 16 are turned off. Therefore, the driving force to pull-down the output data OUT is reduced, so that the amplitude of the output data OUT is reduced.

From t12 to t13, the first to fourth pull-down signals PD <1: 4> and the first to second pull-down emphasis signals PD_EMP <1: 2> are all disabled at a logic low level. In the state, since all of the first to fourth pull-up signals PU <1: 4> are enabled at a logic low level, all of the PMOS transistors P10 to P13 of the pull-up driver 15 are turned on. Therefore, the output data OUT is pulled up with a large amplitude.

From t13 to t14, the first to second pull-down emphasis signals PD_EMP <1: 2> are enabled to a logic high level to turn on the NMOS transistors N18 to N19 of the pull-down driver 16. . Therefore, the driving force for pulling up the output data OUT is reduced, so that the amplitude of the output data OUT is reduced.

As described above, the output buffer according to the present embodiment drives the output data OUT with a large driving force when the level transition of the first internal data IDATA (n) occurs, and then the first internal data IDATA (n). If the level is kept constant, the driving force for driving the output data OUT is reduced to implement the de-emphasis function.

4 is a block diagram showing the configuration of an output buffer according to an embodiment of the present invention.

As shown in FIG. 4, the output buffer of the present embodiment includes a first multiplexer 20, a predriver 21, a second multiplexer 22, a pull-up predriver 23, and a pull-down predriver 24. ), A pull-up driver 25, a pull-down driver 26, and an output pad 27.

The first multiplexer 20 multiplexes the first to M-th inversion data DATAB (n + 1) <1: M> in response to the clock signal CLK to form the second internal data IDATAB (n + 1). Create Here, the first to M-th inversion data DATAB (n + 1) <1: M> are inverted after shifting the first to M-th data DATA (n) <1: M> by one bit. It is a signal. Therefore, the second internal data IDATAB (n + 1) is generated as a signal inverted after shifting the first internal data IDATA (n) by one bit. In the present embodiment, one bit is set to a half period of the clock signal CLK, which may be variously set according to the embodiment.

The predriver 21 receives the second internal data IDATAB (n + 1) and responds to the first to second emulation enable signals DEEMP_EN <1: 2> to output the first to second pull-up Ms. Generate the persist signal PU_EMP <1: 2>. More specifically, the predriver 21 may include the first to second pull-up emphasis signals PU_EMP <which are all disabled at the logic high level when the second internal data IDATAB (n + 1) is at the logic high level. 1: 2>). Also, the predriver 21 may include the first to second ones of the first to second pull-up emphasis signals PU_EMP <1: 2> when the second internal data IDATAB (n + 1) is at a logic low level. Only the signal selected according to the emulation enable signal DEEMP_EN <1: 2> is enabled at a logic low level and output. For example, when the first emulation enable signal DEEMP_EN <1> is at a logic high level, the first pull-up emphasis signal PU_EMP <1> is enabled at a logic low level, and the second emphasis is enabled. When the enable signal DEEMP_EN <2> is at the logic high level, the second pull-up emphasis signal PU_EMP <2> is enabled at the logic low level. The combination of the first to second emulation enable signals DEEMP_EN <1: 2> for selectively enabling the first to second pull-up emphasis signals PU_EMP <1: 2> to a logic low level is Various settings may be made according to the embodiment. Here, the first to second emulation enable signals DEEMP_EN <1: 2> may be externally applied for the de-emphasis function.

The second multiplexer 22 generates the first internal data IDATA (n) by multiplexing the first to Mth data DATA (n) <1: M> in response to the clock signal CLK.

The pull-up driver 23 receives the first internal data IDATA (n) and responds to the first to fourth pull-up code signals PU_CAL <1: 4>. Generate the up signals PU <1: 4>. More specifically, the pull-up predriver 23 may include the first to fourth pull-up signals PU <which are disabled at the logic high level when the first internal data IDATA (n) is at the logic low level. 1: 4>). In addition, the pull-up predriver 23 may include the first to fourth pull-up signals PU <1: 4> of the first to fourth pull-up signals PU <1: 4> when the first internal data IDATA (n) is at a logic high level. Only the signal selected according to the pull-up code signal PU_CAL <1: 4> is enabled at a logic low level and output. For example, when the first pull-up code signal PU_CAL <1> is at a logic high level, the first pull-up signal PU <1> is enabled at a logic low level, and the second pull-up code is enabled. When the signal PU_CAL <2> is at the logic high level, the second pull-up signal PU <2> is enabled at the logic low level, and the third pull-up code signal PU_CAL <3> is at the logic high level. Level, the third pull-up signal PU <3> is enabled at a logic low level, and when the fourth pull-up code signal PU_CAL <4> is at a logic high level, the fourth pull-up signal PU <3> is enabled. PU <4>) is enabled at a logic low level. The combination of the first to fourth pull-up code signals PU_CAL <1: 4> for selectively enabling the first to fourth pull-up signals PU <1: 4> to a logic low level is implemented. Various settings can be made according to the example. The first to fourth pull-up code signals PU_CAL <1: 4> are counted to calibrate the pull-up / pull-down driving of the output buffer 27 using a ZQ resistor in a conventional impedance calibration circuit. Signals.

The pull-down predriver 24 receives the first internal data IDATA (n) and responds to the first to fourth pull-down code signals PD_CAL <1: 4> to the first to fourth pull-downs. A down signal PD <1: 4> is generated. More specifically, the pull-down predriver 24 may include the first to fourth pull-down signals PD <which are disabled at the logic low level when the first internal data IDATA (n) is at the logic high level. 1: 4>). Also, the pull-down predriver 24 may include the first to fourth pull-down signals PD <1: 4> when the first internal data IDATA (n) has a logic low level. Only signals selected according to the pull-down code signals PD_CAL <1: 4> are enabled at a logic high level and output. For example, when the first pull-down code signal PD_CAL <1> is at a logic high level, the first pull-down signal PD <1> is enabled at a logic high level, and the second pull-down code is enabled. When the signal PD_CAL <2> is at the logic high level, the second pull-down signal PD <2> is enabled at the logic high level, and the third pull-down code signal PD_CAL <3> is at the logic high level. Level, the third pull-down signal PD <3> is enabled at a logic high level, and when the fourth pull-down code signal PD_CAL <4> is at a logic high level, the fourth pull-down signal PD <3> is enabled. PD <4>) is enabled at a logic high level. The combination of the first to fourth pull-down code signals PD_CAL <1: 4> for selectively enabling the first to fourth pull-down signals PD <1: 4> to a logic low level is implemented. Various settings can be made according to the example. The first to fourth pull-down code signals PD_CAL <1: 4> are counted to calibrate the pull-up / pull-down driving of the output buffer 27 using a ZQ resistor in a conventional impedance calibration circuit. Signals.

As shown in FIG. 5, the pull-up driver 25 is connected between the power supply voltage VDD and the node nd20 and turned on in response to the first pull-up signal PU <1>. P20, a resistor R20 connected between the node nd20 and the node nd200, and a power supply voltage VDD and the node nd21 connected to the second pull-up signal PU <2>. In response to the PMOS transistor P21 turned on, the resistor R21 connected between the node nd21 and the node nd200, and the power supply voltage VDD and the node nd22, are connected to the third pull-up signal ( PMOS transistor P22 that is turned on in response to PU <3>, resistor R22 connected between node nd22 and node nd200, and is connected between power supply voltage VDD and node nd23, PMOS transistor P23 turned on in response to pull-up signal PU <4>, resistor R23 connected between node nd23 and node nd200, power supply voltage VDD, and node nd24. ) Is connected to the first pull-up emphasizing signal PU_EMP <1>. The PMOS transistor P24 turned on, the resistor R24 connected between the node nd24 and the node nd200, and the power supply voltage VDD and the node nd25 are connected to each other to form a second pull-up emphasis signal ( PMOS transistor P25 turned on in response to PU_EMP <2> and a resistor R25 coupled between node nd25 and node nd200.

As shown in FIG. 5, the pull-down driver 26 is connected between the node nd200 and the node nd26 and between the node nd26 and the ground voltage VSS. 1 NMOS transistor N26 turned on in response to pull-down signal PD <1>, resistor R27 connected between node nd200 and node nd27, node nd27 and ground voltage VSS. NMOS transistor N27 connected between the NMOS transistor N27 turned on in response to the second pull-down signal PD <2>, a resistor R28 connected between the node nd200 and the node nd28, and the node nd28. ) Is connected between the ground voltage VSS and the NMOS transistor N28 turned on in response to the third pull-down signal PD <3>, and the resistor R29 connected between the node nd200 and the node nd29. And an NMOS transistor N29 connected between the node nd29 and the ground voltage VSS and turned on in response to the fourth pull-down signal PD <4>.

The de-emphasis function of the output buffer configured as described above will be described with reference to FIG. 6. However, the timing diagram shown in FIG. 6 includes the first to fourth pull-up code signals PU_CAL <1: 4>, the first to fourth pull-down code signals PD_CAL <1: 4>, and the first to fourth pull-up code signals PD_CAL <1: 4>. It is assumed that all of the second emulation enable signals DEEMP_EN <1: 2> are applied at a logic high level.

First, the second multiplexer 22 multiplexes input first through M-th data DATA (n) <1: M> to generate first internal data IDATA (n). As shown in FIG. 6, the first internal data IDATA (n) has a logic low level from t20 to t22, a logic high level from t2 to t24, a logic low level from t24 to t25, and a logic high level from t25 to t26. , logic low level from t26 to t28, and logic high level from t28 to t29.

Next, the pull-up pre-driver 23 may disable the first to fourth pull-up signals PU <1: all of which are disabled at a logic high level when the first internal data IDATA (n) has a logic low level. 4>). In addition, the pull-up predriver 23 may include the first to fourth pull-up signals PU <1: 4, which are all enabled at a logic low level when the first internal data IDATA (n) is at a logic high level. >), Since all of the first to fourth pull-up code signals PU_CAL <1: 4> are applied at a logic high level.

Next, the pull-down predriver 24 may include the first to fourth pull-down signals PD <1: all of which are disabled at a logic low level when the first internal data IDATA (n) has a logic high level. 4>). In addition, the pull-down predriver 24 may include the first to fourth pull-down signals PD <1: 4 that are all enabled at a logic high level when the first internal data IDATA (n) has a logic low level. >), Since all of the first to fourth pull-down code signals PD_CAL <1: 4> are applied at a logic high level.

The first multiplexer 20 multiplexes the first to M-th inversion data DATAB (n + 1) <1: M> in response to the clock signal CLK to form the second internal data IDATAB (n + 1). Create

Next, the predriver 21 may disable the first to second pull-up emphasis signals PU_EMP <1, which are all disabled at a logic high level when the second internal data IDATAB (n + 1) is at a logic low level. 2>). In addition, the predriver 21 may include the first to second pull-up emphasis signals PU_EMP <1: 2 that are all enabled at a logic low level when the second internal data IDATAB (n + 1) is at a logic high level. >), Since all of the first to second emulation enable signals DEEMP_EN <1: 2> are applied at a logic high level.

Next, the pull-up driver 25 and the pull-down driver 26 drive the output data OUT output to the output pad 27.

Hereinafter, a driving operation of the output data OUT by the pull-up driver 25 and the pull-down driver 26 will be described in detail.

All of the NMOS transistors N14 to N19 of the pull-down driver 26 are turned on by the first to fourth pull-down signals PD <1: 4> which are all enabled at a logic high level from t20 to t21. And pull-up by the first to fourth pull-up signals PU <1: 4> and the first to second pull-up emulation signals PU_EMP <1: 2> that are disabled at a logic high level. The PMOS transistors N20 to N25 of the driver 25 are all turned off. Therefore, the output data OUT is pulled down with a large amplitude.

Since there is no level transition of the first internal data IDATA (n) from t21 to t22, the first to second pull-up emphasis signals PU_EMP <1: 2> are enabled at a logic low level so that the full-driver PMOS transistors N24 to N25 of 25 are turned on, and the driving force for pull-down driving the output data OUT is reduced. Therefore, the amplitude of the output data OUT is reduced.

From t22 to t23, the first to fourth pull-up signals PU <1: 4> and the first to fourth pull-down signals PD <1: 4> are all disabled at a logic low level. Since all of the first to second pull-up emphasis signals PU_EMP <1: 2> are enabled at a logic low level, all of the PMOS transistors P20 to P25 of the pull-up driver 25 are turned on. Therefore, the output data OUT is pulled up with a large amplitude.

From t23 to t24, the first to second pull-up emphasis signals PU_EMP <1: 2> are disabled to a logic high level so that the PMOS transistors P24 to P25 of the pull-up driver 25 are turned off. . Therefore, the driving force for pulling up the output data OUT is reduced, so that the amplitude of the output data OUT is reduced.

As described above, the output buffer according to the present embodiment drives the output data OUT with a large driving force when the level transition of the first internal data IDATA (n) occurs, and then the first internal data IDATA (n). If the level is kept constant, the driving force for driving the output data OUT is reduced to implement the de-emphasis function.

(Figure 1)
10: first multiplexer 11: pull-up free driver
12: pull-down free driver 13: second multiplexer
14: Free driver 15: Full driver
16: pull-down driver 17: output pad
(Figure 4)
20: first multiplexer 21: free driver
22: second multiplexer 23: pull-up free driver
24: Pull-down free driver 25: Pull-up driver
26: pull-down driver 27: output pad

Claims (12)

A pull-up driver that receives the first internal data and generates a pull-up signal enabled in response to the pull-up code;
A pull-down free driver which receives the first internal data and generates a pull-down signal enabled in response to a pull-down code;
A pre-driver receiving the second internal data and generating a pull-down emphasizing signal enabled in response to the enable signal;
A pull-up driver for pull-up driving output data output to an output pad in response to the pull-up signal; And
And a pull-down driver configured to pull-down the output data in response to the pull-down signal and the pull-down emphasis signal.
The output buffer of claim 1, wherein the pull-up cord and the pull-down cord are counted by impedance calibration using an external resistor connected to the output pad.
The output buffer of claim 1, wherein the second internal data is a signal obtained by shifting the first internal data by one bit and inverting the first internal data.
The second driver of claim 1, wherein the predriver outputs the enabled first pull-down emphasis signal when the first enable signal is enabled while the second internal data is at a logic high level. An output buffer for outputting the enabled second pull-down emphasizing signal when the enable signal is enabled.
The method of claim 1, wherein the pull-up driver
A first switch connected between a power supply voltage and a first node and turned on in response to the pull-up signal; And
And a first resistor connected between the first node and an output node on which the output data is output.
The method of claim 5, wherein the pull-down driver
A second resistor connected between the output node and a second node;
A second switch connected between the second node and a ground voltage and turned on in response to the pull-down signal;
A third resistor connected between the output node and a third node; And
And a third switch connected between the third node and the ground voltage and turned on in response to the pull-down emphasizing signal.
A pull-up driver that receives the first internal data and generates a pull-up signal enabled in response to the pull-up code;
A pre-driver receiving the second internal data to generate a pull-up emphasizing signal enabled in response to the enable signal;
A pull-down free driver which receives the first internal data and generates a pull-down signal enabled in response to a pull-down code;
A pull-up driver for pull-up driving output data output to an output pad in response to the pull-up signal and the pull-up emphasis signal; And
And a pull-down driver configured to pull-down the output data in response to the pull-down signal.
8. The output buffer of claim 7, wherein the pull-up cord and the pull-down cord are counted by impedance calibration using an external resistor connected to the output pad.
The output buffer of claim 7, wherein the second internal data is a signal obtained by shifting the first internal data by one bit and inverting the first internal data.
8. The method of claim 7, wherein the predriver outputs the enabled first pull-up emphasis signal when the first enable signal is enabled while the second internal data is at a logic low level. An output buffer configured to output the enabled second pull-up emphasis signal when the enable signal is enabled.
The method of claim 7, wherein the pull-up driver
A first switch connected between a power supply voltage and a first node and turned on in response to the pull-up signal;
A first resistance element connected between the first node and an output node on which the output data is output;
A second switch connected between the power supply voltage and a second node and turned on in response to the pull-up emphasizing signal; And
An output buffer including a second resistor connected between the second node and the output node.
The method of claim 11, wherein the pull-down driver
A third resistor connected between the output node and a third node; And
And a third switch connected between the third node and a ground voltage and turned on in response to the pull-down signal.
KR1020100051287A 2010-05-31 2010-05-31 Output buffer KR20110131710A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190105863A (en) * 2018-03-06 2019-09-18 에스케이하이닉스 주식회사 Data output buffer
KR20190135863A (en) * 2018-05-29 2019-12-09 에스케이하이닉스 주식회사 Data output buffer and memory device having the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190105863A (en) * 2018-03-06 2019-09-18 에스케이하이닉스 주식회사 Data output buffer
KR20190135863A (en) * 2018-05-29 2019-12-09 에스케이하이닉스 주식회사 Data output buffer and memory device having the same

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