KR20110113257A - Liquid crystal display and dithering method thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display, wherein the compensation value is selected according to lower N (N is a positive integer of 2 or more) bit data in a dither matrix defining a time and a position to which a compensation value is applied, and the compensation value is higher. A first dither processor which adds M bit data to M (M is a positive integer of 2 or more) and outputs compensated M bit data; A second dither processor which selects the compensation value according to the lower N bit data in the dither matrix and adds the compensation value to upper M bit data to output compensated M + 1 bit data; A normalization operation unit converting the compensated M + 1 bit data into normalized M bit data; And an averaging processing unit for alternately selecting the compensated M bit data and the normalized M bit data at predetermined time periods.

Description

Liquid crystal display and its dithering method {LIQUID CRYSTAL DISPLAY AND DITHERING METHOD THEREOF}

The present invention relates to a liquid crystal display and a dithering method thereof.

The liquid crystal display of the active matrix driving method displays a moving image using a thin film transistor (hereinafter referred to as TFT) as a switching element. The liquid crystal display device can be miniaturized compared to a cathode ray tube (CRT), which is applied to a display device in a portable information device, an office device, a computer, and a TV, and is rapidly replacing a cathode ray tube.

In the liquid crystal display, a dithering method using a frame rate control (FRC) is applied to express a color expression range. As an example of a dithering method, 8 bit data of an input image is divided into 6 bits of upper (Most Significant Bits, MSBs) and 2 bits of lower (Least Significant Bits, LSBs), and the temporal and spatial information of the lower 2 bit information is used. By compensating the upper 6 bits with a dither matrix as shown in FIG. 1, the color depth of 6 bits can be extended similarly to the color depth effect of 8 bits. In the dither matrix of FIG. 1, the portion represented in black is the compensation value '1' to be added to the upper 6 bits. The compensation value is not set in the white part. The compensation value is added to the upper 6 bits defined by the dither matrix using lower 2 bit information, time information and spatial information of the lower 2 bits. For example, when the lower two bits are '10', the compensation value '1' is added twice to the upper six bits of the same pixel position for four frame periods. In this case, since the decimal number '4' is added to the upper 6 bit data twice, a result of adding a compensation value to the upper 6 bit data by the loss of the lower 2 bits can be obtained.

However, in the conventional dithering method, when the gray value of the upper 6 bit data of the 8 bit input image is larger than the decimal number '252' or the binary number '111111 ₂ ', the upper 6 bit output is fixed to '63' as shown in FIG. Problem, or 'gradation saturation phenomenon'. This is because a compensation value cannot be added to '111111 ₂ '. Such gradation saturation phenomenon limits the number of colors that can be represented in the liquid crystal display.

The present invention provides a liquid crystal display device having no gradation saturation phenomenon and a dithering method thereof.

The liquid crystal display of the present invention selects the compensation value according to the lower N (N is a positive integer of 2 or more) bit data in the dither matrix defining the time and position to which the compensation value is applied, and sets the compensation value to the upper M (M). Is a first dither processor that adds two or more positive integer bit data and outputs compensated M bit data; A second dither processor which selects the compensation value according to the lower N bit data in the dither matrix and adds the compensation value to upper M bit data to output compensated M + 1 bit data; A normalization operation unit converting the compensated M + 1 bit data into normalized M bit data; And an averaging processing unit for alternately selecting the compensated M bit data and the normalized M bit data at predetermined time periods.

으로 정의된다. When the compensated M + 1 bit data is called D2 and the normalized M bit data is called DN1, DN1 is

Is defined.

The liquid crystal display device includes: a data driver circuit for converting data output from the averaging processor into analog data voltages and outputting the data lines to data lines of the liquid crystal display panel; A gate driving circuit sequentially supplying gate pulses to gate lines crossing the data lines of the liquid crystal display panel; And receiving pixel data of a K (where K = M + N) bit, a vertical synchronizing signal, and a data enable signal, and supplying data output from the averaging processor to the data driving circuit. A timing controller for controlling an operation timing of the gate driving circuit is further provided.

The liquid crystal display further includes a counter for counting the vertical synchronization signal and the data enable signal and generating a control signal for controlling a switching time of the averaging processor.

The first dither processor may include: a bit converter configured to receive pixel data of the K bit and separate the upper M bit data and the lower N bit data; A first compensation selector which selects a compensation value from the dither matrix based on a count result of the counter; And a first adder configured to add the compensation value selected by the first compensation selector to the upper M bit data to output the compensated M bit data.

The second dither processor may include a second compensation selector configured to select a compensation value from the dither matrix based on a count result of the counter; And a second adder configured to add the compensation value selected by the second compensation selector to the upper M bit data to output the upper M + 1 bit data.

The normalization calculator comprises: a multiplier for outputting 2M bit data by multiplying the upper M + 1 bit data by 2 ^M −1; And a bit shifter for shifting the 2M bit data to the right by M bits to output the normalized M bit data.

The dithering method of the liquid crystal display selects the compensation value according to lower N (N is a positive integer of 2 or more) bit data in a dither matrix defining a time and a position to which the compensation value is applied, and sets the compensation value to an upper M ( Outputting the compensated M bit data by adding M to a positive integer of 2 or more) bit data; Selecting the compensation value according to the lower N bit data in the dither matrix, adding the compensation value to upper M bit data, and outputting compensated M + 1 bit data; Converting the compensated M + 1 bit data into normalized M bit data; And alternately selecting the compensated M bit data and the normalized M bit data at predetermined time periods.

The present invention can minimize grayscale saturation in dithering by applying M + 1 bit dithering and M bit normalization together with M bit dithering and compensating the upper M bit data with the average.

1 is a diagram illustrating an example of a dither matrix.
FIG. 2 is a diagram showing grayscale saturation occurring in a conventional dithering method.
3 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.
4 through 6 are equivalent circuits showing various pixel arrays of the present invention.
FIG. 7 is a circuit diagram showing in detail the dither processor shown in FIG. 3.
FIG. 8 is a circuit diagram illustrating in detail the averaging processing unit shown in FIG. 7.
9 is a flowchart showing step by step a control procedure of a dithering method according to an embodiment of the present invention.
10 is a graph showing output data of the first dither unit processing unit, normalized data, and output results of the averaging processing unit.

In the dithering method of the present invention, an input image includes K including M bit (MSBs) of M (M is a positive integer of 2 or more) and L bit data (LSBs) of N (N is a positive integer of 2 or more). Assume that K = M + N bits of pixel data.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like numbers refer to like elements throughout. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

Component names used in the following description may be selected in consideration of ease of specification, and may be different from actual product part names.

Referring to FIG. 3, a liquid crystal display according to an exemplary embodiment of the present invention may include a liquid crystal display panel 100, a data driving circuit 102, a gate driving circuit 103, a dither processor 105, and a timing controller 101. Equipped. The data driver circuit 102 includes a plurality of source drive ICs. The gate driving circuit 103 includes a plurality of gate drive ICs.

The liquid crystal display panel 100 includes a TFT array substrate, a color filter array substrate facing the TFT array substrate, and a liquid crystal layer formed between the TFT array substrate and the color filter array substrate. A pixel array as shown in FIGS. 4 to 6 may be formed on the TFT array substrate.

The TFT array substrate may include one or more TFTs formed at the intersections of the data lines 105, the gate lines 106, the data lines 105 and the gate lines 106 formed on the lower glass substrate, and the TFTs. Pixel electrodes, storage capacitors, and the like, connected to one; The color filter array substrate includes a black matrix, a color filter, and the like formed on the upper glass substrate. A polarizing plate is attached to each of the upper glass substrate and the lower glass substrate, and an alignment layer for setting the pre-tilt angle of the liquid crystal is formed.

The common electrode facing the pixel electrode in the liquid crystal display panel 100 is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and in plane switching (IPS) mode. In the horizontal electric field driving method such as FFS (Fringe Field Switching) mode, the pixel electrode is formed on the lower glass substrate.

The liquid crystal display panel 100 applicable to the present invention may be implemented in any liquid crystal mode as well as a TN mode, a VA mode, an IPS mode, and an FFS mode. The liquid crystal display of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display. In the transmissive liquid crystal display device and the transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

Each of the source drive ICs of the data driver circuit 102 includes a shift register, a latch, a digital-to-analog converter, an output buffer, and the like. The source drive ICs are mounted on a source Tape Carrier Package (TCP), bonded to a TFT array substrate of the liquid crystal display panel 100 by a tape automated bonding (TAB) process, and connected to a source printed circuit board (PCB). The source drive ICs may be bonded onto the TFT array substrate of the liquid crystal display panel by a chip on glass (COG) process. Data output channels of each of the source drive ICs are connected 1: 1 to the data lines 105. The source drive ICs latch M bit digital video data R'G'B 'input from the timing controller 101. In response to the polarity control signal POL, the source drive ICs convert the M bit digital video data R'G'B 'into analog positive / negative gamma compensation voltages to reverse the polarity of the data voltages. The source drive ICs output positive / negative data voltages to the data lines 105 in response to the source output enable signal SOE.

The gate driving circuit 103 uses the shift register and the level shifter to gate the gate pulses in response to the gate timing control signals GSP, GSC, and GOE input from the timing controller 101 during the active period ACT. It supplies to 106 sequentially. The gate driving circuit 103 is mounted on a gate TCP (not shown) and bonded to a TFT array substrate of a liquid crystal display panel by a TAB process, or simultaneously on a TFT array substrate with a pixel array by a GIP (Gate In Panel) process. Can be formed directly.

The dither processing unit 105 outputs the first dither processing unit generating a dither output of M bit, the second dither processing unit generating a dither output of M + 1 bit, and the output of the second dither processing unit not exceeding a gray value of 2 ^M −1. A normalization operation unit for re-mapping to a non-valued value, and an averaging processing unit for averaging the outputs of the first dither processing unit and the outputs of the second dither processing unit. The dither processor 105 generates an output R'G'B 'of M bits without grayscale saturation. The detailed configuration and operation of the dither processor 105 will be described later with reference to FIGS. 7 to 10.

The timing controller 101 transfers the digital video data RGB of the input image input from the system board 104 to the dither processor 105, and inputs the output R'G'B 'of the dither processor 105. The data R'G'B 'is transmitted to the data driving circuit 102. The dither processor 105 may be built in the timing controller 101.

The timing controller 101 receives timing signals such as a vertical sync signal Vsync, a horizontal sync signal Hsync, a data enable signal Data Enable (DE), and a dot clock CLK from the system board 104. Control signals for controlling the operation timing of the driving circuit 102 and the gate driving circuit 103 are generated. The control signals include a gate timing control signal for controlling the operation time of the gate driving circuit 103, a data timing control signal for controlling the operation timing of the data driving circuit 102 and the vertical polarity of the data voltage.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP is applied to the gate drive IC that generates the first gate pulse to control the gate drive IC so that the first gate pulse is generated. The gate shift clock GSC is a clock signal commonly input to gate drive ICs and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE). It includes. The source start pulse SSP controls the data sampling start timing of the data driving circuit 102. The source sampling clock SSC is a clock signal that controls sampling timing of data in each of the source drive ICs based on a rising or falling edge. The polarity control signal POL controls the polarity inversion timing of the data voltages output from each of the source drive ICs. The source output enable signal SOE controls the output timing of the data driver circuit 102. If the digital video data to be input to the data driving circuit 102 is transmitted in mini LVDS (Low Voltage Differential Signaling) interface standard, the source start pulse SSP and the source sampling clock SSC may be omitted.

4 to 6 are equivalent circuits showing various examples of the pixel array formed on the TFT array substrate.

In the pixel array shown in FIG. 4, each of the red subpixel R, the green subpixel G, and the blue subpixel B is disposed along the column direction. Each of the TFTs includes a pixel electrode of a liquid crystal cell in which data voltages from the data lines D1 to D6 are disposed on the left side (or right side) of the data lines D1 to D6 in response to gate pulses from the gate lines G1 to G4. To feed. In the TFT array shown in FIG. 4, one pixel includes neighboring red subpixels R, green subpixels G, and blue subpixels B along a row direction (or line direction) perpendicular to the column direction. . When the resolution of the TFT array shown in FIG. 4 is m × n, m × 3 (where 3 is RGB) data lines and n gate lines are required.

In the pixel array illustrated in FIG. 5, the number of data lines D1 to D4 required at the same resolution is 1/2 as compared to the pixel array illustrated in FIG. 4 by subpixels adjacent to each other in the line direction. The number of source drive ICs required can be reduced by one half. In this TFT array, each of the red subpixel R, the green subpixel G, and the blue subpixel B are disposed along the column direction. In the pixel array illustrated in FIG. 5, one pixel includes neighboring red subpixels R, green subpixels G, and blue subpixels G along a line direction perpendicular to the column direction. Two liquid crystal cells adjacent in the line direction share the same data line and sequentially charge the data voltages supplied through the data line. The liquid crystal cell and the TFT disposed on the left side of the data lines D1 to D4 are defined as the first liquid crystal cell and the first TFT TFT1, respectively, and the liquid crystal cell and the TFT disposed on the right side of the data line D1 to D4 are defined. A connection relationship between the TFTs TFT1 and TFT2 will be described as defined by the second liquid crystal cell and the second TFT TFT2, respectively. The first TFT TFT1 supplies data voltages from the data lines D1 to D4 to the pixel electrodes of the first liquid crystal cell in response to gate pulses from the odd gate lines G1, G3, G5, and G7. The gate electrode of the first TFT TFT1 is connected to the odd gate lines G1, G3, G5, and G7, and the drain electrode is connected to the data lines D1 to D4. The source electrode of the first TFT (TFT1) is connected to the pixel electrode of the first liquid crystal cell. The second TFT TFT2 supplies the data voltage from the data lines D1 to D4 to the pixel electrode of the second liquid crystal cell in response to the gate pulses from the even gate lines G2, G4, G6, and G8. The gate electrode of the second TFT TFT2 is connected to the even gate lines G2, G4, G6, and G8, and the drain electrode is connected to the data lines D1 to D4. The source electrode of the second TFT (TFT2) is connected to the pixel electrode of the second liquid crystal cell.

The pixel array shown in FIG. 6 can arrange subpixels of the same color in a row direction to reduce the number of data lines required at the same resolution by one third compared to the pixel array shown in FIG. The number can be reduced to 1/3. In this TFT array, each of the red subpixel R, the green subpixel G, and the blue subpixel B is disposed along the line direction. In the pixel array illustrated in FIG. 6, one pixel includes neighboring red subpixels R, green subpixels G, and blue subpixels G in a column direction. Each of the TFTs includes a pixel electrode of a liquid crystal cell in which data voltages from the data lines D1 to D6 are disposed on the left side (or right side) of the data lines D1 to D6 in response to gate pulses from the gate lines G1 to G6. To feed.

FIG. 7 is a circuit diagram showing in detail the dither processor 105 shown in FIG. 3.

Referring to FIG. 7, the dither processor 105 includes a first dither processor 50, a second dither processor 60, a normalization calculator 70, and an averaging processor 55.

The first dither processor 50 generates an output D1 of M bits that compensates the upper M bit data with a compensation value selected according to the lower N bit data and the dither matrix. The first dither processor 50 includes a bit converter 51, a counter 54, a first compensation selector 52, a first adder 53, and the like.

The bit converter 51 receives K bit pixel data RGB and separates upper M bit data and lower N bit data. The higher order M bit data is input to the first adder 53 and the second adder 63 of the second dither processor 60 described later. The lower N-bit data is input to the first compensation selector 52 and the second adder 63 of the second dither processor 60 described later.

The counter 54 counts the vertical synchronization signal Vsync and the data enable signal DE. The vertical synchronization signal Vsync indicates a frame period to which the pixel data RGB currently input belongs, and the data enable signal DE indicates a horizontal line of the display panel 100 to which the pixel data RGB currently input belongs. . The outputs FR and LN of the counter 54 include a frame count result FR and a line count result LN, and include a first compensation selector 52 and a second dither processor 60 to be described later. It is input to the compensation selection unit 62. The counter 54 also counts the frame period and generates a control signal SEL whose logic is inverted in units of j (j is a positive integer of 2 or more). The control signal SEL is input to the averaging processor 55 to control the switching timing of the averaging processor 55.

The first compensation selector 52 stores a 2 × 4 dither matrix or a 4 × 4 dither matrix as shown in FIG. 1. The first compensation selector 52 receives the output of the counter 54 and determines the frame period and line position of the pixel data RGB currently input. The first compensation selector 52 selects a compensation value by using the lower N bit data as an input address of the dither matrix. The compensation value is selected as '1' to be added to the upper M bit data. The selected compensation value is input to the first adder 53. In order to reduce dither noise, the position of the compensation value may be set differently every frame period as shown in FIG. 1. In FIG. 1, a black portion indicates a position of a compensation value to be added to the upper 6 bits.

The first adder 53 adds the compensation value input from the first compensation selector 52 to the upper M bit data to generate an output D1 of M bits, and averages the output D1 of the M bits. Supply to 55.

The second dither processor 60 generates an output D2 of M + 1 bits that compensates for the upper M bit data with the compensation value selected according to the lower N bit data and the dither matrix. The second dither processor 60 includes a second compensation selector 62, a second adder 63, and the like.

The second compensation selecting unit 62 stores a 2x4 dither matrix or a 4x4 dither matrix. The dither matrix stored in the second compensation selector 62 may be set to be the same as the dither matrix stored in the first compensation selector 52 or may be set to a dither matrix having a different compensation value position. The second compensation selector 62 receives the output of the counter 54 and determines the frame period and line position of the pixel data RGB currently input. The second compensation selector 62 selects a compensation value by using the lower N bit data as an input address of the dither matrix. The compensation value is selected as '1' to be added to the upper M bit data. The selected compensation value is input to the second adder 63.

The second adder 63 adds the compensation value input from the second compensation selector 62 to the upper M bit data to generate an output D2 of M + 1 bits, and outputs the M + 1 bit D2. ) Is supplied to the normalization operation unit 70.

The normalization operation unit 70 includes a multiplier 64 and a bit shifter 65. The multiplier 64 outputs a 2M bit data is multiplied by 2 ^M -1 for M + 1 bit data (D2) from a second dither processor 60. The bit shifter 65 shifts the 2M bit data input from the multiplier 64 to the right by M bits to generate normalized M bit data DN1 for the division operation of the 2M bit data. The normalized M bit data is input to the averaging processor 55. The normalization operation result of the normalization operation unit 70 is shown in Equation 1 below.

The averaging processor 55 may be implemented as a multiplexer as shown in FIG. 8. The multiplexer selects the output D1 of the first dither section for j consecutive frame periods in response to the control signal SEL from the counter 54, and then selects the normalized data DN1 for the next j frame periods. do.

9 is a flowchart showing step by step a control procedure of a dithering method according to an embodiment of the present invention.

Referring to FIG. 9, the dithering method of the present invention receives K bit pixel data, a vertical synchronization signal Vsync, and a data enable signal DE (S1).

The dithering method of the present invention outputs the compensated first M bit data D1 by adding a compensation value to the upper M bit data at a time and location defined by the dither matrix using the first dither processor 50. (S21) At the same time, the dithering method of the present invention uses the second dither processing unit 60 to add M + 1 bit data (compensated by adding a compensation value to upper M bit data at a time and position defined by a dither matrix). D2) is output (S22).

Subsequently, the dithering method of the present invention converts M + 1 bit data D2 into normalized M bit data DN1 using a normalization algorithm as shown in Equation 1 (S3).

Subsequently, the dithering method of the present invention alternately selects M bit data D1 and normalized M bit data compensated for a j frame period and performs dithering with an average value of two data D1 and DN1.

FIG. 10 is a graph illustrating output data D1 of the first dither unit processing unit 50, normalized data DN1, and output result AVER of the averaging processing unit 55.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

50: first dither processor 55: averaging processor
60: second dither processor 70: normalization calculator
100: liquid crystal display panel 101: timing controller
102: data driving circuit 103: gate driving circuit
104: system board 105: dither processor

Claims (7)

In the dither matrix defining the time and position to which the compensation value is applied, the compensation value is selected according to lower N (N is a positive integer of 2 or more) bit data, and the compensation value is higher M (M is a positive integer of 2 or more). a first dither processor for adding M bit data compensated by adding the bit data;
A second dither processor which selects the compensation value according to the lower N bit data in the dither matrix and adds the compensation value to upper M bit data to output compensated M + 1 bit data;
A normalization operation unit converting the compensated M + 1 bit data into normalized M bit data; And
An averaging processor configured to alternately select the compensated M bit data and the normalized M bit data at predetermined time periods;
When the compensated M + 1 bit data is called D2 and the normalized M bit data is called DN1, DN1 is

Liquid crystal display characterized in that defined by. The method of claim 1,
A data driving circuit converting the data output from the averaging processor into an analog data voltage and outputting the data to the data lines of the liquid crystal display panel;
A gate driving circuit sequentially supplying gate pulses to gate lines crossing the data lines of the liquid crystal display panel; And
Receives pixel data of a K (where K = M + N) bit, a vertical synchronizing signal, and a data enable signal, and supplies data output from the averaging processing unit to the data driving circuit, wherein the data driving circuit and the And a timing controller for controlling the operation timing of the gate driving circuit. The method of claim 2,
And a counter for counting the vertical synchronization signal and the data enable signal and generating a control signal for controlling the switching time of the averaging processing unit. The method of claim 3, wherein
The first dither processor,
A bit converter which receives the K bit pixel data and separates the upper M bit data and the lower N bit data;
A first compensation selector which selects a compensation value from the dither matrix based on a count result of the counter;
And a first adder configured to output the compensated M bit data by adding the compensation value selected by the first compensation selector to the upper M bit data. The method of claim 4, wherein
The second dither processor,
A second compensation selecting unit which selects a compensation value from the dither matrix based on a count result of the counter;
And a second adder configured to output the upper M + 1 bit data by adding the compensation value selected by the second compensation selector to the upper M bit data. The method of claim 5, wherein
The normalization operation unit,
A multiplier for outputting 2M bit data by multiplying the upper M + 1 bit data by 2 ^M −1; And
And a bit shifter for shifting the 2M bit data to the right by M bits to output the normalized M bit data. In the dither matrix defining the time and position to which the compensation value is applied, the compensation value is selected according to lower N (N is a positive integer of 2 or more) bit data, and the compensation value is higher M (M is a positive integer of 2 or more). outputting the compensated M bit data by adding to the bit data;
Selecting the compensation value according to the lower N bit data in the dither matrix, adding the compensation value to upper M bit data, and outputting compensated M + 1 bit data;
Converting the compensated M + 1 bit data into normalized M bit data; And
Alternately selecting the compensated M bit data and the normalized M bit data at predetermined time periods,
When the compensated M + 1 bit data is called D2 and the normalized M bit data is called DN1, DN1 is

Dithering method of the liquid crystal display device characterized in that defined by.

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