KR20110033915A - Spread spectrum clock generator - Google Patents

Abstract

PURPOSE: A spread spectrum clock generator providing a structure is provided to safely generate a spread spectrum clock by forming a spread spectrum clock generator by using an oscillator. CONSTITUTION: A phase-frequency detector(310) outputs an up/down signal by comparing a phase and a frequency of an output clock signal fed back from an input clock signal and an oscillator. A charge pump(320) generates a current corresponding to the up/down signal inputted from the phase-frequency detector. A loop filter(330) outputs an analog voltage control signal corresponding to a current amount inputted from a charge pump. According to the oscillator(340), an oscillator adjusts a center frequency of the output clock signal according to the analog voltage control signal. According to a N bit digital signal, the oscillator modulates a frequency of the output clock signal.

Description

 Spread Spectrum Clock Generator {SPREAD SPECTRUM CLOCK GENERATOR}

TECHNICAL FIELD The present invention relates to the design technology of spread spectrum clock generators, and in particular, to simplify the configuration and spread spectrum to maintain a stable frequency modulation ratio against temperature, supply voltage and process variation (PVT variation). It relates to a clock generator.

Recently, the voltage control oscillator (VCO), which is an internal block of a phase locked loop (PLL) required to adjust data timing at data transmission / reception terminals between interfaces as operating frequencies and data input bits of various information devices increases. Electromagnetic interference (EMI) is remarkably generated by the high frequency clock signal generated by the oscillator, which causes a malfunction in the peripheral circuit. Spread Spectrum Clock Generator (SSCG) can reduce the power density of the output frequency of the output signal by using the spread spectrum of the output signal frequency. It is known as a means.

In other words, the spread spectrum clock generator is a circuit that receives an external clock signal and outputs a clock signal whose frequency varies with a constant modulation frequency and a constant modulation ratio. For example, when a 100 MHz clock signal is input from the outside, a spread spectrum clock generator that generates a clock signal having a frequency modulation ratio of ± 1% and a modulation frequency of 100 kHz is a center of 100 MHz. It generates and outputs a clock signal that changes between 99MHz and 101MHz in 10usec periods based on frequency. As such, the spread-spectrum clock generator intentionally finely modulates the frequency of the clock signal so that the peak power of the clock signal is dispersed and lowered at a specific frequency, thereby reducing electromagnetic interference (EMI) emission.

1 illustrates a conventional method using an analog frequency modulation scheme (eg, Hsiang-Hui Chang, I-Hui Hua, and Shen-Iuan Liu, “A Spread Spectrum Clock Generator with Triangular Modulation,” IEEE Journal of Solid-State Circuits, vol. 38, no. 4, pp. 673-676, april 2003), a block diagram of a spread spectrum clock generator, as shown here, a phase frequency detector 110, a charge pump 120, 140, a clock divider. 130, a loop filter 150, and a voltage controlled oscillator 160.

The phase frequency detector 110, the charge pump 120, the loop filter 150, and the voltage controlled oscillator 160 are components of a basic PLL, and the clock divider 130 and the charge pump 140 are spread spectrum modulated. Generate an analog modulation waveform for.

That is, the clock divider 130 divides the input clock signal CLK _IN to match the spread spectrum modulation frequency, and the charge pump 140 up / down current signal corresponding to the divided clock signal as described above. Is generated and output to the connection points of the resistors R1 and R2 of the loop filter 150, thereby generating an analog modulation waveform in the form of a triangular wave for spread spectrum modulation.

Accordingly, the analog voltage control signal V _CTRL of the loop filter 150 exists in the form of a combination of the fundamental waveform and the analog modulation waveform by the PLL.

2 shows another conventional method using a sigma-delta frequency synthesizer (∑ △ fractional N frequency synthesizer, for example, Mitsutoshi Sugawara, Terukazu Ishibashi, Kazuo Ogasawara, Morishige Aoyama, Michael Zwerg, Steven Glowinski, Yukihiro Kameyama, Tomonori Yanagita, Muneo Fukaishi) , Shinichi Shimoyama, Takashi Ishibashi, and Toshihoro Noma, “1.5 Gbps, 5150 ppm Spread Spectrum SERDES PHY with a 0.3 mW, 1.5 Gbps level detector for serial ATA,” IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 60- 63, 2002, a block diagram of a spread spectrum clock generator, as shown here, clock divider 210, phase frequency detector 220, charge pump 230, loop filter 240, and voltage controlled oscillator 250. ), A functional N-divider 260, a? -Δ modulator 270, and a clock divider 280.

In the spread spectrum clock generator having the structure as shown in FIG. 2, the spreading ratio δ and the modulation waveform can be easily adjusted only by adjusting the division ratio using the Σ-Δ modulator 270 and the functional N-divider 260. Can be.

However, the conventional spread spectrum clock generator has a disadvantage in that the frequency modulation ratio is sensitive to ambient temperature, power supply voltage, and PVT variation, or is complicated to implement and occupies a lot of chip area.

Accordingly, the technical problem to be solved by the present invention is to provide a structure that can more simply implement a spread spectrum clock generator, and to maintain a stable frequency modulation ratio (modulation ratio) even under ambient temperature changes, power supply voltage and process changes To provide a spread spectrum clock generator.

The objects of the present invention are not limited to the above-mentioned objects. Other objects and advantages of the invention will be more clearly understood by the following description.

The present invention for achieving the above object comprises a phase frequency detector for comparing the phase and frequency of the input clock signal and the output clock signal fed back from the oscillator and outputs the up / down signal according to; A charge pump generating a current corresponding to an up / down signal input from the phase frequency detector; A loop filter for outputting an analog voltage control signal corresponding to the amount of current input from the charge pump; And an oscillator configured to adjust a center frequency of the output clock signal according to the analog voltage control signal and spread spectrum modulate the frequency of the output clock signal according to an N bit digital signal.

Another object of the present invention for achieving the above object comprises: a first clock divider for dividing an input clock signal at a required frequency and outputting it to one input terminal of a phase frequency detector; A second clock divider for dividing an output clock signal to output a signal having the same frequency as that of the first clock divider to the other input terminal of the phase frequency detector; A third clock divider for dividing the input clock signal to generate a clock frequency required by a spread spectrum modulator; A spread spectrum modulator for generating an N bit digital signal using a clock signal input from the third clock divider; A phase frequency detector for comparing a phase and a frequency of a clock signal input from the first and second clock dividers and outputting an up / down signal accordingly; A charge pump generating a current corresponding to an up / down signal input from the phase frequency detector; A loop filter for outputting an analog voltage control signal corresponding to the amount of current input from the charge pump; And an oscillator configured to adjust a center frequency of the output clock signal according to the analog voltage control signal and spread spectrum modulate the frequency of the output clock signal according to the N-bit digital signal.

Instead of using a typical sigma-delta frequency synthesizer or analog frequency modulation scheme, the invention uses a phase frequency detector, charge pump, loop filter, and an oscillator whose frequency is adjusted to an analog voltage signal and an N-bit digital signal. By implementing the generator, it is easy to implement the spread spectrum clock generator, and there is an effect that the frequency modulation ratio can stably generate the spread spectrum clock without being influenced by ambient temperature, power supply voltage, and process variations.

In addition, the spread spectrum clock generator according to the present invention has an effect that can be used to generate a frequency-modulated signal such as FM or FSK in various wired and wireless communication fields in addition to the spread spectrum clock generator.

1 is a block diagram of a conventional spread spectrum clock generator using an analog frequency modulation scheme.
2 is a block diagram of a spread spectrum clock generator using a sigma-delta frequency synthesizer.
3 is a block diagram of a spread spectrum clock generator in accordance with the present invention.
4 is a block diagram of another spread spectrum clock generator in accordance with the present invention.
5A is a detailed block diagram illustrating an implementation of an oscillator in FIG. 3 or 4.
FIG. 5B is a detailed circuit diagram of any delay cell in FIG. 5A. FIG.
6A is a detailed circuit diagram illustrating another embodiment of the oscillator in FIG. 3 or 4.
FIG. 6B is a detailed circuit diagram of any LC oscillator in FIG. 6A.
7 is a graph showing a simulation result of a spread spectrum clock generator according to the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a spread spectrum clock generator according to the present invention, as shown therein, a phase frequency detector (PFD) 310, a charge pump (CP) 320, a loop filter 330, and And an oscillator (oscillator) 340 whose frequency is adjusted by the analog voltage control signal V _CTRL and the digital signal MOD [N-1: 0].

The phase frequency detector 310 compares the phase and frequency of the input clock signal CLK _IN and the output clock signal CLK _OUT fed back from the oscillator 340 and outputs an up / down signal UP / DN according to a difference. do.

The charge pump 320 generates a corresponding amount of current according to the up / down signal UP / DN input from the phase frequency detector 310.

The loop filter 330 converts a current input from the charge pump 320 into an analog voltage control signal V _CTRL .

The oscillator 340 is different from a conventional voltage controlled oscillator (VCO) or a digital controlled oscillator (DCO) and an analog voltage control signal V _CTRL and an N bit digital signal MOD [N-1. : 0]) is an oscillator whose frequency is adjusted.

In particular, the oscillator 340 is controlled by the analog voltage control signal V _CTRL input from the loop filter 330 to adjust the center frequency of the output clock signal CLK _OUT to a desired frequency. In addition, the oscillator 340 spread-spectrum modulates the frequency of the output clock signal CLK _OUT by using the N-bit digital signal MOD [N-1: 0] input at arbitrary predetermined time intervals. do.

Therefore, the loop bandwidth of the PLL including the phase frequency detector 310, the charge pump 320, the loop filter 330, and the oscillator 340 is approximately 1/10 of the spread spectrum modulation frequency. The loop filter 330 should be designed to be as follows.

If the N-bit digital signal MOD [N-1: 0] is always fixed to a constant value without changing data, the spread spectrum clock generator 300 according to the present invention operates as a general PLL. However, when the N-bit digital signal MOD [N-1: 0] is changed at any predetermined time interval, the output clock signal CLK _OUT of the spread spectrum clock generator 300 according to the present invention is changed. The frequency is spread spectrum modulated by the digital signal MOD [N-1: 0].

라면, 그 N 비트의 디지털 신호(MOD[N-1:0])가 입력되는 임의의 정해진 시간 간격은 1/

/ 2N이 되어야 한다. The time interval at which the N-bit digital signal MOD [N-1: 0] is input depends on the type of modulation profile used. As a general example, a triangular modulation profile is used and the N-bit digital signal (MOD [N-1: 0]) is a thermometer code, the modulation frequency when the input time interval is constant. (modulation frequency)

If any N time digital signal MOD [N-1: 0] is input, then any given time interval is 1 /

/ 2N

비트의 써모 코드(thermometer code)에 해당하므로 N 비트의 디지털 신호(MOD[N-1:0])가 입력되는 임의의 정해진 시간 간격은 1/

/

이 된다.If the N-bit digital signal MOD [N-1: 0] is binary data rather than the thermometer code,

Since this corresponds to the bit's thermometer code, any given time interval at which the N-bit digital signal (MOD [N-1: 0]) is input is 1 /

Of

Becomes

The oscillator 340 used in the spread spectrum clock generator 300 is an oscillator whose frequency is adjusted by an analog voltage control signal V _CTRL and a digital signal MOD [N-1: 0]. Technologies such as Sangjin Byun, Jyung Chan Lee, Jae Hoon Shim, Kwangjoon Kim, and Hyun-Kyu Yu, “A 10 Gb / s CMOS CDR and DEMUX IC with a quarter-rate linear phase detector,” IEEE Journal of Solid-State Circuits, vol. 41, no. 11, pp. 2566-2576, November, 2006).

However, the oscillator of the prior art uses the digital signal LCVCO_BAND [1: 0 because the digital signal LCVCO_BAND [1: 0] is not used for frequency modulation but is used for coarse tuning to select a frequency band. Once the value of]) is determined, it is fixed to the value, which is different from the present invention. That is, in this case, the digital signal LCVCO_BAND [1: 0] is not used for frequency modulation of the output clock signal.

4 is a block diagram showing another embodiment of a spread spectrum clock generator according to the present invention, when compared to the spread spectrum clock generator 300 of FIG. 3, three clock dividers 350, 360, and 370 are shown. And a spread spectrum modulator 380 for generating N-bit digital signals MOD [N-1: 0].

The clock divider (/ K) 350 divides the input clock signal CLK _IN at the required frequency and outputs the signal to one input terminal of the phase frequency detector 310.

The clock divider (/ R) 360 divides the output clock signal CLK _{OUT to} output a signal having the same frequency as that of the clock divider 350 to the other input terminal of the phase frequency detector 310. Play a role.

The clock divider (/ M) 370 divides the input clock signal CLK _IN to generate a clock frequency required by the spread spectrum modulator 380.

Accordingly, the divided values K, R, and M of the clock dividers 350, 360, and 370 become natural numbers of 1 or more, respectively, and each of these values is a modulation frequency of the spread spectrum clock generator 300. (modulation frequency), loop bandwidth (loop bandwidth) and the like is determined in relation.

Spread spectrum modulator 380 is a modulator that generates N bits of digital signal MOD [N-1: 0].

The frequency of the clock signal input from the spread spectrum modulator 380 is a time interval at which the N-bit digital signal MOD [N-1: 0] to be generated is a thermometer code. In this case, 2N times the modulation frequency (modulation frequency).

비트의 써모미터 코드에 해당하므로, 변조 주파수(modulatioin frequency)의

배가 된다.In addition, the frequency of the clock signal received from the spread spectrum modulator 380 is, when the N-bit digital signal MOD [N-1: 0] to be generated is binary data instead of a thermometer code.

Corresponds to the bit's thermometer code,

It is doubled.

Meanwhile, FIG. 5A illustrates the output clock signal CLK _OUT by the analog voltage control signal V _CTRL and the digital signal MOD [N-1: 0] applied to the spread spectrum clock generator 300 according to the present invention. A detailed block diagram showing an implementation of the oscillator 340 in which the frequency is adjusted, as shown here, is composed of a plurality of delay cells 501-505 connected in series.

5B is a detailed circuit diagram of an arbitrary delay cell (for example, 503) among the delay cells 501 to 505 having the same configuration as that of FIG. 5A. Referring to this, the operation of the oscillator 340 will be described below.

The oscillator 340 is composed of P (where P is a natural number of 3 or more) serially connected delay cells to output an output clock signal CLK _OUT of a frequency corresponding to each of these delays. This is because the sum of the phase difference of each delay cell must be ± 180 degrees to operate as an oscillator. In the embodiment of FIG. 5A, the oscillator 340 is implemented with five delay cells 501-505.

As described above, since the total number of delay cells is P, and the number of capacitors that can be connected in parallel to the basic capacitor is L, the total number of capacitors that can be combined in the entire oscillator 340 is P * L. N = P * L since the N bit digital signal MOD [N-1: 0] is used to adjust the combination of capacitors.

= P * L이 된다. 이와 같은 경우에는 N 비트의 디지털 신호(MOD[N-1:0])가 바이너리/써모미터 코드 변환기를 통해 각 딜레이셀에 공급되도록 하여야 한다.If the N bit digital signal (MOD [N-1: 0]) is binary data instead of the thermometer code

= P * L In this case, N-bit digital signals (MOD [N-1: 0]) must be supplied to each delay cell through a binary / thermometer code converter.

Each of the delay cells 501 to 505 is configured to provide an inverter I1 for inverting and outputting an input clock signal, a MOS transistor MT1-MT4 operating as a current source source of the inverter I1, and an output terminal of the inverter I1. It includes a basic capacitor (C0) connected and a plurality of capacitors and MOS transistor (C1, M1-CL, ML) connected in series, the MOS transistor (MT1-MT4) by the analog voltage control signal (V _CTRL ) Driving is controlled and the MOS transistors M1-ML are turned on or off by the N-bit digital signal MOD [N-1: 0].

The inverter I1 inverts and outputs an input clock signal. As the current source thereof, the MOS transistors MT1-MT4 are used. However, the analog voltage control signal V _CTRL is supplied to the gates of the MOS transistors MT3 and MT4.

Therefore, the amount of current supplied to the basic capacitor C0 and the capacitors C1-CL is controlled by the analog voltage control signal V _CTRL . For example, when the analog voltage control signal V _CTRL is increased, the amount of current supplied to the basic capacitor C0 and the capacitors C1-CL increases, thereby correspondingly to the frequency of the output clock signal CLK _OUT . Is increased.

The basic capacitor C0 is connected between the output terminal of the inverter I1 and the ground terminal, and capacitors and MOS transistors C1, M1, C2, M2 connected in series between the connection point and the ground terminal. And (CL, ML) are connected in parallel, and L (where L is a natural number of 1 or more) bits of the N bits of the digital signals MOD [N-1: 0] is the MOS transistor M1-. ML) is supplied to the gate.

Accordingly, the on-off of the MOS transistors M1-ML is determined by the L bit digital signal, thereby determining the number of capacitors connected in parallel with the basic capacitor C0 among the capacitors C1-CL. .

For example, when the least significant bit is '1' among the L bit digital signals supplied to the delay cell 503 of the third stage and all the remaining bits are '0', the first of the MOS transistors M1-ML is determined. Only the MOS transistor M1 is turned on and the remaining MOS transistors M2-ML are turned off. Accordingly, the capacitor C1 is connected in parallel to the basic capacitor C0.

As the number of capacitors C1-CL connected to the basic capacitor C0 in parallel increases, the capacity of the total capacitors increases, so that the charging time becomes longer. Accordingly, the frequency of the output clock signal CLK _OUT also corresponds. Is greatly reduced.

6A illustrates the output clock signal CLK _OUT by the analog voltage control signal V _CTRL and the digital signal MOD [N-1: 0] applied to the spread spectrum clock generator 300 according to the present invention. A detailed block diagram showing another embodiment of the oscillator 340 in which the frequency is adjusted, as shown here, which consists of a plurality of LC oscillators 601-605 connected in series.

FIG. 6B is a detailed circuit diagram of an arbitrary LC oscillator (eg, 603) among the LC oscillators 601-605 having the same configuration of FIG. 6A. Referring to this, the operation of the oscillator 340 will be described below.

In the present embodiment, the oscillator 340 is composed of P (where P is one or more natural numbers) serially connected LC oscillators and outputs an output clock signal CLK _OUT of a frequency corresponding to each of these oscillations. The reason why P is set to 1 or more is that each LC oscillator operates as an oscillator alone, and P = 2, 3,... This is because it operates as an oscillator even if it is configured as a ring as shown. 6A illustrates an example in which the oscillator 340 is implemented with five LC oscillators 601-605.

The total number of LC oscillators constituting the oscillator 340 is P, and the number of capacitors that can be connected to the left and right sides of the varactor by the turn-on operation of the MOS transistor in each LC oscillator is L in total. The total number of possible capacitors is P * L. Since N bits of the digital signal MOD [N-1: 0] are used to adjust the number of the connected capacitors, it can be seen that N = P * L as shown in FIG. 6A.

= P * L 이 됨을 알 수 있으며, 이 경우에는 N 비트의 디지털 신호(MOD[N-1:0])가 바이너리/써모미터 코드 변환기를 통해 각 딜레이셀에 공급되도록 하여야 한다.If the N bit digital signal (MOD [N-1: 0]) is binary data and not a thermometer code

= P * L. In this case, N bits of digital signal (MOD [N-1: 0]) must be supplied to each delay cell through a binary / thermometer code converter.

Each of the LC oscillators 601-605 is an inductor L1, L2, and varistor Cr constituting a basic LC resonant circuit, and a MOS transistor M1-M4 for supplying driving power to the LC resonant circuit. And MOS transistors M5 and M6 constituting a current source, capacitors and MOS transistors CL ₁ and ML ₁ connected in series with each other and connected in parallel between one terminal of the selector Cr and the ground terminal. (CL _L , ML _L ), capacitors and MOS transistors CR ₁ , MR ₁ ,... Which are connected in series with each other and are connected in parallel between the other terminal of the varistor Cr and a ground terminal. , It is composed of _(L CR, MR _L).

Here, the analog voltage control signal V _CTRL is supplied as a control signal of the selector Cr, and L (where L is a natural number of 1 or more) among the N-bit digital signals MOD [N-1: 0]. the digital signal bit is supplied to the gate of the MOS transistor _{(ML 1 ..., ML L)} , (MR 1 ..., MR L).

The analog voltage control signal V _CTRL is supplied as a control signal of the selector Cr of each of the LC oscillators 601-605 so that its capacitance is adjusted. Accordingly, the oscillation frequency of the basic LC resonant circuit composed of inductors L1, L2, and varactor Cr is adjusted in each LC oscillator 601-605 by the analog voltage control signal V _CTRL . Thus, the frequency of the output clock signal CLK _OUT of the oscillator 340 is adjusted.

Is supplied to the gate of a digital signal of L-bit wherein the MOS transistor _{(ML 1 ..., ML L)} , (MR 1 ..., MR L) of: Separately, the N-bit digital signal (MOD [0 N-1] ) Their turn-on operation is controlled. Accordingly, one of the capacitors CL ₁ ,..., CL _L , and (CR ₁ ,..., CR _L ) is connected between one terminal and the ground terminal of the selector Cr by the digital signal of the L bit, and the other terminal. The number of capacitors connected in parallel between the ground terminals is determined, thereby adjusting the oscillation frequency of the LC resonant circuit in each of the LC oscillators 601-605, thereby outputting the signal clock signal CLK of the oscillator 340. The frequency of _OUT is adjusted.

7 is a graph showing simulation results of a spread spectrum clock generator 300 operating as described above.

Here, the X axis is the time axis, and the Y axis is the frequency of the spread spectrum modulated output clock signal CLK _OUT generated by the spread spectrum clock generator 300. As can be seen, it can be seen that the frequency of the output clock signal CLK _OUT is finely modulated digitally according to a triangular modulation profile with time.

In particular, the simulation results showed that the sensitivity of the frequency modulation ratio (modulation ratio) was -1.3% / 100 ℃ and the sensitivity of the frequency modulation ratio (modulation ratio) was 7.02% / V. All of the sensitivity was very small. The reason is that the spread spectrum clock generator 300 of the present invention, which modulates the N bits of the digital signal MOD [N-1: 0], uses a total of N MOS transistors operating as a switch. -1: 0]), and the number of capacitors connected in parallel is determined thereby to determine the total capacitance accordingly, thereby determining the delay time of the clock signal or the LC resonant frequency so that the output clock accordingly This is because the frequency of the signal CLK _OUT is modulated.

The frequency modulation ratio is the ratio of the basic capacitor C0 and the relatively low capacitance capacitors C1-CL connected in parallel to it as in FIG. 5B, or the varer Cr as in FIG. 6B. It is determined by the ratio of the relatively small capacitance capacitors CL ₁ ,..., CL _L , and (CR ₁ ,..., CR _L ) connected in parallel to both terminals thereof.

The ratio of the capacitor values is hardly affected by temperature, power supply voltage, or PVT variation when implemented with a MiM capacitor. Therefore, the frequency modulation ratio of the spread spectrum clock generator 300 according to the present invention is not significantly affected by changes in ambient temperature, power supply voltage, or process.

The spread spectrum clock generator 300 may be used to generate a frequency modulated signal such as frequency modulation (FM) or frequency shift keying (FSK) in various wired and wireless communication fields in addition to generating a spread spectrum clock.

Although the preferred embodiment of the present invention has been described in detail above, the scope of the present invention is not limited thereto, and may be implemented in various embodiments based on the basic concept of the present invention defined in the following claims. Such embodiments are also within the scope of the present invention.

310: phase frequency detector 320: charge pump
330 loop filter 340 oscillator
350-370: Clock divider 501-505: Delay cell
601-605: LC Oscillator

Claims (12)

A phase frequency detector for comparing a phase and a frequency of an input clock signal and an output clock signal fed back from the oscillator and outputting an up / down signal accordingly;
A charge pump generating a current corresponding to an up / down signal input from the phase frequency detector;
A loop filter for outputting an analog voltage control signal corresponding to the amount of current input from the charge pump;
And an oscillator for adjusting a center frequency of the output clock signal according to the analog voltage control signal and spread spectrum modulating the frequency of the output clock signal according to an N bit digital signal.
The spread spectrum clock generator of claim 1, wherein the oscillator receives the N-bit digital signal at a predetermined time interval.
The spread spectrum clock generator of claim 1, wherein the oscillator is a ring type oscillator, and is configured of the analog voltage control signal and P delay cells whose delay time is adjusted by an L bit of an N bit digital signal. .
4. The spread spectrum clock generator of claim 3 wherein N, L and P are natural numbers having a relationship of N = L * P.
The method of claim 3, wherein the delay cell
An inverter for inverting and outputting an input clock signal;
A plurality of MOS transistors operating as current source sources of the inverter;
A plurality of capacitors including a basic capacitor connected to an output terminal of the inverter, a plurality of capacitors and a MOS transistor connected in series, and the plurality of MOS transistors operating as a current source source of the inverter are controlled by an analog voltage control signal, and A spread spectrum clock generator, characterized in that the N-bit digital signal is supplied to the gates of a plurality of MOS transistors connected in series with a capacitor.
6. The spread spectrum clock generator of claim 5, wherein the capacitance of the plurality of capacitors is less than the capacitance of the basic capacitor.
The spread spectrum clock as claimed in claim 1, wherein the oscillator is a ring type LC oscillator comprising the analog voltage control signal and P LC oscillators whose resonance frequency is adjusted by L bits of the N bits of digital signals. generator.
8. The spread spectrum clock generator of claim 7, wherein N, L and P are natural numbers having a relationship of N = L * P.
The method of claim 7, wherein the LC oscillator
Inductors L1, L2 and varistor Cr constituting a basic LC resonant circuit;
MOS transistors M1-M4 for supplying driving power to the LC resonant circuit, and MOS transistors M5 and M6 constituting a current source;
Capacitors and MOS transistors CL ₁ and ML ₁ connected in series with each other and connected in parallel between one terminal of the varistor Cr and a ground terminal. , (CL _L , ML _L );
Capacitors and MOS transistors CR ₁ and MR ₁ connected in series with each other and connected in parallel between the other terminal and the ground terminal of the varistor Cr; And (CR _L , MR _L ), and the analog voltage control signal V _CTRL is supplied as a control signal of the selector Cr, and the N-bit digital signal MOD [N-1: 0] Wherein the L-bit digital signal is configured to be supplied to the gates of the MOS transistors (ML ₁ ..., ML _L ) and (MR ₁ ..., MR _L ), respectively.
4. The spread spectrum clock generator of claim 1, wherein the spread spectrum clock generator generates a frequency modulated signal of FM or FSK.
A first clock divider for dividing the input clock signal at the required frequency and outputting the input clock signal to one input terminal of the phase frequency detector;
A second clock divider for dividing an output clock signal to output a signal having the same frequency as that of the first clock divider to the other input terminal of the phase frequency detector;
A third clock divider for dividing the input clock signal to generate a clock frequency required by a spread spectrum modulator;
A spread spectrum modulator for generating an N bit digital signal using a clock signal input from the third clock divider;
A phase frequency detector for comparing a phase and a frequency of a clock signal input from the first and second clock dividers and outputting an up / down signal accordingly;
A charge pump generating a current corresponding to an up / down signal input from the phase frequency detector;
A loop filter for outputting an analog voltage control signal corresponding to the amount of current input from the charge pump;
And an oscillator configured to adjust a center frequency of the output clock signal according to the analog voltage control signal and spread spectrum modulate the frequency of the output clock signal according to the N-bit digital signal.
12. The spread spectrum clock generator of claim 11, wherein the division value of the first to third clock dividers is one or more natural numbers and is determined by a modulation frequency and a loop bandwidth of the spread spectrum clock generator.

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