KR20100080159A - Semiconductor device and method for manufacturing thereof - Google Patents

Semiconductor device and method for manufacturing thereof Download PDF

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Publication number
KR20100080159A
KR20100080159A KR1020080138801A KR20080138801A KR20100080159A KR 20100080159 A KR20100080159 A KR 20100080159A KR 1020080138801 A KR1020080138801 A KR 1020080138801A KR 20080138801 A KR20080138801 A KR 20080138801A KR 20100080159 A KR20100080159 A KR 20100080159A
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South Korea
Prior art keywords
diffusion barrier
layer
diffusion
barrier layer
gate
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KR1020080138801A
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Korean (ko)
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선종원
신희재
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주식회사 동부하이텍
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Priority to KR1020080138801A priority Critical patent/KR20100080159A/en
Publication of KR20100080159A publication Critical patent/KR20100080159A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Ceramic Engineering (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

According to one or more exemplary embodiments, a method of manufacturing a semiconductor device may include preparing a first conductive semiconductor substrate; And forming a diffusion barrier layer by performing an epitaxial process on the first conductive semiconductor substrate, wherein the diffusion barrier layer is a SiC epitaxial layer.

Description

Semiconductor device and method for manufacturing thereof

The embodiment relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same that can prevent diffusion of impurities injected into a silicon wafer.

Recently, as the integration of semiconductor devices is advanced, the gates, channels, and sources / drains of transistors are also reduced. Accordingly, undesired electrical characteristics of the semiconductor device may appear.

For example, as the thickness of the gate insulating layer becomes thinner, gate patterning occurs due to diffusion of boron dopant (B +) from the gate electrode made of PMOS polysilicon, and thus leakage current of the field effect transistor. ). In addition, a punch through occurs due to the diffusion of the boron dopant from the source / drain formation, thereby lowering the reliability of the device.

This is because a lot of silicon interstitial produced by the ion implantation process is injected into the silicon substrate, which greatly increases the diffusivity of the ions and thus the diffusion of impurity ions. Is called Transient Enhanced Diffusion (TED).

The TED phenomenon occurs in boron, and when the boron ion is injected into the PMOS device, the diffusion depth of the boron ion is increased by the interstitial inside the silicon substrate, thereby integrating the device. And a problem of lowering the electrical characteristics of the device.

The embodiment provides a semiconductor device and a method of manufacturing the same, which can effectively reduce interstitial silicon by growing a SiC epitaxial layer on a semiconductor substrate through carbon atoms present in the SiC epitaxial layer.

A method of manufacturing a semiconductor device according to the first embodiment includes preparing a first conductive semiconductor substrate; And forming a diffusion barrier layer by performing an epitaxial process on the first conductive semiconductor substrate, wherein the diffusion barrier layer is a SiC epitaxial layer.

A method of manufacturing a semiconductor device according to a second embodiment includes preparing a first conductive semiconductor substrate; Forming a first conductive epitaxial layer on the first conductive semiconductor substrate; Implanting diffusion preventing ions into the first conductivity type epitaxial layer to form a diffusion prevention layer; And forming an diffusion barrier layer by performing an annealing process on the diffusion barrier layer.

A semiconductor device according to a third embodiment includes a diffusion barrier epitaxial layer formed on a first conductivity type semiconductor substrate; A gate formed on the diffusion barrier layer; A gate formed on the diffusion barrier layer to be aligned with both sides of the gate; An LDD region formed in a shallow region of the diffusion barrier layer so as to be aligned at both sides of the gate; Spacers formed on both sidewalls of the gate; And a source and a drain formed in a deep region of the diffusion barrier layer so as to be aligned at both sides of the spacer.

According to the embodiment, by forming the SiC diffusion barrier layer on the semiconductor substrate it is possible to reduce the interstitial generated by ion implantation through the carbon atoms present in the SiC diffusion barrier layer. Accordingly, it is possible to remove interstitial that acts as a source of TED (Transient Enhanced Diffusion) of p-type impurities.

In addition, by reducing the diffusion depth of impurities such as boron used as a source / drain implantation of the PMOS transistor and dopant of LDD implantation, the shallow junction ( shallow junctions).

A unit pixel of the image sensor and a method of manufacturing the same according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where described as being formed "on / over" of each layer, the on / over may be directly or through another layer ( indirectly) includes everything formed.

A method of manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS. 1 and 2.

1 and 2, an epitaxial process is performed on the first conductive semiconductor substrate (Si-sub) 100.

The first conductive semiconductor substrate 100 may be a single crystal or polycrystalline silicon substrate, and may be a substrate doped with p-type impurities or n-type impurities. For the description of the embodiment, the first conductivity type will be described based on the case of n type. In addition, the crystallographic orientation of the first conductivity-type semiconductor substrate may have a flat surface (1,0,0).

The epitaxial process is to grow a low concentration silicon layer on a high concentration silicon substrate. The reason for using the epi layer is first, because there is a low concentration n-type epi layer, so the depletion region of the device is increased. You can increase it deeply. Second, having a high concentration of silicon substrate under the epi layer can reduce random diffusion of electrons because the electrons recombine quickly before electrons diffuse into neighboring unit cells.

A diffusion barrier epitaxial layer 110 is formed on the first conductive semiconductor substrate 100 by the epitaxial process. The diffusion barrier epitaxial layer 110 may be formed of a SiC epitaxial layer (SiC-epi). The diffusion barrier epitaxial layer 110 is formed on the first conductive semiconductor substrate 100 to reduce interstitial, which is an invasive site serving as a source of a transient enhanced diffusion (TED). have. The diffusion barrier epitaxial layer 110 may adjust its thickness according to the purpose of the device, for example, may be formed to a thickness of 01. ~ 1.0 × ㎛.

Specifically, the anti-diffusion epitaxial layer 110 uses an epitaxial process at a temperature of 800 to 1200 ° C. using a single chamber reactor and using SiH 4 and C 3 H 8 as a source gas. It can be formed by going.

Interstitial inter-silicon lattice through the carbon atoms present in the SiC epitaxial layer (SiC-epi) by growing a SiC epitaxial layer (SiC-epi) on the first conductive semiconductor substrate 100 (interstitial) can be effectively reduced.

This is because the carbon atoms present in the substitution type sites of the SiC epitaxial layer (SiC-epi) react with the interstitial generated by ion implantation and change into invasive atoms.

That is, carbon (C) ions are located and fixed at interstitial, which is an invasive site in the polycrystalline silicon lattice (C s + I = C 1 ).

As the carbon (C) ions are fixed to the interstitial in the silicon lattice, boron, which is a p-type impurity of a second conductivity type, that is, an ion for forming an LDD structure implanted into the SiC epitaxial layer (SiC-epi) (B) The diffusion of ions can be prevented. The interstitial in the silicon lattice is a space smaller in size than the silicon atom between silicon atoms and is diffused along the interstitial when atoms smaller than the silicon atom are injected into the silicon lattice. Therefore, when the boron ions are implanted in the silicon lattice in a fixed state by injecting carbon (C) ions, which are diffusion preventing ions having a size similar to that of the boron atoms, in the silicon lattice in advance, The securing of, i.e., the securing of interstitial is limited, thereby preventing the boron ions injected in the subsequent process from being diffused into the channel region or other regions.

As described above, an SiC epitaxial layer, which is an anti-diffusion epitaxial layer, is formed on the first conductive semiconductor substrate so that boron TED, which is a p-type impurity, is used as a source of interstitial as a source. The concentration can be greatly reduced.

3 is a cross-sectional view illustrating that a transistor is formed in the diffusion barrier epitaxial layer 110 formed on the first conductive semiconductor substrate 100 according to the first embodiment. For example, the transistor may be a PMOS transistor.

Referring to FIG. 3, a diffusion barrier epitaxial layer 110 is formed on the first conductive semiconductor substrate 100 by an epitaxial process. The diffusion barrier epitaxial layer 110 is a SiC epitaxial layer (SiC-epi). Since the diffusion prevention epitaxial layer 110 is formed in the same manner as in FIGS. 1 and 2, it will be omitted.

An isolation layer 120 is formed on the diffusion preventing epitaxial layer 110. The device isolation layer 120 is to define an active region of the diffusion barrier epitaxial layer 110 and may be formed by an STI process.

Although not shown, a Vt channel region of a PMOS transistor may be formed on a surface of the diffusion barrier epitaxial layer 110.

The gate 130 is formed on the diffusion barrier epitaxial layer 110. The gate 130 may be formed by depositing a gate oxide layer and a gate conductive layer on the diffusion barrier layer 110 and then selectively patterning the gate oxide layer and the gate conductive layer. In this case, the gate conductive film may be a polysilicon, a metal, or a laminated film of polysilicon and a metal.

Next, a lightly doped drain (LDD) region 150 is formed inside the diffusion barrier layer by ion implantation of a p-type impurity (p−), which is a low concentration dopant using the gate 130 as a mask. In addition, an insulating layer is deposited on the entire surface of the gate 130 and etched to form a spacer 140 contacting both sidewalls of the gate. The p-type impurity (p +), which is a high concentration dopant, is ion implanted using the gate 130 and the spacer 140 as a mask to form a source / drain region 160 in contact with the LDD region 150. For example, the dopant for forming the LDD region 150 and the source / drain region 160 may be formed of boron ions.

The LDD region 150 and the source / drain region 160 are formed by injecting boron (B) ions into the diffusion barrier epitaxial layer 110 formed of the SiC epitaxial layer (SiC-epi). Since the SiC-epi restricts the diffusion of boron ions, it is possible to implement a microfile of the LDD structure, the source and the drain region.

Accordingly, a shallow junction can be formed by reducing the diffusion depth of boron ions used as dopants such as source / drain ion implantation and LDD ion implantation of a PMOS transistor.

4 to 5 illustrate a method of manufacturing a semiconductor device according to the second embodiment.

4 and 5, an epitaxial process is performed on the first conductive semiconductor substrate (Si-sub) 200.

The first conductive semiconductor substrate 200 may be a single crystal or polycrystalline silicon substrate, and may be a substrate doped with p-type impurities or n-type impurities. For the description of the embodiment, the first conductivity type will be described based on the case of n type (n ++). In addition, the crystallographic orientation of the first conductivity-type semiconductor substrate 200 may have a flat surface (1,0,0).

A first epitaxial process is performed on the first conductive semiconductor substrate 200 to form a first conductive epitaxial layer (Si-epi) 210. The first conductivity type epi layer 210 may be a low concentration n-type epi layer (n-epi).

Next, a diffusion barrier epitaxial layer 220 is formed by performing a second epitaxial process on the first conductive epitaxial layer 210. The diffusion barrier epitaxial layer 220 may be formed of a SiC epitaxial layer (SiC-epi). The diffusion barrier epitaxial layer 220 is formed on the first conductive epitaxial layer 210 to reduce interstitial, which is an invasive site serving as a source of transient enhanced diffusion (TED). have. The diffusion barrier epitaxial layer 220 may adjust its thickness according to the purpose of the device, for example, may be formed to a thickness of 01. ~ 1.0 × ㎛.

Specifically, the diffusion barrier epitaxial layer 220 uses an epitaxial process at a temperature of 800 to 1200 ° C. using a single chamber reactor and SiH 4 and C 3 H 8 as a source gas. It can be formed by going.

As described above, a SiC epitaxial layer (SiC-epi), which is a diffusion preventing epitaxial layer 220, is formed on the first conductive semiconductor substrate 200, so that boron TED (boron) transient enhanced diffusion (PED), which is a p-type impurity, is formed. It is possible to significantly reduce the concentration of interstitial that serves as a source.

Although not shown, a PMOS transistor may be formed in the diffusion barrier epitaxial layer 220 of the first conductivity type semiconductor substrate 200.

6 to 8 illustrate a method of manufacturing a semiconductor device according to the third embodiment.

Referring to FIG. 6, a first conductive epitaxial layer 310 is formed on the first conductive semiconductor substrate 300.

The first conductive semiconductor substrate 300 may be a single crystal or polycrystalline silicon substrate, and may be a substrate doped with p-type impurities or n-type impurities. For the description of the embodiment, the first conductivity type will be described based on the case of n type (n ++). In addition, the crystallographic orientation of the first conductivity-type semiconductor substrate 300 may have a flat surface (1,0,0).

The first conductive epitaxial layer 310 may be formed by performing an epitaxial process on the first conductive semiconductor substrate 300. For example, the first conductivity type epi layer 310 may be a low concentration n-type epi layer (n-epi).

Referring to FIG. 7, the diffusion barrier layer 320 is formed on the first conductive epitaxial layer 310. The diffusion barrier layer 320 may be formed of a SiC layer.

The diffusion barrier layer 320 may be formed by ion implanting carbon ions into the first conductive epitaxial layer 310. For example, the ion implantation process for forming the diffusion barrier layer 320 may be performed by adjusting Rp (Projection Range) to 0.1 ~ 1.0㎛, implanting carbon (C) ions with ion implantation energy of 100 ~ 500keV. have.

Referring to FIG. 8, a diffusion barrier epitaxial layer 320 is formed on the first conductivity type epitaxial layer 310. The diffusion barrier epitaxial layer 320 may be formed by an annealing process on the diffusion barrier layer 320. That is, the diffusion barrier epitaxial layer 320 is formed by diffusing carbon ions of the diffusion barrier layer 320 through the annealing process. For example, the diffusion barrier epitaxial layer 320 may be formed by annealing at about 1000 to 1100 ° C. using a rapid thermal process (RTP) device.

Accordingly, the diffusion barrier epitaxial layer 320 formed of SiC is formed on the first conductive semiconductor substrate 300 to serve as a source of boron atom's transient enhanced diffusion (TED). It is possible to reduce the concentration of.

Although not shown, an ion implantation process for the Vt channel, the LDD region, and the source / drain junction of the PMOS transistor may be performed on the diffusion barrier epitaxial layer 320.

The above-described embodiments are not limited to the above-described embodiments and drawings, and various substitutions, modifications, and changes can be made without departing from the spirit and scope of the present invention. It will be clear to those who have it.

1 to 2 are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment.

FIG. 3 is a diagram illustrating a transistor formed using the semiconductor substrate illustrated in FIG. 2.

4 to 5 are views illustrating a manufacturing process of the semiconductor device according to the second embodiment.

6 to 8 are views illustrating a manufacturing process of the semiconductor device according to the third embodiment.

Claims (11)

Preparing a first conductivity type semiconductor substrate; And Performing an epitaxial process on the first conductive semiconductor substrate to form a diffusion barrier epitaxial layer, The diffusion preventing epi layer is a method for manufacturing a semiconductor device, characterized in that the SiC epitaxial layer. The method of claim 1, The diffusion preventing epi layer is a method of manufacturing a semiconductor device, characterized in that the epitaxial growth process using the SiH 4 and C 3 H 8 as a source gas. The method of claim 1, The method of claim 1, further comprising forming a first conductive epitaxial layer on the first conductive semiconductor substrate. The method of claim 1, After forming the diffusion barrier layer, Forming a gate on the diffusion barrier layer; Forming a shallow region LDD region of the diffusion barrier layer so as to be aligned at both sides of the gate; Forming spacers on both side walls of the gate; And Forming a source and a drain in a deep region of the diffusion barrier layer so as to be aligned at both sides of the spacer. The method of claim 4, wherein The LDD region and the source / drain are formed by ion implantation of p-type impurities. Preparing a first conductivity type semiconductor substrate; Forming a first conductive epitaxial layer on the first conductive semiconductor substrate; Implanting diffusion preventing ions into the first conductivity type epitaxial layer to form a diffusion prevention layer; And A method of manufacturing a semiconductor device comprising the step of annealing the diffusion barrier layer to form a diffusion barrier layer. The method of claim 6, The diffusion barrier layer is a semiconductor device manufacturing method, characterized in that formed by ion implanting carbon (carbon) ions into the first conductivity type epi layer. The method of claim 6, The diffusion preventing epi layer is a semiconductor device manufacturing method, characterized in that for performing an annealing process using a rapid thermal process (RTP) for the diffusion barrier layer. A diffusion barrier epitaxial layer formed on the first conductive semiconductor substrate; A gate formed on the diffusion barrier layer; A gate formed on the diffusion barrier layer to be aligned with both sides of the gate; An LDD region formed in a shallow region of the diffusion barrier layer so as to be aligned at both sides of the gate; Spacers formed on both sidewalls of the gate; And a source and a drain formed in a deep region of the diffusion barrier layer so as to be aligned at both sides of the spacer. 10. The method of claim 9, The diffusion preventing epi layer is a semiconductor device, characterized in that the SiC epitaxial layer. 10. The method of claim 9, And the LDD region and the source / drain are formed of p-type impurities.
KR1020080138801A 2008-12-31 2008-12-31 Semiconductor device and method for manufacturing thereof KR20100080159A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150118517A (en) * 2014-04-14 2015-10-22 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Dislocation stress memorization technique (dsmt) on epitaxial channel devices
US9425099B2 (en) 2014-01-16 2016-08-23 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial channel with a counter-halo implant to improve analog gain
US9525031B2 (en) 2014-03-13 2016-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial channel
US9553150B2 (en) 2014-01-16 2017-01-24 Taiwan Semiconductor Manufacturing Co., Ltd. Transistor design
US9768297B2 (en) 2014-01-16 2017-09-19 Taiwan Semiconductor Manufacturing Co., Ltd. Process design to improve transistor variations and performance

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9425099B2 (en) 2014-01-16 2016-08-23 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial channel with a counter-halo implant to improve analog gain
US9553150B2 (en) 2014-01-16 2017-01-24 Taiwan Semiconductor Manufacturing Co., Ltd. Transistor design
US9768297B2 (en) 2014-01-16 2017-09-19 Taiwan Semiconductor Manufacturing Co., Ltd. Process design to improve transistor variations and performance
US9899475B2 (en) 2014-01-16 2018-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial channel with a counter-halo implant to improve analog gain
US9525031B2 (en) 2014-03-13 2016-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial channel
KR20150118517A (en) * 2014-04-14 2015-10-22 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Dislocation stress memorization technique (dsmt) on epitaxial channel devices
US9419136B2 (en) 2014-04-14 2016-08-16 Taiwan Semiconductor Manufacturing Co., Ltd. Dislocation stress memorization technique (DSMT) on epitaxial channel devices
US9502559B2 (en) 2014-04-14 2016-11-22 Taiwan Semiconductor Manufacturing Co., Ltd. Dislocation stress memorization technique (DSMT) on epitaxial channel devices
US9899517B2 (en) 2014-04-14 2018-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Dislocation stress memorization technique (DSMT) on epitaxial channel devices

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