KR20100042423A - Method for forming a pattern in the semiconductor device - Google Patents

Method for forming a pattern in the semiconductor device Download PDF

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Publication number
KR20100042423A
KR20100042423A KR1020080101565A KR20080101565A KR20100042423A KR 20100042423 A KR20100042423 A KR 20100042423A KR 1020080101565 A KR1020080101565 A KR 1020080101565A KR 20080101565 A KR20080101565 A KR 20080101565A KR 20100042423 A KR20100042423 A KR 20100042423A
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KR
South Korea
Prior art keywords
pattern
hard mask
forming
layer
spacer
Prior art date
Application number
KR1020080101565A
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Korean (ko)
Inventor
구선영
Original Assignee
주식회사 하이닉스반도체
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Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020080101565A priority Critical patent/KR20100042423A/en
Publication of KR20100042423A publication Critical patent/KR20100042423A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/708—Mark formation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H01L2223/5446—Located in scribe lines

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

The present invention relates to a method of forming a pattern of a semiconductor device, by preventing the spacer layer formed on the sidewalls of the hard mask pattern of the scribe lane region from being removed, so that the pattern can be formed without a phenomenon that the pattern collapses or is lifted during the subsequent patterning process. A technique for providing frame components with improved reliability is disclosed.

Description

METHODS FOR FORMING A PATTERN IN THE SEMICONDUCTOR DEVICE

The present invention relates to a method of forming a pattern of a semiconductor device. In particular, the present invention relates to a method of forming a frame formed in the scribe lane region when the SPT process is applied.

As semiconductor devices are highly integrated, the size and pitch of patterns for implementing circuits constituting semiconductor devices are gradually decreasing.

As a result, the photo processing technology in the machining process refines the mask design to properly control the amount of light emitted through the mask, develop a new photoresist, and develop a scanner using a high numerical aperture lens. By overcoming efforts to develop modified masks, the technical limitations of semiconductor device manufacturing apparatuses have been overcome.

However, due to limitations in exposure and resolution ability that proceed with current light sources, for example, KrF, ArF, etc., it is difficult to form a width and an interval of a desired pattern.

Accordingly, various studies for forming a photoresist pattern having a size and an interval of a fine pattern have been continued.

One method is a double patterning technology (DPT) method in which a pattern is formed by performing two photographic processes.

The DPT method uses a DE2T (Double Expose Etch Technology) method that exposes and etches a pattern having twice the period of the pattern period, and then exposes and etches a second pattern having the same double period between them, and a spacer. There is a SPT (Spacer Patterning Technology) method of forming a pattern.

The SPT method includes positive SPT (Positive Spacer Patterning Technology) in which a portion where a spacer is formed is a pattern, and negative SPT (Negative Spacer Patterning Technology) in which a portion where a spacer is formed is a space.

In this case, the negative SPT cannot be formed as a frame structure applied when a single exposure mask is used or a frame structure applied in a positive SPT.

1A to 1D illustrate a pattern method method according to a negative SPT process, which illustrates a cell region I in which a desired pattern is formed and a scribe lane region II in which a frame configuration is formed.

Referring to FIG. 1A, the etched layer 110 is formed on the semiconductor substrate 100, and the hard mask pattern 120 is formed on the etched layer 110. The hard mask pattern 120 pitch of the cell region I is formed to be twice the pitch of the target pattern.

Here, although the hard mask pattern 120 formed in the scribe lane area II is illustrated as one pattern, the hard mask pattern 120 may include an overlay vernier, an alignment key, and a die fit target according to a situation. Or it may be formed in the form of an open box.

Referring to FIG. 1B, a spacer layer 130 is deposited on the hard mask pattern 120 and the etched layer 110. The spacer layer 130 is formed of an oxide-based material.

Referring to FIG. 1C, the gap fill layer 140 is formed to completely fill the space between the hard mask patterns 120 of the cell region I. Here, the gap fill film 140 is formed of a polysilicon layer. At this time, in the scribe lane region II, since the space between the hard mask patterns 120 is wide, the gap fill layer 140 is not completely filled, and is deposited only on the sidewall of the hard mask pattern 120.

Referring to FIG. 1D, the spacer layer 130 exposed by an etch-back process is removed. That is, the spacer layer 130 on the top and sidewalls of the hard mask pattern 120 is removed, and the spacer layer 130 under the gap fill layer 140 is not removed.

In this case, since the gap fill layer 140 is deposited only on the sidewalls of the hard mask pattern 120 in the scribe lane region II, the spacer layer 130 on the etched layer 110 exposed by the gap fill layer 140 is also removed. .

Next, after removing the spacer layer 130, the etching target layer 110 is etched using the gap fill layer 140 and the hard mask pattern 120 as an etching mask to form the etching target layer pattern 110a.

As described above, in the case of forming a frame structure by removing the spacer layer to form a space, the etched layer pattern is formed to have a high aspect ratio such as 'A' of FIG. 1D and these patterns are collapsed or lifted ( There is a problem that the particles act as particles.

The present invention seeks to improve the characteristics of the frame configuration by preventing the spacers of the pattern sidewalls from being removed in the negative SPT process.

The method of forming a pattern of a semiconductor device according to the present invention

Forming an etched layer on the substrate of the cell region and the scribe lane region, forming a hard mask pattern on the etched layer, forming a spacer on the sidewall of the hard mask pattern, and forming a hard mask on the scribe lane region Forming a photoresist pattern on the pattern and the spacer, removing the spacer of the cell region, and etching the etched layer using the hard mask pattern having the spacer as an etch mask to form an etched layer pattern. Characterized in that it comprises a.

Here, the etched layer pattern is an overlay vernier, an alignment key, a die fit target or an open box, and the spacer is formed of an oxide layer, and the pattern forming method. Is characterized in that it is applied to the SPT process.

In addition, the pattern formation method of the semiconductor element of this invention is

Forming an etched layer on the substrate of the cell region and the scribe lane region, forming a hard mask pattern on the etched layer, forming a spacer on the sidewall of the hard mask pattern, and forming the hard mask on the cell region. Forming a gap fill layer filling the pattern, forming a photoresist pattern on the hard mask pattern and the spacer on the scribe lane region, and removing the spacer exposed on the cell region using the photoresist pattern as a mask Opening the gap fill layer and the hard mask pattern, and etching the etching layer using the gap fill layer and the hard mask pattern as an etch mask to form an etch layer pattern.

The pitch of the hard mask pattern of the cell region is formed to be twice the pitch of the target pattern, the gap fill layer is formed of a polysilicon layer, and the spacer is formed of an oxide film.

The etched layer pattern of the scribe lane region may be an overlay vernier, an alignment key, a die fit target, or an open box.

The pattern forming method of the semiconductor device according to the present invention does not remove the spacer layer formed on the sidewalls of the hard mask pattern of the scribe lane region, so that the pattern can be formed without pattern collapse or pattern lifting during the subsequent patterning process. Thus, frame configurations with improved reliability can be formed.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

2A to 2F are cross-sectional views illustrating a method of forming a pattern of a semiconductor device according to the present invention, and show a cell region I in which a desired pattern is formed and a scribe lane region II in which a frame structure is formed.

Referring to FIG. 2A, an etched layer 210 is formed on the semiconductor substrate 200, and a hard mask pattern 120 is formed on the etched layer 210. The hard mask pattern 120 pitch of the cell region I is formed to be twice the pitch of the target pattern.

Here, although the hard mask pattern 120 formed in the scribe lane area II is illustrated as one pattern, the hard mask pattern 120 may include an overlay vernier, an alignment key, and a die fit target according to a situation. Or it may be formed in the form of an open box.

Referring to FIG. 2B, a spacer layer 230 is deposited on the hard mask pattern 220 and the etched layer 210. Here, the hard mask pattern 220 is preferably formed of a polysilicon layer, and may further include any one selected from the group consisting of an amorphous carbon layer and a silicon oxynitride layer (SiON) on the polysilicon layer. have. The amorphous carbon layer is formed by a chemical vapor deposition (CVD) method, and the silicon oxynitride layer is formed to protect the amorphous carbon layer.

In addition, the spacer layer 230 is formed of an oxide-based material, and more preferably, a low pressure tetra ethyl ortho silicate (LP-TEOS) film.

Here, after the spacer layer 230 is deposited, the entire surface etching process may be performed, so that the spacer layer 230 remains only on the sidewalls of the hard mask pattern 220, and then the subsequent process may be performed.

Referring to FIG. 2C, the gap fill layer 240 is formed to completely fill the gaps between the hard mask patterns 220 of the cell region I. Here, the gap fill film 240 is formed of a polysilicon layer. In this case, since the space between the hard mask patterns 220 is wide in the scribe lane region II, the gap fill layer 240 is not completely filled, and is deposited only on the sidewalls of the hard mask pattern 220.

Referring to FIG. 2D, a photoresist pattern 250 is formed on the hard mask pattern 220 of the scribe lane region II. The photoresist pattern 250 may be formed such that the spacer layer 230 formed on the sidewalls of the hard mask pattern 220 does not open.

Referring to FIG. 2E, the spacer layer 230 exposed by the etch-back process is removed. That is, the spacer layer 230 on the top and sidewalls of the hard mask pattern 220 is removed, and the spacer layer 230 under the gap fill layer 240 is not removed.

In this case, the spacer layer 230 of the scribe lane region II is covered by the photoresist pattern 250, such as 'B', and thus is not removed.

Referring to FIG. 2F, the etched layer 210 is etched using the gap fill layer 240, the hard mask pattern 220, and the photoresist pattern 250 as an etch mask to form an etched layer pattern 210a. In this case, since the gap fill layer 240 and the hard mask pattern 220 are both formed of a polysilicon layer, etching is performed using a difference in etching selectivity between the polysilicon layer and the etched layer 210.

Next, the photoresist pattern 250 is removed.

Here, the etched layer pattern 210a may be a frame component such as an overlay vernier, an alignment key, a die pit target or an open box.

As such, the spacer layer 230 of the scribe lane region II may not be removed so that the pattern may not fall or lift during the subsequent patterning process.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

1A to 1D are cross-sectional views illustrating a method of forming a pattern of a semiconductor device according to the prior art.

2A to 2F are cross-sectional views illustrating a method of forming a pattern of a semiconductor device according to the present invention.

<Explanation of Signs of Major Parts of Drawings>

200 semiconductor substrate 210 etched layer

220: hard mask pattern 230: spacer layer

240: gap film 250: photosensitive film pattern

Claims (12)

Forming an etched layer on the substrate in the cell region and the scribe lane region, and forming a hard mask pattern on the etched layer; Forming a spacer on sidewalls of the hard mask pattern; Forming a photoresist pattern on the hard mask pattern and the spacer in the scribe lane region; Removing the spacers of the cell region; And Etching the etched layer using the photoresist pattern and the hard mask pattern as an etch mask to form an etched layer pattern Pattern forming method of a semiconductor device comprising a. The method of claim 1, The etched layer pattern may include an overlay vernier, an alignment key, a die fit target, or an open box. The method of claim 1, The spacer is a pattern forming method of a semiconductor device, characterized in that formed by an oxide film. The method of claim 1, The hard mask pattern is a pattern formed method of a semiconductor device, characterized in that formed of a polysilicon layer. The method of claim 1, The pattern forming method is a pattern forming method of a semiconductor device, characterized in that applied to the SPT (Spacer Patterning Technology) process. Forming an etched layer on the substrate in the cell region and the scribe lane region, and forming a hard mask pattern on the etched layer; Forming a spacer on sidewalls of the hard mask pattern; Forming a gap fill layer filling the hard mask pattern of the cell region; Forming a photoresist pattern on the hard mask pattern and the spacer of the scribe lane region; Removing the spacers exposed in the cell region using the photoresist pattern as a barrier to open the gap fill layer and the hard mask pattern; And Etching the etched layer using the photoresist pattern, the gap fill layer, and the hard mask pattern as an etch mask to form an etched layer pattern Pattern forming method of a semiconductor device comprising a. The method of claim 6, The pitch of the hard mask pattern of the cell region is formed to be twice the pitch of the target pattern (Target Pattern) pattern forming method of a semiconductor device. The method of claim 6, The gap fill film is a pattern forming method of a semiconductor device, characterized in that formed of a polysilicon layer. The method of claim 6, The etched layer pattern of the scribe lane region may be an overlay vernier, an alignment key, a die fit target, or an open box. . The method of claim 6, The spacer is a pattern forming method of a semiconductor device, characterized in that formed by an oxide film. The method of claim 6, The hard mask pattern is a pattern formed method of a semiconductor device, characterized in that formed of a polysilicon layer. The method of claim 6, The pattern forming method is a pattern forming method of a semiconductor device, characterized in that applied to the SPT (Spacer Patterning Technology) process.
KR1020080101565A 2008-10-16 2008-10-16 Method for forming a pattern in the semiconductor device KR20100042423A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022179010A1 (en) * 2021-02-25 2022-09-01 长鑫存储技术有限公司 Method for forming overlay mark, and semiconductor structure
KR20230078432A (en) 2021-11-26 2023-06-02 한국인 Automatic nail clippers

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022179010A1 (en) * 2021-02-25 2022-09-01 长鑫存储技术有限公司 Method for forming overlay mark, and semiconductor structure
US20230223349A1 (en) * 2021-02-25 2023-07-13 Changxin Memory Technologies, Inc. Method for forming overlay marks and semiconductor structure
KR20230078432A (en) 2021-11-26 2023-06-02 한국인 Automatic nail clippers

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