KR20100040288A - Programmable chip enable and chip address in semiconductor memory - Google Patents

Abstract

Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be re-addressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.

Description

Programmable Chip Enable and Chip Address of Semiconductor Memory {PROGRAMMABLE CHIP ENABLE AND CHIP ADDRESS IN SEMICONDUCTOR MEMORY}

The present invention relates to techniques for fabricating integrated circuits, such as semiconductor-based memory devices.

BACKGROUND OF THE INVENTION Semiconductor-based memory devices, including volatile memory such as DRAM or SRAM and nonvolatile memory such as flash memory, are increasingly used in various electronic devices. For example, nonvolatile semiconductor memory is used in cell phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices. Among them, electrically erasable programmable read only memory (EEPROM) and electrically programmable read only memory (EPROM) including flash EEPROM are the most widely used semiconductor memories.

Like most storage devices, semiconductor memory devices may have bad elements or bad storage areas. For example, individual reservoirs or memory cells of a semiconductor memory array may be defective. In addition, peripheral circuitry for memory arrays, including word lines, bit lines, decoders, and the like, may be bad, which may also cause the associated reservoirs to be bad as well. It is inevitable that some of the memory arrays will be defective in any commercially manufactured semiconductor memory device.

Most failure management schemes are based on redundant memory cells that replace the primary memory cells that are determined to be defective. In a typical semiconductor memory manufacturing process as shown in FIG. 1, a wafer level test 12 is performed before packaging a memory chip to form a memory device. One wafer may include hundreds to thousands of memory chips, each memory chip comprising a memory array and peripheral circuit elements, wherein the peripheral circuit elements include control logic and logic circuitry for accessing the memory cells of the array. Such as: During the wafer level test 12, the function of the memory chip is tested, so that bad devices are not unnecessarily integrated into the packaged device. Wafer level testing is often performed at high and / or low temperatures (eg, 85 ° C. and / or −30 ° C.) to ensure its functionality under extreme conditions and to ensure its functionality even after stressing the chip. Memory cells that do not pass the functional test can be replaced with redundant memory cells on the chip. Depending on the type of memory being manufactured, different redundancy schemes may be applied. For example, individual memory cells may be replaced, entire columns or bitlines of memory cells may be replaced, or entire blocks of memory cells may be replaced.

After wafer level testing 12, the wafer is separated into individual memory chips and one or more memory chips are packaged 14 to form a memory device. A burn-in process 16 is then performed on the packaged memory device to stress the memory array and peripheral circuitry of the chip. In general, burn-in processes are performed at higher temperatures (eg, 125 ° C.) than wafer level tests. High voltages are applied to various parts of each chip to stress out the weak devices. Stress conditions of the burn-in process are set to cause the failure of the weak devices, such weak devices may be detected during subsequent package level testing 18. In some manufacturing processes a burn-in process may not be carried out.

Package level testing consists of various functional tests to determine which cells are defective after the burn-in process. In recent years, techniques such as anti-fuse techniques have been incorporated into the fabrication process, and memory cells that have proven defective after the burn-in process can be replaced with redundant memory cells in the memory chip. .

In some cases, package level testing 18 may determine that the entire memory chip is defective. For example, the number of defective memory cells in an array may exceed the redundancy capacity for a die that may fail or certain peripheral circuitry, and an unusable determination is made for such a die. If this situation occurs, the entire memory package containing the defective die becomes unusable and is generally badly processed 20, which leads to reduced yields in the manufacturing process. If the memory package contains multiple memory chips, failure of one die will cause the entire package to be discarded.

After packaging, a programmable chip enable circuit is provided in the memory die to isolate and disable a particular memory die. In a multi-chip memory package, memory dies that do not pass a package-level test may be disabled by programmable circuitry and isolated from the memory package. In general, the chip enable pins of each memory die in a multi-chip package are tied together so that all chips are enabled in response to the master chip enable signal. The programmable chip enable circuit may override the master chip enable signal received from the controller or host device. In order to allow a particular memory die to be re-addressed after packaging, a programmable chip address circuit is provided. For example, one or more defect free memory die may be re-addressed using programmable circuitry to replace the unique address provided by pad bonding, so that a contiguous range of addresses may be provided. Also, regardless of detecting a faulty memory die, the memory chips can be re-addressed after packaging.

In one embodiment of the present invention, a method of manufacturing a nonvolatile memory is provided, the method comprising packaging a plurality of nonvolatile memory chips and a controller in a memory package, where the memory package is a nonvolatile memory chip. And a common chip enable line connected to each and the controller. The plurality of nonvolatile memory chips are enabled in response to a chip enable signal provided on a common chip enable line. After packaging, a test is performed to determine whether the plurality of nonvolatile memory chips are defective. If the memory chip is defective, it is isolated from being enabled in response to the chip enable signal.

According to an embodiment of the present invention, there is provided a nonvolatile memory system, in which each chip has a plurality of nonvolatile memory chips having a plurality of nonvolatile reservoirs and one or more chip enable pins. Include them. The chip enable pin (s) of each memory chip is connected to a common line. The controller is in communication with a common line and the selection circuit on each memory chip is responsive to the chip enable signal provided by the controller. Each select circuit enables its corresponding memory chip in response to a chip enable signal. The set of one or more programmable circuits on each chip is in communication with a chip enable pin and a select circuit of the chip. The set of programmable circuits are configurable after packaging the nonvolatile memory system to isolate the corresponding memory chip not to be enabled in response to the chip enable signal.

In addition, each memory chip further includes a set of one or more device select pins and one or more programmable additional circuits. Device select pins are connected to the set of one or more pads and additional programmable circuits are connected between the device select pins and the select circuit. A unique address for each memory chip is defined using a predetermined configuration for a set of pads as part of packaging. The selection circuit for each memory chip will compare the unique address received on the set of device selection pins with the address received from the controller to determine whether the memory chip has been selected. By configuring additional circuitry programmable to provide another address to the chip's selection circuit in place of the address received from the set of pads, the unique address of the memory chip can be replaced with another address.

Programmable chip enable circuitry is provided in the memory die to enable specific memory die to be disabled after packaging and / or programmable chip address circuitry to provide that the specific memory die is re-addressed after packaging. It becomes possible.

1 is a flow chart illustrating a method of manufacturing a memory in accordance with the prior art.
2 is a block diagram of an exemplary memory package.
3 is a block diagram of a memory package according to an embodiment of the present invention.
4 is a flowchart illustrating a method of manufacturing a semiconductor memory in accordance with an embodiment of the present invention.
FIG. 5 is a table describing example techniques for re-addressing a packaged memory die.
Figure 6 is a block diagram illustrating a selection circuit for a memory die in accordance with one embodiment of the present invention.
7 is a circuit diagram illustrating a portion of a programmable chip enable circuit according to an embodiment of the present invention.
8 is a circuit diagram illustrating a portion of a programmable chip address circuit according to an embodiment of the present invention.
FIG. 9 is a table illustrating an example technique for re-addressing a memory die from multiple packages to form a package from the memory die of each smaller package.
10 is a block diagram of a nonvolatile memory system.
11 is a plan view of a NAND string.
FIG. 12 is an equivalent circuit diagram of the NAND string of FIG.
13 is a diagram of an exemplary structure of a memory array.
14 is a flowchart of a method of programming a nonvolatile memory.
15 is a graph illustrating exemplary threshold voltage distribution and full-sequence programming for an array of memory cells.
FIG. 16 is a graph illustrating an exemplary threshold voltage distribution for an array of memory cells and a two-pass programming technique in which each memory cell stores data for two pages.
17 is a flowchart of a method of reading a nonvolatile memory.
18 is a flowchart of a method of reading a page of data from a nonvolatile memory.

2 shows a nonvolatile memory system 100 having a plurality of individual memory dies 102 and a controller 110. Each memory die is an integrated circuit memory chip or a die mounted on a substrate (or printed circuit board 104). Controller 110 is also an integrated circuit chip or die mounted on its own printed circuit board 124. The two printed circuit boards may be mounted on a third printed circuit board (not shown). In other implementations, the controller and the memory die may be mounted on the same board.

Each memory device includes a nonvolatile memory array 106 composed of individual nonvolatile memory cells. The memory array may include, but is not limited to, flash memory cells arranged using structures such as, for example, NAND and NOR architectures. Each memory die 102 includes peripheral circuits for addressing and controlling an individual memory array. Controller 110 is included within the memory system to control memory operation between the host device and the individual memory die 102. The controller can independently address each memory die of the system. The controller does not necessarily need to be included in the memory system. For example, in some implementations, a host device, such as a processor of a standard processor-based computing system, may be responsible for the function of the controller. Also, multiple memory dies 102 may be packaged in one package without a controller and then combined with other packages and controllers to form a memory system.

Each memory die 102 includes two sets of external pinouts (or pins). For each die, the first group of pinouts 116 is a group of device select pins. The device select pin provides the memory device with a unique chip address for the packaged memory system. The device select pin of each die is connected to the set of bonding pads 114 of that die. In this particular configuration, each memory die 102 has five device select pinouts 116, which are connected to corresponding pads 114. By selectively grounding a particular pad to the memory die, the memory die is configured or keyed to have an address. A predetermined ground configuration for the pads may be provided to the individual memory die to assign a unique chip address within the package. Substrate 104 may include mounts having a predetermined pad configuration. When a die is mounted on the substrate, the corresponding chip address is assigned to these dies. Each memory die will determine an address from the configuration applied to the pad. Device select pins provide the pad's ground configuration to select circuitry in the device. When the device is enabled, the selection circuit compares the ground configuration with the addresses provided by the controller 110 to determine if it is selected and must process the request.

Assuming that ground in FIG. 2 represents logic '0', memory die 1 is assigned address '11' and in the figure 'x' represents a pad that is grounded. An address '10' is assigned to the memory die 2, an address '01' is assigned to the memory die 3, and an address '00' is assigned to the memory die 4. Although FIG. 2 shows a total of five device select pins and ground pads for each die, only two pads are needed to address the four individual memory dies shown in FIG.

The second set of pinouts 118 are device bus pinouts for connecting each memory die to the common device bus 120. One end of the device bus 120 is connected to the controller 110 and the other end is connected to each of the individual memory die 102. The number of device bus pinouts 118 will vary from implementation to implementation, in particular depending on the requirements of the bus within the system. Each memory die is connected to a common bus to receive and respond to various control commands and address commands issued by the controller 110. Although the control line 122 is shown as separate from the device bus 120, in various embodiments the control line may be considered part of the device bus 120. The control line 122 is a master chip enable line. In general, each memory device is enabled in response to a master chip enable signal provided by controller 110. In response to this chip enable signal, each device enables a set of input registers within the device. The chip or array address is delivered from the controller on the device bus and shifted into the registers of each device while enabled. The selection circuit 130 in each device compares the received array address with the unique address provided by the predetermined ground configuration for the set of pads 114 to determine whether the memory device will be selected. For sake. If so, the control circuitry for the memory die will process the request by writing data to or reading data from the array.

As mentioned above, some defects detected after packaging a memory die to form a package as shown in FIG. 2 may cause a failure for the entire memory package. The device bus pinouts 118 of each memory die are bundled together internally in a package. For example, each of the pinouts may be connected to a common bonding pad. Once the dies are packaged together, it is not possible to physically change the internal wiring to disconnect from the bad die. In addition, the pad bonding 114 of each memory die is fixed at the time of packaging. The predetermined configuration of the pad is applied and the memory die is connected via device select pins as part of the packaging process. Once the die is packaged, the configuration for fixed pad bonding cannot be changed. Thus, if one die does not pass the package level test, the package is typically found to be an error and discarded. Because the chip enable and device select pins are fixed prior to detecting a die error, the die cannot be disabled or mapped out from the address range for the device. Even if there is only one faulty die, the entire package becomes unusable.

To overcome these disadvantages, a programmable chip enable and a programmable chip address are provided to individual memory dies in the nonvolatile memory system. Faulty dies in a multi-chip configuration can be isolated if their errors are detected after packaging. If a faulty die breaks the contiguous address range for the memory system, other dies in the package can be re-addressed via a programmable chip address, which yields a contiguous address range despite the faulty die. For sake.

3 illustrates a nonvolatile memory system 200 according to an embodiment of the present invention. The system 200 of FIG. 3 includes many of the same components as the components of the system shown in FIG. Along with the controller 210, a number of memory devices 202 are provided in a package. Each memory device 202 includes a first group 216 of pins connected to a corresponding set of bonding pads 214 for a die. The second group of pins (or pinouts) 218 is a device bus pinout for connecting each memory die to the common device bus 220. As before, each memory die is connected to the control line 22 via a chip enable pin, which may be considered part of the device bus 220.

The control circuits of each memory die in FIG. 3 include a first programmable circuit 240 that replaces or reprograms the unique address provided by the set of ground pads, and is also provided on the control line 222. Second programmable circuitry 242 isolating the memory die from the chip enable signal. Although the first and second circuits 240 and 242 are shown as separate from the select circuit 230 of each memory die, these circuits 240 and 242 may be included in the select circuit as part of the select circuit. It may be. Each of the programmable circuits may include one or more fuses or other programmable circuitry capable of reprogramming the chip enable signal and / or the unique array address for that memory die.

Various types of programmable circuits may be used to store the chip enable signal and / or data needed to reprogram the unique address for a particular memory die. Typically, some type of fuse circuits may be provided to store logic data used to program the chip enable signal and / or chip address for the die. Since fuse circuits are programmed after device packaging, the fuse circuits must be writable in a packaged state. Anti-fuses provide a useful means for storing logic data and are used in one embodiment of the present invention. Unlike the initial low resistance state of a standard fuse, the anti-fuse has a first logic state corresponding to high resistance and a second logic state corresponding to low resistance. In some implementations, antifuses are written or blown using a laser annealing process or an electrical process to bring the device into a low resistance state corresponding to a second logic state or a programmed logic state. Because direct access to fuses is often required and can only be integrated into wafer level testing, this type of antifuse may not be appropriate for post-packaging programming.

Since ROM fuses can be written even after the molding and packaging process, these ROM fuses are particularly suitable for post-packaging programming. The ROM fuse includes an anti-fuse element in one of two logic states, including an unprogrammed state (high-resistance state) or a programmed state (low-resistance state). Anti-fuse links that are not programmed in ROM arrays or registers can have a gigaohm resistance, and programmed anti-fuse links can have hundreds of ohms. To program a typical anti-fuse, a high voltage is applied to move the link from an initial high resistance state to a programmed state (low resistance state). This serves to store one bit of logical data. Other electrically programmable fuses may also be used, which experience post-packaging programming. For example, some electrically programmable fuses typically store data in a logic state using a programmable nonvolatile memory device. In general, electrically programmable fuses can be accessed and programmed both before and after device packaging. In one embodiment using a programmable fuse, a portion of the main array of memory cells may be used for the memory die.

Programmable chip enable circuit 242 may have a fuse or an anti-fuse in its initial state, the initial state of the anti-fuse causing the chip enable signal to be passed directly to the selection circuitry of the memory die. In this state, the memory die typically operates to receive a master chip enable signal from a controller (or host device) on its chip enable pin. A second value may be set in the fuse after packaging the device to cause the chip enable signal to be basically overridden for that particular memory die. ROM anti-fuse (also simply referred to as ROM fuse) may be set to a low-resistance state, which allows other signals to be provided instead of the chip enable signal provided on the device bus.

Assume that each memory die 202 is enabled by a selection circuit in response to a low or ground voltage on the chip enable line. As shown in FIG. 3, a programmable chip enable circuit is provided between the chip enable pin and the select circuit. When the programmable circuit is set to the second value, a high voltage may be applied to the input of the selection circuit instead of the chip enable signal. Thus, the chip will not be enabled in response to the chip enable signal provided by the controller or host.

One or more fuses for programmable chip address circuit 240 may store and provide an alternative unique address for its corresponding memory die. In Figure 3, each unique chip address consists of two bits to address four memory dies individually. Thus, two fuses may be used to assign an alternative address. A third fuse can be used to store a value indicating whether the address provided by the fuse should be used in place of the standard address from the pad bonding. For example, the memory die chip address may be reprogrammed, such that the memory die chip address may be reprogrammed by reprogramming the third fuse to activate the chip address circuitry to replace the chip address. In response to the third fuse being set in the programmed state, logic values stored by the first two fuses may be provided to the selection circuit in place of the unique address provided on the device select pins from the pad bonding. The fuse in its initial state may, for example, correspond to logic '0' and the fuse in the programmed state may correspond to logic '1'. If the third fuse is set, values from the first two fuses are supplied to the input of the selection circuit in place of the pad bonded address.

A process for manufacturing a nonvolatile semiconductor memory device is illustrated in FIG. 4 where programmable chip enable and / or programmable chip address is used. Wafer level testing is performed on a group of semiconductor wafers in step 302, where typically each wafer has a plurality of non-separated memory array dies including a memory array and peripheral circuitry for controlling the memory array. After wafer level testing, each memory die of the wafer is separated and packaged (step 304). Single chip packages, multi-chip packages, all of which may be packaged in step 304 with or without a controller chip. A wide variety of package configurations can be used. Generally, the die is mounted on a substrate using a conductive layer etched on one or both sides. An electrical connection is made between the die and the conductive layer (s), which provide an electrical lead structure for integrating the die into the electronic system.

As part of the process of forming an electrical connection between the die and the conductive layer (s), the chip enable pins of each memory array may have a master chip enable line or common to receive a chip enable signal from a controller or host device. Is connected to the bus (step 306). In step 308, for the device select pins of each chip, a predetermined configuration is applied to the set of bond pads, so that each chip is assigned its own unique chip address. The selected pins may be configured as ground pads defining an address as shown in the example of FIG. For some dies, bond pads may be provided on the die, which may be connected to, for example, an electrical lead of a leadframe, to define a unique chip address. Once an electrical connection is established between the die and the substrate, the assembly is typically surrounded by a molding compound to provide a protective package.

An optional burn-in process as described above with respect to FIG. 1 may be performed in step 310 to stress the package, including the memory array (s), peripherals, controllers, and the like. After burn-in, testing is performed on the package (step 312). For example, there are various types of package level tests, including bit line tests and word line tests to detect defects, shorts, etc., memory cell tests for read, write, and data retention, peripheral circuit tests, and the like. Can be applied. In some embodiments, after packaging, redundant memory cells may be used in step 312 to replace defective memory cells of individual memory die individually or in block units, column units, or the like.

If no die is determined to be defective, the process is complete and packaged devices with full capacity are delivered at step 316. If one or more memory dies are defective, these defective dies may be isolated from other dies in the package (step 318). In one embodiment, step 314 includes determining if the number of defective dies is a manageable number and proceeding to step 318 only if the number of defective dies can be processed by the programmable circuitry. can do. If all dies are faulty or if another predetermined number of dies are faulty, the package may be discarded.

In step 318, the defective die is disabled as described above in one embodiment of the present invention. Programmable circuitry on a memory die may invalidate a chip enable signal provided to the die on a common device bus for a package. For example, a ROM fuse may be programmed to a predetermined logic state that causes the die to be disabled. In response, the circuit can provide another bias to the chip enable input (eg, a chip enable pin) that invalidates the chip enable signal. If the chip enable signal goes low to enable the device, the programmable circuit can output a high voltage on the chip enable line, which is internal to the die and always disables the die. .

In step 320, it is determined whether one or more defect free memory dies of the chip can be re-addressed. In some cases, the defective die is simply disabled and the memory package is provided with a reduced capacity by that amount. As will be described in more detail below, in other cases, one or more defect free memory dies are re-addressed to provide a flawless contiguous address range for the memory package. For example, if the second of the four chip memory packages is disabled, chip 0 may be re-addressed to the address of chip 1 to provide a contiguous address range for chip 2 and chip 3. If one or more die is re-addressed, an alternate address is provided for that die using programmable circuitry to replace the unique address provided by pad bonding.

FIG. 5 is a table illustrating an exemplary scheme for re-addressing memory die in a four chip package. The example scheme is just one example for reconfiguring chip addresses for a memory die. In this example, three chip packages are not provided. Thus, even if only one die is defective, at least two dies are disabled. This can be done, for example, to provide a memory package having a normalized size. In another example, only one defective die may be disabled and three chip packages may be provided.

If all chips are good, no re-addressing is required and a full capacity package is provided. If chip 3 is defective, a package is provided in which chip 2 and chip 3 are isolated and having a capacity of 1/2. Since chip 0 and chip 1 provide contiguous address ranges, no chip is re-addressed. If chip 2 is bad, chips 2 and 3 are once again isolated and none of the chips are re-addressed. If chip 1 is bad, chip 1 and chip 3 are isolated and chip 2 is reprogrammed to chip 1's chip address. This provides a contiguous address range corresponding to the original addresses of chip 0 and chip 1. If Chip 1 and Chip 3 are bad, they are isolated and Chip 2 is reprogrammed with the chip address for Chip 1. If chip 1 and chip 2 are bad, they are isolated and chip 3 is reprogrammed to the address of chip 1. If chip 1, chip 2, and chip 3 are bad, they are disabled and chip 0 remains at its original address. If chip 0 is bad or chip 0 and chip 3 are bad, chip 0 and chip 3 are disabled and chip 2 is reprogrammed to the address of chip 0. If chip 0 and chip 2 are bad, they are isolated and chip 3 is programmed to the address of chip 0. If chip 0, chip 2, and chip 3 are bad, they are disabled and chip 1 is programmed to the address of chip 0. If chip 0 and chip 1 are bad, they are disabled and chip 2 is programmed to the address of chip 0. If chip 0, chip 1, and chip 3 are bad, they are disabled and chip 2 is programmed to the address of chip 0. If chip 0, chip 1, and chip 2 are bad, they are isolated and chip 3 is programmed to chip 0's address. If all chips are bad, the package is discarded.

6 illustrates a selection circuit 230 according to an embodiment of the present invention. In Figure 6, the programmable circuit is shown as being part of the selection circuit 230, although this need not be the case in all implementations. Typically, the selection circuit includes a shift register 352, a comparator 354, an address matching latch 356, and an S-R register 358. The select circuit has device select pins 216 and input from device bus 220, including chip enable line 222. The selection circuit has an output DS for selecting or not selecting the device (memory die) under control.

Comparator 354 and address matching latch 356 implement address matching for the memory die. In the example of FIG. 6, the 2-bit address is shifted from the serial lines S0 and S1 of the device bus 220 into the shift register 352. The clocking signal is transmitted on the control line P / D, which is gate-enabled by the LOW signal on the master chip enable line 222. The LOW signal is inverted by the inverter 368. In FIG. 6, the master chip enable line 222 is shown as part of the device bus 220. Next, a 2-bit unique chip address is passed from the shift register 352 to the comparator 354.

When the programmable chip address circuit is in its initial state, the comparator receives the unique chip address obtained from the device select pinout 216 as a second input. As discussed above, the address for each location in the array is defined by the grounding configuration or "key" of the bonding pads 214. Because of the memory die connected to a particular mount on the board, the address defined by the mount's pad is passed to the memory device through the device select pinout.

The comparator compares the address received on serial lines S0 and S1 with the address obtained on the device select pin. If the addresses match, the comparator output 360 goes HIGH. This output is clocked in the address matching register 356 by the falling edge of the chip enable signal on the chip enable line CE 222 (its connection not shown). This causes the S-R register 358 to be set to HIGH, so the output DS is also high and the device is selected. If the addresses do not match, the DS will be LOW and the device will not be selected.

Programmable chip enable circuitry 242 is used to isolate a particular memory die from a package. This is accomplished by isolating the memory die from the master chip enable signal, where the memory die is disabled and thus no memory die is selected. The programmable chip enable circuit can be programmed even after packaging to disable the corresponding memory die. When the programmable chip enable circuit is in an initial state, the programmable chip enable circuit transfers the chip enable signal received through the master chip enable line 222 to an inverter 368 for controlling the gate 362. Will deliver immediately. The selection circuit operates in the normal mode so that the chip enable signal enables the clocking signal P / D to shift the address on the serial lines SO and Sl into the shift register 352.

If the programmable circuit is set to the second state, the memory die is isolated from the chip enable line 222. The gate 362 is enabled by the master chip enable signal going low. Thus, the programmable circuit can drive the HIGH signal on line 370 instead of the chip enable signal that has typically been delivered on line 370. In this way, regardless of the chip enable signal provided on the chip enable line by the host or controller, the gate will remain off and the clocking signal will also be unique chip address on serial lines S0 and S1. Will not enable the shift register 352 to receive. By disabling the input shift register 352, the corresponding memory die is disabled and will remain in that state regardless of the chip enable signal.

Programmable device selection circuitry 240 is used to reprogram the unique chip address for a particular memory die in a package. The device select input pins are connected to the programmable device select circuit, and when the programmable circuit is in the initial operating state, the programmable device select circuit will pass those signals directly to the comparator 354. The first fuse can store a single bit, which indicates that the chip address received on the device select pin should be invalidated. When the single bit is asserted, the programmable device selection circuit provides a different unique address to the comparator 354, so that the chip address provided by physical bonding can be invalidated. Multiple fuses corresponding to the number of bits of the unique chip address are used to provide different addresses. For example, the initial resistance state of the fuse may correspond to logic '0' and the programmed low resistance state may correspond to logic '1'. Or vice versa. In order to store a new chip address, address fuses may be optionally conditioned. The programmable circuit will then provide this address to the comparator via bus 364. As such, the memory die can be reprogrammed with a new unique chip address even after packaging.

Figure 7 illustrates a programmable chip enable circuit 242 in accordance with one embodiment of the present invention. The ROMRD timing signal is provided to the gate 402 as a first input. The data signal from the ROM fuse is provided to the second input. The data signal carries a signal for single bit data from a ROM fuse for the circuit. If the ROM fuse is in its initial state, the gate is not enabled in response to the timing signal. In various embodiments, the timing signal may be asserted at power up or power down, for example, to allow the data from the ROM fuse to be read. If the gate is not enabled by a programmed fuse, the gate output remains LOW and the output CE_force also remains LOW. As such, the master chip enable signal is transferred to the selection circuit, as described above with reference to FIG.

If a ROM fuse is programmed, CE_ROM will be high when the ROMRD timing signal is issued and the output of gate 402 will be high. When the output of the gate 402 becomes high, the output of the OR gate 404 also becomes high. In response to the timing signals i_RRD and o_RRD, the HIGH value, which is the output of the OR gate, is sampled by the flip flop 406. Next, the sampled HIGH value is provided as the output CE_force.

An output CE_force is provided to the NOR gate 408 along with a sampled value of the chip enable signal from the chip enable pin. An input buffer (not shown) may be used for the sampled values. If CE_force is HIGH by programming the ROM fuse, the output of NOR gate 408 is LOW. The output is inverted by inverter 410 and provided as an internal chip enable signal CE_internal. A CE_internal signal that is HIGH will be provided to inverter 368 (FIG. 6), which outputs a LOW value to gate 362 (FIG. 6). Thus, shift register 352 is disabled, resulting in the memory die being disabled.

Figure 8 illustrates a programmable device selection circuit 240 in accordance with one embodiment of the present invention. An output of the ROMRD timing signal and the first ROM fuse (referred to as the selection fuse) are provided to the gate 420. When the timing signal ROMRD goes high, data from the ROM fuse is provided to the gate. If no fuse is programmed, the output of the gate remains low and the output of flip flop 424 is low. If the fuse is programmed, the output of gate 420 goes HIGH and the output of OR gate 422 goes HIGH. Next, CADD_SEL, which is an output of the flip flop 424, becomes HIGH in response to the timing signals i_RRD and o_RRD.

The lower portion of the circuit shown in Figure 8 is used to select either the original chip address provided by pad bonding or the programmed address provided by the programmable circuit. The first multiplexer MUX1 426 receives two inputs, CADD0_ori and CADD0_ROM, which are for the first bit of the chip address. CADD0_ori is the signal from pad bonding for the first bit of the chip address. CADD0_ROM is the signal from the first ROM fuse for the first address bit. The second multiplexer MUX2 428 receives two inputs, CADD1_ori and CADD1_ROM, which are for the second bit of the chip address. CADD1_ori is the signal from the pad bonding for the second bit of the chip address. CADD1_ROM is for the second address bit as the signal from the second ROM fuse. If CADD_SEL is low, this corresponds to that no selection ROM fuse has been programmed for the programmable device selection circuit, and hence the original chip address is provided from the multiplexers. That is, MUX1 provides the output CADD0 for the first bit of the chip address from pad bonding (CADD0_ori) and MUX2 provides the output CADD1 for the second bit of the chip address from pad bonding (CADD1_ori). If less than CADD_SEL, this corresponds to the selection ROM fuse being programmed, and the programmed chip address from each of the ROM fuses is provided. That is, MUX1 provides the CADD0_ROM value from the first address ROM fuse on the output CADD0 and MUX2 provides the CADD1_ROM value from the second address ROM fuse on the output CADD1.

The exemplary embodiments shown in Figs. 6-8 use two bits of address. Thus, the multiplexers receive two inputs and two ROM fuses are used to replace the chip address. If more bits are used for the chip address, additional ROM fuses may be used for the additional bits of the address.

It should be noted that the programmable chip address may be used independently of the programmable chip enable. For example, it may be revealed through package level testing that a particular chip has better or better performance characteristics than other chips. If it is desired (or desired) that chip 0 of the package should be "cleaner" or have better performance, the selected chips may be re-addressed. For example, if chip 3 has particularly good performance, then the address of chip 3 and the address of chip 0 can be exchanged with each other so that a good chip can be placed in the head of the array. In this case, none of the chips are disabled.

As mentioned above, some memory systems may include multiple packages. For example, one memory card may include two or more memory packages. 9 is a table illustrating another example for re-addressing a select memory die to provide a continuous address range. In Figure 9 two memory packages are combined to form a larger memory package (e.g., a memory card). Each package contains four memory array dies. Each combined memory package includes at least one defective die. By combining two packages, each of which contains a defective die, one good four-die package is provided.

If chip 3 of the first package is bad and chip 0, chip 1, and chip 2 of the second package are bad, the two packages are combined to form a memory package having a contiguous address range consisting of four memory dies. can do. As described above, chips 3 of the first package and chips 0, 1, and 2 of the second package may be isolated. Next, chip 3 of the second package may be reconfigured to the address of chip 3 of the first package. In some embodiments, separate package addresses may be used or specific bits may be used for the package and internal die addresses. In this case, reconfiguring chip 3 of the second package only needs to reconfigure the bits to represent the first package. In other cases, more complex re-addressing may be used.

FIG. 10 is another diagram of a nonvolatile memory system as shown in FIG. 3, illustrating additional components that may be included in some implementations. Memory device 510 includes one or more memory dies or chips 512. Memory die 512 includes a two-dimensional array 500 of memory cells, control circuit 520, and read / write circuits 530A, 530B. In one embodiment of the invention, access to the memory array 500 by various peripheral circuits is implemented in a symmetrical manner on opposite sides of the array, thus the density of the access lines and the density of the circuit at each side. Can be reduced in half. The read / write circuit 530A, 530B includes a number of sense blocks 550, which allows pages of memory cells to be read or programmed in parallel. Memory array 500 may be addressed by word lines through row decoders 540A and 540B and by bit lines through column decoders 542A and 542B. In a typical embodiment, like one or more memory die 512, a controller 544 is included within the same memory device 510 (eg, a removable storage card or package). Command and data are passed between the host and the controller 544 via lines 532, and between the controller and one or more memory die 512 via lines 534, which is the device bus 220. Can be

The control circuit 520 cooperates with the read / write circuits 530A and 530B to perform a memory operation on the memory array 500. The control circuit 520 includes a state machine 522, an on-chip address decoder 524, and a power control module 526. State machine 522 provides chip level control for memory operations. On-chip address decoder 524 provides an address interface between an address used by a host or a memory controller and a hardware address used by decoders 540A, 540B, 542A, 542B. The power control module 526 controls the power and voltages supplied to the word lines and bit lines during the memory operation.

In one embodiment, the selection circuit 230 is part of the control circuit 520. The control circuit may form part of the state machine or may be a standalone circuit component. As such, programmable circuits 240 and 240 may be included in the control circuit as well as the state machine. The control circuit may or may not have programmable fuse elements. For example, in some implementations a dedicated ROM fuse may be provided in the control circuit. In other cases, a real memory array 500 may be used for the programmable elements, so that programmable circuitry can be divided between the control circuit 520 and the array.

In one embodiment, the memory cell array 500 is configured as a NAND flash memory array. 11 is a top view illustrating an example NAND string 600. 12 is an equivalent circuit diagram thereof. 11 and 12 include transistors 610, 612, 614, and 616 disposed in series between the first select gate 612 and the second select gate 622. In one embodiment, each of the transistors 610, 612, 614, 616 forms a separate memory cell of the NAND string. In another embodiment, the NAND string memory cells may include multiple transistors or may differ from those shown in FIGS. 11 and 12. As discussed herein, it is not limited to a particular number of memory cells present in one NAND string. The select gate 620 connects the NAND string to the bit line 626. The select gate 622 connects the NAND string to the common source line 628. The selection gate 620 is controlled by applying an appropriate voltage to the control gate 620CG via the selection line SGD. The select gate 622 is controlled by applying an appropriate voltage to the control gate 622CG via the select line SGS. Each transistor has a control gate and a floating gate. For example, transistor 610 has control gate 610CG and floating gate 610FG. Transistor 612 has control gate 612CG and floating gate 612FG. Transistor 614 has control gate 614CG and floating gate 614FG. Transistor 616 has control gate 616CG and floating gate 616FG. The control gate 610CG is connected to the word line WL3, the control gate 612CG is connected to the word line WL2, the control gate 614CG is connected to the word line WL1, and the control gate 616CG. Is connected to the word line WL0.

As in the example shown in Fig. 13, the NAND flash EEPROM is divided into 1024 blocks. Each block of memory cells includes a set of bit lines forming a column and a set of word lines forming a row. In general, each block is divided into a number of pages. Although one or more pages may be programmed or read through a single operation, generally one page is the smallest unit of programming or reading. In another embodiment, individual pages may be divided into segments and the segment may include the fewest number of cells written at a time as a basic programming operation. In general, one or more data pages are stored in a row of memory cells. A page can store one or more sectors of data, the size of which is typically defined by the host system. One sector includes user data and overhead data. In general, the overhead data includes an Error Correction Code calculated from the user data of that sector. A portion of the controller (to be described later) calculates the ECC when data is programmed into the array and also checks the ECC when data is read from the array. Alternatively, the ECC and / or other overhead data may be stored in pages different from the user data associated with them, even in different blocks. Generally, a sector of user data is 512 bytes, which corresponds to the size of one sector typically used in magnetic disk drives. In general, overhead data is an additional 16-20 bytes. A large number of pages form one block, for example eight pages may form one block, or 32, 64 or more pages may form a block. In some embodiments, rows of NAND strings make up the block.

13 shows four memory cells connected in series to form one NAND string. Although each cell is shown as including four cells in the NAND string, more or fewer than four cells (eg, 16, 32, or another number of cells) may be used. One terminal of the NAND string is connected to the corresponding bit line through a first select transistor or gate (connected to the select gate drain line SGD). The other terminal of the NAND string is connected to a common source (c-source) through a second select transistor (connected to the select gate source line SGS). Data stored in each block can be erased at the same time. There are 8512 columns in each block of the example of FIG. 13, and these columns are divided into even columns and odd columns. The bit lines are divided into even bit lines BLe and odd bit lines BLO. In an odd / even bitline structure, memory cells along a common wordline and connected to odd bitlines are programmed at one time, and memory cells along a common wordline and connected to even bitlines are programmed once. Thus, 532 bytes of data can be read or programmed simultaneously. These 532 bytes of data being read or programmed simultaneously form one logical page. Thus, in the above example, one block can store at least eight pages. When each memory cell stores two bits of data (eg, a multi-level cell), one block stores 16 pages. Other sized blocks and pages may also be used with the present invention.

In another embodiment of the present invention, the bit lines are not divided into odd and even bit lines. This structure is commonly referred to as an all bitline structure. In an all bitline structure, during read and program operations, all bitlines of a block are selected simultaneously. Memory cells along a common wordline and connected to any bitline are programmed simultaneously. In other embodiments, the bitlines or blocks may be split into other units (eg, right and left, in two or more groups, etc.).

In one example of the invention, when programming a memory cell, the drain and P-well receive zero volts while the control gate receives a series of programming pulses of increasing magnitude. In one embodiment, the magnitude of the series of pulses ranges from 12 volts to 24 volts. In another embodiment, the range of the series of pulses may be different, for example having a starting level higher than 12 volts. During programming of the memory cells, verify operations are performed in the periods between the programming pulses. That is, the programming level of each cell of the cell group being programmed in parallel is read out between the respective programming pulses to determine whether the cell being programmed has reached or exceeded the verify level. One means for verifying programming is to test continuity at a particular comparison point. Cells that are verified to be fully programmed are locked out, for example, in a NAND cell, thereby all subsequent programming pulses by raising the bitline voltage from 0 volts to V _DD (eg, 1.8 to 3.3 volts). Terminates the programming process for these cells. In some cases, the number of pulses will be limited (eg, limited to 20 pulses), and an error is expected if a given memory cell is not fully programmed even by the last pulse. In some implementations, memory cells are erased (in blocks or other units) prior to programming.

Figure 14 is a flow chart illustrating one embodiment of a method of programming a nonvolatile memory. The memory cells to be programmed are erased at step 700. Step 700 may include erasing (in blocks or units) memory cells other than the memory cells to be programmed. In step 702, soft programming is performed to narrow the erase threshold voltage distribution for erased memory cells. As a result of the erase process, some memory cells may be in a deeper erase state than necessary. Soft programming may apply small programming pulses to move the threshold voltage distribution of erased memory cells closer to the erase verify level. At step 704, a " data load " command is issued by the controller 544 and input to the control circuit 520, which causes data to be input into the data input / output buffer. The input data is recognized as a command and latched in the state machine 522 via a command latch signal and, although not shown, is input to the control circuit 520. In step 706, address data representing the page address is input from a controller or host to a row controller or decoder 540A, 540B. The input data is identified as a page address and latched through state machine 522 and is affected by the address latch signal input to the control circuit. In step 708, a page of program data for the addressed page is input to the data input / output buffer for programming. For example, in one embodiment of the present invention, 532 bytes of data may be input. The data is latched in the appropriate registers / latches for the selected bit lines. In some embodiments, the data is also latched in the second register for the selected bit lines, which will be used in the verify operation. At step 710, a " program " command is issued by the controller and entered into the data input / output buffer. This command is latched by the state machine 522 via a command latch signal input to the control circuit.

Triggered by a "program" command, the data latched in step 708 will be programmed into the selected memory cells, which are controlled by the state machine using a stepped pulse program voltage signal applied to the appropriate word line. . In step 712, the program pulse voltage level Vpgm applied to the selected word line is initialized to a start pulse (e.g., 12 volts) and the program counter PC held by the state machine 522 is initialized to zero. In step 714, a first Vpgm pulse is applied to the selected word line. If a logic " 0 " is stored in a particular data latch to indicate that the corresponding memory cell should be programmed, the corresponding bit line is grounded. On the other hand, if logic " 1 " is stored in a particular data latch to indicate that the memory cell must maintain its current data state, the corresponding bit line is connected to V _DD and programming is inhibited.

In step 716, states of the selected memory cells are verified. If it is detected that the target threshold voltage of the selected memory cell has reached the appropriate target level, the data stored in the corresponding data latch is changed to logic " 1. " If it is detected that the target threshold voltage of the selected memory cell has not reached the appropriate target level, the data stored in the corresponding data latch is not changed. In this way, the bit lines in which logic "1" is stored in the corresponding data latches do not need to be programmed. If all data latches are storing logic "1", the state machine knows that all selected cells have been programmed. In step 718, it is checked whether all data latches are storing logic "1". If so, the programming process is complete and successful, since all selected memory cells have been programmed and verified to be in the target state. A status of "PASS" is reported at step 720. In some implementations, it should be noted that at step 718, not all data latches need to store a logic "1". If at least a predetermined number of data latches are storing logic "1", that may be sufficient. The data latches still storing logic "0" are related to cells that have not yet been programmed (slowly programmed cells) or to defective cells. A limited number of insufficiently programmed cells or defective cells may be tolerated, in which error correction (ECC) is applied during subsequent read operations to correct corrupted data associated with slow programmed memory cells or defective memory cells. Because it can.

If at step 718 it is found that not all data latches are storing logic "1", the programming process continues. In step 722, the program counter PC is checked for a program limit value. An example of a program limit is 20. However, other values may be used. If the program counter PC is not less than 20, it is determined whether the number of memory cells not successfully programmed is less than or equal to a predetermined number (step 724). If the number of bits that were not successfully programmed is less than or equal to the predetermined number, then the programming process is flagged as passed and a status of PASS is reported in step 726. Bits that were not successfully programmed can be corrected using error correction during the read process. However, if the number of memory cells that were not successfully programmed is greater than the predetermined number, then the programming process is flagged as failed and a status of FAIL is reported in step 728. If the program counter PC is less than 20, the Vpgm level is increased by the step size and the program counter PC is incremented at step 730. After step 730, the process returns to step 714 to apply the next Vpgm pulse.

The flowchart of FIG. 14 illustrates a single-pass programming method that can be applied to a binary repository. In a two-pass programming method that can be applied to a multi-level repository, for example, multiple programming steps or verification steps may be used within a single iteration of the flowchart. Steps 712-730 may be performed for each pass of a programming operation. In a first pass, one or more program pulses may be applied and the results verified to determine whether the cell is in an appropriate intermediate state. In a second pass, one or more program pulses may be applied and the results verified to determine if the cell is in the proper final state.

If the programming process ends successfully, the threshold voltages of the memory cells must be within one or more threshold voltage distributions for programmed memory cells or one or more threshold voltage distributions for erased memory cells. FIG. 15 is a diagram illustrating threshold voltage distributions for a memory cell array when each memory cell stores two bits of data. 15 shows a first threshold voltage distribution E for erased memory cells. Three threshold voltage distributions A, B, C for programmed memory cells are also shown. In one embodiment, the threshold voltages in the E distribution are negative and the threshold voltages in the A, B and C distributions are positive.

Each different threshold voltage range shown in FIG. 15 corresponds to predetermined values for the set of data bits. The particular relationship between the data programmed into the memory cell and the threshold voltage levels of the memory cell depends on the data encoding scheme applied to that cell. In one embodiment, data values are assigned to threshold voltage ranges using Gray code assignment, so that even if the threshold voltage of the floating gate is shifted to an adjacent physical state due to an error, only 1 Only bits will be affected. As an example, "11" is assigned to threshold voltage range E (state E), logic value "10" is assigned to threshold voltage range A (state A), and logic value "00" is assigned to threshold voltage range B (state B). Is assigned to the threshold voltage range C (state C). However, in other embodiments, gray codes may not be used. Although four states are shown in Figure 15, the present invention can be used with other multi-state structures that include more or fewer than four states.

15 also shows three read reference voltages Vra, Vrb, and Vrc for reading data from memory cells. The threshold voltages of a given memory cell are Vra, Vrb, Vrc By testing whether it is higher or lower, the system can determine which state the memory cell is in. 15, three verify reference voltages Vva, Vvb, and Vvc are shown. When programming the memory cells to state A, the system will test whether these memory cells have a threshold voltage equal to or greater than Vva. When programming the memory cells to state B, the system will test whether these memory cells have a threshold voltage equal to or greater than Vvb. When programming the memory cells to state C, the system will test whether these memory cells have a threshold voltage equal to or greater than Vvc.

In one embodiment shown in Fig. 15, known as full sequence programming, memory cells can be programmed directly from erase state E to any of programming states A, B, C. For example, a population of memory cells to be programmed may be erased first, so that all reservoirs in the population are in erased state E. The process shown in Figure 15 will then be used to program the memory cells directly into state A, B, or C. Some memory cells are programmed from state E to state A, while other memory cells are programmed from state E to state B and / or from state E to state C. In such an embodiment, both bits coded for a particular memory state of a memory cell may be considered part of a single page data.

Figure 16 illustrates an example of a two-pass technique for programming a multi-state memory cell that stores data for two different pages (lower page and upper page). Four states are shown: state E (11), state A (10), state B (00), and state C (01). For state E, both pages store "1". For state A, the lower page stores "0" and the upper page stores "1". In the case of state B, both pages store "0". For state C, the lower page stores "1" and the upper page stores "0". Although specific bit patterns have been assigned for each state, it should be noted that other bit patterns may be assigned. In the first programming pass, the threshold voltage level of the memory cell is set according to the bit to be programmed in the lower logical page. If the bit is a logic " 1 ", the threshold voltage is not changed since the threshold voltage is already in the proper state as a result of being previously erased. However, if the bit to be programmed is a logic "0", the cell's threshold voltage rises to state A, which is shown by arrow 750. This terminates the first programming pass.

In the second programming pass, the threshold voltage level of the cell is set in accordance with the bit to be programmed into the upper logical page. If the upper logical page bit is to store a logic "1", programming does not occur because the memory cell is in either state E or A, depending on the programming of the lower page bit, and both states E and A are logic. Has an upper page bit of "1". If the upper page bit is to store a logic "0", the threshold voltage is shifted. If the cell remains in erase state E as a result of the first pass, then the cell is programmed in the second pass, so that the threshold voltage is increased to be in state C, as shown by arrow 754. If the memory cell was programmed to state A as a result of the first programming pass, then the memory cell is further programmed in the second pass, thus the threshold voltage is increased to be in state B as shown by arrow 752. The result of the second pass is to program the repository into a predetermined state specified to store a logical "0" for the upper page without changing the data for the lower page. Many other methods exist for measuring the conduction current of a memory cell during a read or verify operation. In the above example, the conduction current of the selected memory cell will allow (or disallow) the NAND string containing the selected memory cell to discharge the bit line. In order to determine whether the bit line is discharged or not, the voltage on the bit line is measured after a predetermined time. In another example, the conduction current of the memory cell is measured by the rate at which the dedicated capacitor in the sense amplifier is discharged.

Figure 17 is a flow chart illustrating one embodiment for reading data from nonvolatile memory cells. Figure 17 provides a read process at the system level. In response to the request for reading data received in step 800, a read operation is performed on the particular page (step 802). In one embodiment, when data is programmed for a page, the system will also generate Error Correction Codes (ECCs) and write these ECCs along with the data page. ECC techniques are well known in the art. The ECC process used may include any suitable ECC process known in the art. When reading data from the page, ECC will be used to determine if there is an error in the data (step 804). The ECC process may be performed at the controller, at the state machine, or somewhere in the system. If there is no error in the data, then at step 806 the data is reported to the user. If an error is found in step 804, it is determined whether the error is correctable (step 808). The error may be due to the floating gate coupling effect or due to other physical mechanisms. Various ECC methods have the ability to correct a predetermined number of errors in the data set. If the ECC process can correct the data, then the ECC process is used to correct the data in step 810 and the corrected data is reported to the user in step 812. If the data cannot be corrected by the ECC process, a data recovery process is performed at step 814. In some embodiments, the ECC process will be performed after step 814. After the data has been restored, the data is reported at step 816. It should be noted that the process of Figure 16 can be used with data programmed using all-bit programming or odd / even bitline programming.

18 is a flowchart illustrating a process for performing a read operation on a page. The process of FIG. 18 may be performed for a page covering all the bitlines of the block, only the odd bitlines of the block, only the even bitlines of the block, or other subsets of the bitlines of the block. In step 850, a read reference voltage Vra is applied to the appropriate word line associated with the page. In step 852, bit lines associated with the page are sensed to determine whether the addressed memory cells are conductive or not, based on applying Vra to their control gates. The conducting bit lines indicate that the memory cells are turned on, so the threshold voltages of these memory cells are lower than Vra (eg, state E). In step 854, the result of sensing for the bit lines is stored in the appropriate latches for these bit lines. In step 856, a read reference voltage Vrb is applied to word lines associated with the page being read. In step 858, the bitlines are sensed as described above. At step 860, the results are stored in the appropriate latches for these bit lines. In step 862, a read reference voltage Vrc is applied to word lines associated with the page. In step 864, the bit lines are sensed as described above to determine which memory cells are conductive. In step 866, the results of the sense step are stored in the appropriate latches for these bit lines. In step 868, data values for each bitline are determined. For example, if a memory cell is conductive at Vra, the memory cell is in state E. If the memory cell is conductive at Vrb and Vrc but not at Vra, the memory cell is in state A. If the memory cell is conductive at Vrc but not at Vra and Vrb, the memory cell is in state B. If the memory cell is not conductive at Vra, Vrb or Vrc, the memory cell is in state C. In other embodiments, sensing the various levels Vra, Vrb and Vrc may be performed in a different order.

Depending on the coding and / or architecture applied, different numbers of read reference voltages may need to be applied in various embodiments. For example, if the upper page / lower page structure applies, as long as the memory cell is in one of states E and A (high page bit = 1) or one of states B and C (high page bit = 0). By simply using the read reference voltage Vrb to determine if it is in a state, the upper page read may be completed. The lower page read may be completed by using the Vra and Vrc read reference voltage levels, which indicate whether the memory cell is in one of states E and C (lower page bit = 1) or states A and B (lower page bit). = 0) to determine if one is in a state.

Although a NAND type flash memory has been described mainly for illustrative purposes, the present invention is not limited thereto and has application to various types of integrated circuits. Basically, embodiments of the present invention can be used in any type of circuits that include an addressable die. Other embodiments may include NOR type flash memory and volatile memory such as SRAM and DRAM. In addition, the foregoing detailed description is provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. In order to best explain the technical idea of the present invention and its practical application, embodiments of the present invention have been selected. Accordingly, those skilled in the art will be able to best utilize the present invention through various embodiments, and best utilize various modifications suitable for the specific application under consideration. The scope of the invention should be defined by the appended claims.

202: memory die
214: Bonding Pad
216 device select pin
218: second group of pins (or pinouts)
240: programmable chip address circuit
242: Programmable Chip Enable Circuit

Claims (18)

As a manufacturing method of a nonvolatile reservoir,
Packaging a plurality of nonvolatile memory chips and a controller in a memory package, the memory package including a common chip enable line connected to each of the nonvolatile memory chips and the controller, wherein the common chip The plurality of nonvolatile memory chips are enabled in response to a chip enable signal provided on an enable line;
After the packaging, determining whether the plurality of nonvolatile memory chips are defective; And
If it is determined that a particular memory chip is defective during the determining, isolating the particular memory chip of the plurality of nonvolatile memory chips to prevent the specific memory chip from being enabled in response to the chip enable signal. ) step
Method for producing a nonvolatile reservoir comprising a. The method of claim 1,
Isolating the specific memory chip,
And overriding said chip enable signal for said particular memory chip. The method of claim 1,
Each of the plurality of nonvolatile memory chips includes a chip enable pin, a select circuit, and one or more programmable circuits connected between the chip enable pin and the select circuit, wherein the chip enable signal is the chip in Received on the enable pin;
Isolating the particular memory chip comprises programming the one or more programmable circuits to provide a substantially constant bias from the chip enable pin to the selection circuit independent of the chip enable signal. A method of producing a nonvolatile reservoir. The method of claim 3,
The one or more programmable circuits are one or more programmable first circuits;
Each of the memory chips comprises a set of one or more device select pins and one or more programmable second circuits, the one or more device select pins connected to a set of one or more pads, the one or more programmable second circuits Connected between one or more device select pins and the select circuit;
The method further includes defining a unique address for each of the memory chips using a predetermined configuration for the set of one or more pads, wherein the selection circuitry of each memory chip comprises: And comparing the address received from the controller with the unique address received on the set of one or more device selection pins to determine if selected. The method of claim 4, wherein
The method further comprises replacing the unique address of a second memory chip with another address if it is determined that the particular memory chip is defective;
The replacing step may be performed for the second memory chip to provide the other address to the selection circuitry of the second memory chip in place of the unique address received from the set of pads through the one or more device select pins. Setting up said at least one programmable second circuit. The method of claim 5,
Configuring the one or more programmable second circuits for the second memory chip,
Programming one or more fuses to define the other address, the other address being provided from the one or more fuses to the selection circuit and the other address invalidating the unique address received from the set of pads. (Override) The manufacturing method of a nonvolatile reservoir characterized by the above-mentioned. The method of claim 3,
Wherein said at least one programmable first circuit is at least one fuse. The method of claim 7, wherein
Wherein said at least one fuse comprises at least one of an anti-fuse, a laser fuse, and an electrically blowable fuse. The method of claim 1,
Wherein each memory chip comprises a nonvolatile NAND memory array. A nonvolatile memory system,
A plurality of nonvolatile memory chips, each comprising a plurality of nonvolatile reservoirs and one or more chip enable pins, wherein the one or more chip enable pins of each memory chip are connected to a common line;
A controller in communication with the common line;
A selection circuit on each memory chip, responsive to a chip enable signal provided on the common line by the controller, each selection circuit enabling a corresponding memory chip in response to the chip enable signal; And
Set of one or more programmable circuits on each chip
It is made, including
Said set of programmable circuits are in communication with said chip enable pin and a selection circuit of a corresponding memory chip,
And said set of programmable circuits are configurable after packaging said nonvolatile memory system to isolate said corresponding memory chip not to be enabled in response to said chip enable signal. The method of claim 10,
And said set of programmable circuits isolate said corresponding memory chip by invalidating said chip enable signal prior to reaching said selection circuit of said corresponding memory chip. The method of claim 10,
And said set of programmable circuits isolate said corresponding memory chip by providing a substantially constant bias from said chip enable pin to said selection circuit independent of said chip enable signal. The method of claim 10,
Each memory chip includes one or more device select pins connected to a set of one or more pads for each chip, the set of pads for each chip having a predetermined configuration defining a unique address for each chip. Has;
Said set of one or more programmable circuits on each chip is a first set of one or more programmable circuits; And
Each chip further includes a second set of one or more device select pins and one or more programmable circuits in communication with the select circuit for each chip, wherein the second set of one or more programmable circuits for each memory chip Is configurable after packaging the nonvolatile memory system to define a different address for each of the memory chips. The method of claim 13,
The plurality of memory chips comprises a defective memory chip and a defect free first memory chip;
The first set of one or more programmable circuits for the defective chip is configured to isolate the defective memory chip so that it is not enabled in response to the chip enable signal; And
And said second set of one or more programmable circuits for said defect free first memory chip are configured to replace a unique address of said defect free first memory chip with a different address. The method of claim 14,
And the other address for the defect free first memory chip is a unique address of the defective memory chip. The method of claim 13,
The second set of one or more programmable circuits for a particular memory chip is configured to define another address by storing the other address, the other address being the predetermined configuration of the set of pads for the particular memory chip. And a selection circuit for the particular memory chip in place of the unique address defined by. The method of claim 16,
And the first set of one or more programmable circuits is one or more fuses. The method of claim 17,
And the at least one fuse comprises at least one of an anti-fuse, a laser fuse, and an electrically blowable fuse.

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