KR20090106011A - Method for fabricating pillar pattern - Google Patents

Method for fabricating pillar pattern Download PDF

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KR20090106011A
KR20090106011A KR1020080031471A KR20080031471A KR20090106011A KR 20090106011 A KR20090106011 A KR 20090106011A KR 1020080031471 A KR1020080031471 A KR 1020080031471A KR 20080031471 A KR20080031471 A KR 20080031471A KR 20090106011 A KR20090106011 A KR 20090106011A
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South Korea
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pillar
substrate
etching
forming
film
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KR1020080031471A
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Korean (ko)
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김명옥
조윤석
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주식회사 하이닉스반도체
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Priority to KR1020080031471A priority Critical patent/KR20090106011A/en
Publication of KR20090106011A publication Critical patent/KR20090106011A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Element Separation (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE: A method for fabricating a pillar pattern is provided to prevent a bird beak by preventing the insertion of a substrate with a thin etching barrier. CONSTITUTION: A method for fabricating a pillar pattern is comprised of the steps: forming a plurality of pillar heads(23) by etching a part of the substrate(21); forming an etch barrier(24) exposing a substrate between the pillar heads while being on the side wall of the pillar head; etching a part of substrate between pillar heads by using the etch barrier; forming a protection layer(25) on the side wall of the pillar head; and forming a pillar neck by etching the substrate with protection layer as each barrier.

Description

필라패턴 제조 방법{METHOD FOR FABRICATING PILLAR PATTERN}Pillar pattern manufacturing method {METHOD FOR FABRICATING PILLAR PATTERN}

본 발명은 반도체 소자의 제조 기술에 관한 것으로, 특히 채널을 상/하 방향으로 유도하기 위한 필라패턴의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor device, and more particularly, to a method of manufacturing a pillar pattern for guiding a channel in an up / down direction.

반도체 소자의 디자인룰(design rule)이 감소함에 따라 소스 및 드레인(source and drain)을 활성영역 내에 상/하로 배치시켜서 채널이 상/하 방향, 예컨대 수직방향으로 형성되는 반도체 소자가 제안되었다. 그리고, 상/하 방향의 채널은 기둥형상의 필라패턴에 형성된다.As a design rule of a semiconductor device decreases, a semiconductor device in which a channel is formed in an up / down direction, for example, a vertical direction by disposing source and drain up and down in an active region has been proposed. The up / down channels are formed in the pillar-shaped pillar pattern.

도 1a 및 도 1b는 종래기술에 따라 채널이 상/하 방향으로 형성되는 반도체 소자의 필라패턴 제조 방법을 나타낸 공정단면도이다.1A and 1B are cross-sectional views illustrating a method of manufacturing a pillar pattern of a semiconductor device in which channels are formed in an up / down direction according to the related art.

도 1a에 도시된 바와 같이, 기판(11)에 복수의 게이트 하드마스크막(12)을 형성한후, 이를 식각장벽으로 기판(11)을 식각하여 필라헤드(13, pillar head)를 형성한다.As shown in FIG. 1A, after forming a plurality of gate hard mask layers 12 on the substrate 11, the pillar 11 is formed by etching the substrate 11 using an etch barrier.

도 1b에 도시된 바와 같이, 기판(11)의 단차를 따라 절연막을 형성하고, 전 면식각 공정을 진행하여 필라헤드(13)의 측벽을 보호하는 측벽보호막(15)을 형성한다.As shown in FIG. 1B, an insulating film is formed along the step of the substrate 11, and a front side etching process is performed to form a sidewall protective film 15 that protects the sidewall of the pillar head 13.

이어서, 측벽보호막(15A)을 식각장벽으로 기판(11)을 식각하여 필라넥(16)을 형성한다. 이로써, 필라헤드(13)와 필라넥(16)을 포함하는 필라패턴이 형성된다.Subsequently, the pillar 11 is formed by etching the substrate 11 using the sidewall passivation layer 15A as an etch barrier. As a result, a pillar pattern including the pillar head 13 and the pillar neck 16 is formed.

그러나, 필라헤드(13)를 형성하는 과정에서, 필라헤드(13) 바닥면 외측의 기판(11)은 기운(14, slope)형상을 갖게 되고, 이후, 필라넥(16)을 형성하는 과정에서 버즈비크(14A, bird beak)형상으로 변형된다.However, in the process of forming the pillar head 13, the substrate 11 outside the bottom surface of the pillar head 13 has a slope shape 14, and then in the process of forming the pillar neck 16. It is deformed to a bird beak 14A shape.

도 2는 버즈비크 형상(14A)을 촬영한 전자현미경 사진으로, 이를 참조하면 필라헤드(13)와 필라넥(16) 경계지역의 형상이 버즈비크(14A)인 것을 확인할 수 있다.FIG. 2 is an electron microscope photograph of a 14B of Buzzbeek. Referring to this, it can be seen that the shape of the boundary between the pillar head 13 and the pillarneck 16 is Buzzbeek 14A.

이와 같은 버즈비크(14A)형상은 전계(electric field)를 집중시켜 반도체 소자의 특성을 열화시킬 뿐만 아니라, 필라헤드(13)와 필라넥(16)의 폭, 직경등의 수치를 왜곡시켜 후속 게이트 전극의 형성을 어렵게 하는 문제점을 발생시킨다.The shape of the Buzzbee 14A not only deteriorates the characteristics of the semiconductor device by concentrating an electric field, but also distorts numerical values such as the width and diameter of the pillar head 13 and the pillar neck 16, thereby causing subsequent gates. A problem arises that makes the formation of the electrode difficult.

본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로서, 필라헤드를 형성하는 과정에서 형성되는 기판의 기움형상을 제거하는 필라패턴 제조 방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a pillar pattern manufacturing method for removing the shape of the substrate formed in the process of forming the pillar head.

상기의 목적을 달성하기 위한 본 발명의 필라패턴 제조 방법은 기판의 일부를 식각하여 복수의 필라헤드를 형성하는 단계, 상기 필라헤드의 측벽에 형성되어 상기 필라헤드 사이의 기판을 노출시키는 식각장벽막을 형성하는 단계, 상기 식각장벽막을 이용하여 상기 필라헤드 사이의 기판 일부를 식각하는 단계, 상기 필라헤드의 측벽에 측벽보호막을 형성하는 단계 및 상기 측벽보호막을 식각장벽으로 기판을 식각하여 필라넥을 형성하는 단계를 포함한다.The pillar pattern manufacturing method of the present invention for achieving the above object is to form a plurality of pillar head by etching a portion of the substrate, an etching barrier film formed on the sidewall of the pillar head to expose the substrate between the pillar head Forming a portion of the substrate between the pillar heads using the etching barrier layer, forming a sidewall protective layer on the sidewall of the pillarhead, and etching the substrate using the sidewall protective layer as an etch barrier to form a pillarneck. It includes a step.

상술한 바와 같은 과제 해결 수단을 바탕으로 하는 본 발명은, 얇은 두께의 식각장벽막을 이용하여 기판의 기움형상을 제거하고, 나아가 버즈비크 형상을 방지한다.The present invention, which is based on the above-mentioned means for solving the problems, removes the shape of the substrate by using an etch barrier film having a thin thickness, and further prevents the shape of the burj beak.

따라서, 전계 집중에 따른 반도체 소자의 특성 열화를 방지하며, 반도체 소자의 수율을 증가시킬 수 있는 효과를 갖는다.Therefore, it is possible to prevent the deterioration of characteristics of the semiconductor device due to the concentration of the electric field, and to increase the yield of the semiconductor device.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위해 본 발명의 가장 바람직한 실시예를 첨부한 도면을 참조하여 설명한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

도 3a 내지 도 3d는 본 발명의 실시예에 따라 채널이 상/하 방향으로 형성되는 반도체 소자의 필라패턴 제조 방법을 나타낸 공정단면도이다.3A to 3D are cross-sectional views illustrating a method of manufacturing a pillar pattern of a semiconductor device in which a channel is formed in an up / down direction according to an exemplary embodiment of the present invention.

도 3a에 도시된 바와 같이, 기판(21)에 복수의 게이트 하드마스크막패턴(22)을 형성하고, 이를 식각장벽으로 기판(21)을 식각하여 필라헤드(23, pillar head)를 형성한다.As shown in FIG. 3A, a plurality of gate hard mask layer patterns 22 are formed on the substrate 21, and the pillar 21 is formed by etching the substrate 21 using an etch barrier.

게이트 하드마스크막패턴(22)은 질화막 또는 질화막과 산화막의 적층구조로 형성하며, 게이트 하드마스크막패턴(22)과 기판(21)과의 박막 스트레스(film stress)를 완화하고자 패드 산화막(pad oxide)을 개재할 수 있다. The gate hard mask layer pattern 22 is formed of a nitride structure or a stacked structure of a nitride layer and an oxide layer, and pad oxide film is used to relieve film stress between the gate hard mask layer pattern 22 and the substrate 21. ) Can be intervened.

여기서, 게이트 하드마스크막패턴(22)으로 사용하는 질화막은 LPCVD(Low Pressure Chemical Vapor Deposition) 방식으로 형성하고, 산화막은 LPTEOS(Low Pressure Tetra Ethyl Ortho Silicate), PETEOS(Plasma Enhanced Tetra Ethyl Ortho Silicate), 열산화막(thermal oxide), HTO(High Temperature deposition of Oxide) 및 MTO(Medium Temperature deposition of Oxide)으로 이루어진 그룹 중에서 선택된 어느 하나의 박막으로 형성한다.Here, the nitride film used as the gate hard mask film pattern 22 is formed by a low pressure chemical vapor deposition (LPCVD) method, and the oxide film is LPTEOS (Low Pressure Tetra Ethyl Ortho Silicate), PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), It is formed of any one thin film selected from the group consisting of a thermal oxide (thermal oxide), high temperature deposition of oxide (HTO) and medium temperature deposition of oxide (MTO).

그리고, 게이트 하드마스크막패턴(22)은 원(circular type) 형상을 갖는다.The gate hard mask film pattern 22 has a circular shape.

이어서, 필라헤드(23)와 게이트 하드마스크막패턴(22)의 측벽에 식각장벽 막(24)을 형성한다.Subsequently, an etch barrier film 24 is formed on sidewalls of the pillar head 23 and the gate hard mask film pattern 22.

식각장벽막(24)은 플라즈마 산화(plasma oxidation) 공정을 진행하여 형성한후, 비등방성 식각공정을 진행하여 형성한다. 여기서, 플라즈마 산화 공정은 N2와 O2 플라즈마를 이용하고, 필라헤드(23)를 형성하는 챔버 내에서 인시츄(insitu)로 진행한다. 또는 포토레지스트 스트립퍼(stripper)에서 진행한다.The etching barrier film 24 is formed by performing a plasma oxidation process and then an anisotropic etching process. Here, the plasma oxidation process uses N 2 and O 2 plasma, and proceeds in situ in the chamber forming the pillar head 23. Or in a photoresist stripper.

위와 같이 플라즈마 산화 공정을 진행하게 되면, 10~30Å의 얇은 식각장벽막(24)이 형성되는데, 이는 종래기술에 해당하는 도 1b의 측벽보호막(15)의 두께에 비해 상대적으로 얇은 두께이다. 도 1b의 측벽보호막(15)은 80~150Å의 두께를 갖바, 이 두꺼운 두께로 인해 기판의 기운형상을 보호하고, 이에 따라 버즈비크 형상을 유발한다. 그러나, 식각장벽막(24)은 얇은 두께를 갖기 때문에 기판(21)의 기운형상(A)을 노출시킬 수 있다.When the plasma oxidation process is performed as described above, a thin etch barrier film 24 having a thickness of 10 to 30 μs is formed, which is relatively thin compared to the thickness of the sidewall protective film 15 of FIG. 1B corresponding to the prior art. The side wall protective film 15 of FIG. 1B has a thickness of 80 to 150 kPa, which protects the shape of the substrate due to the thick thickness, thereby inducing a buzz beak shape. However, since the etch barrier film 24 has a thin thickness, the shape A of the substrate 21 may be exposed.

도 3b에 도시된 바와 같이, 식각장벽막(24)을 식각장벽으로 기판(21)을 식각하여 기운형상(A)을 제거한다.As shown in FIG. 3B, the substrate 21 is etched using the etch barrier 24 to remove the aura shape A. Referring to FIG.

기운형상(A)의 제거를 위한 식각공정은 등방성 식각 공정으로 진행하는데, 얇은 두께의 식각장벽막(24)으로 인해 기운형상(A)이 노출된 상태이기 때문에 등방성 식각 공정에서 기운형상(A)은 제거된다. 그리고, 등방성 식각 공정은 20~200mTorr의 압력과 10~100W의 바이어스 파워(bias power)를 인가하여 등방성 조건(isotropic condition)을 만든 후, HBr, Cl2, SF6, CF4, O2, N2, He 및 Ar으로 이루어진 그룹 중에서 선택된 적어도 어느 하나의 가스를 사용하여 진행한다. 예를 들면, Cl2, O2 및 Ar의 혼합 가스를 사용할 수 있다.The etching process for removing the energy shape (A) proceeds to an isotropic etching process. Since the energy shape (A) is exposed due to the etch barrier film 24 having a thin thickness, the shape (A) in the isotropic etching process is exposed. Is removed. In the isotropic etching process, an isotropic condition is applied by applying a pressure of 20 to 200 mTorr and a bias power of 10 to 100 W. HBr, Cl 2 , SF 6 , CF 4 , O 2 , N It proceeds using at least one gas selected from the group consisting of 2 , He and Ar. For example, a mixed gas of Cl 2 , O 2 and Ar can be used.

그리고, 게이트 하드마스크막패턴(22)의 형성 공정부터, 기운형상(A)의 제거 공정까지 인시츄로 진행할 수 있다.Then, the process can be performed in situ from the formation process of the gate hard mask film pattern 22 to the removal process of the shape A.

도 3c에 도시된 바와 같이, 기운형상(A)이 제거된 기판(21)의 단차를 따라 절연막을 증착하고, 비등방성 식각 공정을 진행하여 측벽보호막(25)을 형성한다. 여기서, 측벽보호막(25)은 80~150Å의 두께를 갖으며, 절연막은 산화막 또는 질화막일 수 있다.As shown in FIG. 3C, an insulating film is deposited along the step of the substrate 21 from which the shape A is removed, and an anisotropic etching process is performed to form the sidewall protective film 25. Here, the sidewall protective film 25 has a thickness of 80 ~ 150Å, the insulating film may be an oxide film or a nitride film.

도 3d에 도시된 바와 같이, 측벽보호막(25)을 식각장벽으로 기판(21)을 등방성 식각하여 필라넥(26, pillar neck)을 형성한다. 이로써, 필라헤드(23)와 필라넥(26)을 포함하는 필라패턴이 제조된다.As shown in FIG. 3D, a pillar neck 26 is formed by isotropically etching the substrate 21 using the sidewall protective layer 25 as an etch barrier. As a result, a pillar pattern including the pillar head 23 and the pillar neck 26 is manufactured.

필라넥(26)의 형성은 Cl2, HBr 및 O2가 혼합된 식각가스를 이용한 기판(21)의 비등방성 식각과, CF4, SF6 및 Ar이 혼합된 식각가스를 이용한 기판(21)의 등방성 식각을 순차적으로 진행하여 형성하거나, 이들 기판(21)의 비등방성 식각과 등방성 식각을 반복 진행하여 형성한다.A substrate formation using a Cl 2, HBr and O 2 are anisotropic etching of the substrate 21 using a mixed etching gas and, CF 4, SF 6, and Ar is a mixed etching gas of the pillar-neck (26) (21) Isotropic etching is performed in order, or anisotropic etching and isotropic etching of these substrates 21 are repeated.

이때, 상위 공정에서 기판(21)의 기운형상(A)이 제거된 상태이기 때문에 도 4와 같이 버즈비크 형상은 형성되지 않는다. 도 4는 필라패턴의 제조 공정 완료 후, 필라패턴을 촬영한 전자현미경 사진으로, 이를 참조하면, 기판의 기운형상 나아가 버즈비크 형상이 없는 것을 확인할 수 있다.At this time, since the shape A of the substrate 21 is removed in the upper process, the Buzzbee shape is not formed as shown in FIG. 4. 4 is an electron micrograph photographing the pillar pattern after completion of the manufacturing process of the pillar pattern. Referring to this, it can be seen that there is no aura shape and a burj beak shape of the substrate.

전술한 바와 같은 본 발명의 실시예는, 필라헤드 사이 기판(21)의 기움형 상(A)을 제거하기 위해 얇은 두게의 식각장벽막(24)을 형성한 후, 이를 식각장벽으로 기판(21)의 기움형상(A)을 식각한다.According to the embodiment of the present invention as described above, in order to remove the angular phase A of the substrate 21 between the pillar heads, a thin etch barrier film 24 is formed, and then the substrate 21 is used as an etch barrier. Etch the shape (A) of

따라서, 기움형상(A)은 제거되며, 나아가 기판(21)의 버즈비크 형상의 발생을 방지한다.Therefore, the shape A is removed, further preventing the occurrence of the buzz beak shape of the substrate 21.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

도 1a 및 도 1b는 종래기술에 따라 채널이 상/하 방향으로 형성되는 반도체 소자의 필라패턴 제조 방법을 나타낸 공정단면도.1A and 1B are cross-sectional views illustrating a method of manufacturing a pillar pattern of a semiconductor device in which channels are formed in an up / down direction according to the related art.

도 2는 버즈비크 형상(14A)을 촬영한 전자현미경 사진.FIG. 2 is an electron microscope photograph of a burj beak shape 14A. FIG.

도 3a 내지 도 3d는 본 발명의 실시예에 따라 채널이 상/하 방향으로 형성되는 반도체 소자의 필라패턴 제조 방법을 나타낸 공정단면도.3A to 3D are cross-sectional views illustrating a method of manufacturing a pillar pattern of a semiconductor device in which a channel is formed in an up / down direction according to an exemplary embodiment of the present invention.

도 4는 필라패턴의 제조 공정 완료 후, 필라패턴을 촬영한 전자현미경 사진.4 is an electron microscope photograph of the pillar pattern after completion of the pillar pattern manufacturing process.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

21 : 기판 22 : 게이트 하드마스크막패턴21 substrate 22 gate hard mask film pattern

23 : 필라헤드 24 : 식각장벽막23: pillar head 24: etching barrier

25 : 측벽보호막 26 : 필라넥25 sidewall protective film 26

Claims (7)

기판의 일부를 식각하여 복수의 필라헤드를 형성하는 단계;Etching a portion of the substrate to form a plurality of pillar heads; 상기 필라헤드의 측벽에 형성되어 상기 필라헤드 사이의 기판을 노출시키는 식각장벽막을 형성하는 단계; Forming an etch barrier film formed on sidewalls of the pillar head to expose a substrate between the pillar heads; 상기 식각장벽막을 이용하여 상기 필라헤드 사이의 기판 일부를 식각하는 단계;Etching a portion of the substrate between the pillar heads using the etching barrier layer; 상기 필라헤드의 측벽에 측벽보호막을 형성하는 단계; 및Forming a sidewall protective film on sidewalls of the pillar head; And 상기 측벽보호막을 식각장벽으로 기판을 식각하여 필라넥을 형성하는 단계Etching the substrate using the sidewall protective layer as an etch barrier to form a pillar neck; 를 포함하는 필라패턴 제조 방법.Pillar pattern manufacturing method comprising a. 제1항에 있어서,The method of claim 1, 상기 식각장벽막은 The etching barrier is 상기 필라헤드 사이 기판의 기움형상을 노출시키는 것을 특징으로 하는 필라패턴 제조 방법.A pillar pattern manufacturing method, characterized in that to expose the shape of the substrate between the pillar head. 제1항에 있어서,The method of claim 1, 상기 식각장벽막은 10~30Å의 두께로 형성되는 필라패턴 제조 방법.The etching barrier film is a pillar pattern manufacturing method is formed to a thickness of 10 ~ 30Å. 제1항에 있어서,The method of claim 1, 상기 식각장벽막은 플라즈마 산화 공정으로 산화막을 형성한 후, 비등방성 식각 공정을 진행하여 형성하는 필라패턴 제조 방법.The etching barrier film is a pillar pattern manufacturing method is formed by performing an anisotropic etching process after forming the oxide film by a plasma oxidation process. 제4항에 있어서,The method of claim 4, wherein 상기 플라즈마 산화 공정은 N2와 O2 플라즈마를 이용하는 필라패턴 제조 방법.The plasma oxidation process is a pillar pattern manufacturing method using N 2 and O 2 plasma. 제4항에 있어서,The method of claim 4, wherein 상기 플라즈마 산화 공정은 상기 필라헤드를 형성하는 챔버 내에서 인시츄(insitu)로 진행하거나, 포토레지스트 스트립퍼(stripper)에서 진행하는 필라패턴 제조 방법.The plasma oxidation process is performed in-situ in the chamber forming the pillar head, or the pillar pattern manufacturing method proceeds in a photoresist stripper. 제1항에 있어서,The method of claim 1, 상기 식각장벽막을 이용하여 기판의 일부를 식각하는 단계는, 등방성 식각 공정으로 진행하는 필라패턴 제조 방법.Etching a portion of the substrate using the etching barrier film, the pillar pattern manufacturing method proceeds to an isotropic etching process.
KR1020080031471A 2008-04-04 2008-04-04 Method for fabricating pillar pattern KR20090106011A (en)

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