KR20090104449A - Flash memory device using dummy cell and driving method thereof - Google Patents

Abstract

PURPOSE: A flash memory device using a dummy cell and an operating method thereof are provided to reduce a verification time and a read time by including a dummy cell inside a string cell. CONSTITUTION: A flash memory device(100) includes a plurality of strings(10). The plurality of strings have first memory cells and second memory cells. One of the second memory cells belonging to each string is programmed. The remaining of the second memory cells is erased. The read voltage is applied to the programmed second memory cells during the read/verification operation.

Description

Flash memory device using dummy cell and its operation method {FLASH MEMORY DEVICE USING DUMMY CELL AND DRIVING METHOD THEREOF}

The present invention relates to a flash memory device, and more particularly, to a method for programming verification of a flash memory device using a dummy cell.

A flash memory device of a general All Bit Line (ABL) architecture programs all bit lines (BL) at a time. In detail, a flash memory device having an All Bit Line (ABL) architecture may program 8Kbytes simultaneously, and divide or verify 4Kbytes twice at a time.

The reason why a flash memory device having an all-bit line (ABL) structure verifies or reads cells programmed at a time by dividing them in two times is firstly programmed or erased in the same word line. If cells are adjacent to each other, an incorrect read operation may occur due to a coupling capacitor between neighboring bit lines. Second, a bias voltage of a source to which all bit lines are commonly connected may not be kept constant. Because. The above description of the above-described flash memory device having an all-bit line (ABL) structure is described in US Patent US 7,023,736 filed by Scandisk.

Accordingly, since the flash memory device having the all-bit line (ABL) structure continuously verifies or reads the bit line, a problem arises in that the programming verification or read time is increased.

SUMMARY OF THE INVENTION An object of the present invention is to provide an apparatus and a method of verifying the same, which reduces verification or read time in a flash memory having an all-bit line structure.

A flash memory device according to an embodiment of the present invention includes a plurality of strings each having first memory cells and second memory cells, and any one of the second memory cells belonging to each string is set to a programmed state. And the rest of the second memory cells are set to the erased state.

In an embodiment, the second memory cells are dummy cells.

In an embodiment, only one of the second memory cells belonging to the same row is set to the programmed state, and the other is set to the erased state.

In an embodiment, a read voltage is applied to the second memory cells set to the programmed state during the read / verify operation.

In an embodiment, during the read / verify operation, the strings are precharged simultaneously.

In an embodiment, the strings are read N times.

In an embodiment, the second memory cells belonging to each string are selectively programmed after an erase operation and a verify operation.

In an embodiment, the number of second memory cells is determined according to the number of reads.

A method of operating a flash memory device according to an embodiment of the present invention is a method of operating a flash memory device including a plurality of strings, the method comprising: precharging strings each having first memory cells and second memory cells simultaneously; ; Sensing first strings of the strings; And sensing second strings of the strings, wherein one of the second memory cells belonging to each string is set to a programmed state, and the other of the second memory cells is set to an erased state. do.

In an embodiment, the second memory cells are dummy cells.

In an embodiment, only one of the second memory cells belonging to the same row is set to the programmed state, and the other is set to the erased state.

In an embodiment, a read voltage is applied to the second memory cells set to the programmed state during the read / verify operation.

In an embodiment, the number of second memory cells is determined according to the number of reads.

In an embodiment, the operation method includes a read operation and a verify operation.

The flash memory device according to the present invention has an effect of reducing a verification or read time by including a dummy cell in a string cell.

Example 1

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

1 is a block diagram illustrating a flash memory device according to the present invention.

Referring to FIG. 1, an embodiment according to the present invention is a flash memory device having an All Bit Line (ABL) structure. That is, the flash memory device 100 according to the present invention programs all the bit lines BL at a time, and reads all the bit lines by dividing them at several times.

The flash memory device 100 according to the present invention includes a plurality of string cells 10, a page buffer 20, a row decoder 30, and a control logic 40. do.

Each of the string cells 10 includes first and second dummy cells DC1 and DC2 and a plurality of normal cells. The page buffer 20 is used to write or read data in the plurality of string cells 10. The row decoder 30 receives an address ADDR from an external device (eg, a memory controller). The row decoder 30 selects a word line WL corresponding to the address ADDR to the plurality of string cells 10. The control logic 40 generates a control signal CNTR to control the write operation and the read operation of the page buffer 20.

Each of the string cells 10 according to an embodiment of the present invention includes the same number of dummy cells as the number of reads. For example, the flash memory device 100 according to the present invention programs 8 Kbytes at a time, and reads a plurality of string cells 10 by 4 Kbytes at a time. Each of the string cells 10 according to the embodiment of the present invention includes two dummy cells.

FIG. 2 is a circuit diagram illustrating some of the string cells 10 illustrated in FIG. 1.

Referring to FIG. 2, the string cells 10 according to the present invention include first to fourth bit lines BL1 to BL4. Each of the first to fourth bit lines BL1 to BL4 includes two dummy cells. That is, the first bit line BL1 includes first and second dummy cells DC1 and DC2. The second bit line BL2 includes third and fourth dummy cells DC3 and DC4. The third bit line BL3 includes fifth and sixth dummy cells DC5 and DC6. The fourth bit line BL4 includes seventh and eighth dummy cells DC7 and DC8.

The second, third, sixth, and seventh dummy cells DC2, DC3, DC6, and DC7 are programmed, and the first, fourth, fifth, and eighth dummy cells DC1, DC4, DC5, and DC8 are programmed. Is in the erased state. Programming operations of the first to eighth dummy cells DC1 to DC8 are described in detail with reference to FIG. 3. The verification operation of the string cell 10 including the dummy cell shown in FIG. 2 is described in detail in FIG. 4.

The positions of the first to eighth dummy cells DC1 to DC8 according to the embodiment of the present invention are located between the plurality of normal cells. In addition, the position of the dummy cells according to another embodiment of the present invention is shown in FIG.

3 is a flowchart illustrating a program order of the dummy cell shown in FIG. 2.

1 and 3, in the flash memory device 100 according to an embodiment of the present invention, the first to fourth bit lines BL1 to BL4 in the string cell 10 are erased (S01) and erased. It is verified that (S02). When the verification is completed (S03), the flash memory device 100 according to the embodiment of the present invention programs the first, third, fifth and seventh dummy cells DC1, DC3, DC5, and DC7 (S04). The second, fourth, sixth, and eighth dummy cells DC2, DC4, DC6, and DC8 are erased (S05).

4 is a timing diagram illustrating a verification operation of a flash memory device according to an exemplary embodiment of the present invention.

The flash memory device 100 according to an exemplary embodiment of the present invention describes an operation of programming the string cell 10 at once and dividing all the bit lines at twice.

1 to 4, during the time T1, the verification method according to the present invention initializes the first and second bit lines BL1 and BL2 to the ground voltage GND simultaneously. In order to sense the first bit line BL1, the word line D_WL1 of the first dummy cell DC1 applies a ground voltage GND and the word line D_WL2 of the second dummy cell DC2. Applies a read voltage Vrd. In addition, the selected word line applies a verify voltage, and the unselected word line applies a read voltage Vrd.

The read voltage Vrd illustrated in the present invention should be higher than the threshold voltage Vth of all the cells in the string cell. This is because the blocking of the second bit line BL2 is removed by blocking the sensing of the second bit line BL2 during the sensing period of the first bit line BL1.

During the time T2, the verification method according to the present invention simultaneously precharges the first and second bit lines BL1 and BL2. When the first and second bit lines BL1 and BL2 are precharged at the same time, there is no coupling capacitor between the bit lines, thereby reducing the precharge time.

During the time T3, the verification method according to the present invention senses the first bit line BL1. Since the ground voltage GND is applied to the first dummy cell DC1 and the read voltage Vrd is applied to the second dummy cell DC2, the page buffer 20 selects the selected word of the first bit line BL1. The cell current of the line is sensed.

The ground voltage GND is applied to the third dummy cell DC3, and the read voltage Vrd is applied to the fourth dummy cell DC4. Therefore, since the second bit line BL2 is blocked by the third dummy cell DC3, the second bit line BL2 maintains the precharge voltage. That is, the page buffer 20 continues to apply the precharge voltage to the second bit line BL2.

During the time T4, the verification method according to the present invention discharges the first bit line BL1 to the ground voltage GND. At this time, the second bit line BL2 continues to maintain the precharge voltage.

During the time T5, the verification method according to the present invention senses the second bit line BL2. Since the second bit line BL2 is in the precharge voltage state, the page buffer 20 may directly sense the second bit line BL2.

The read voltage Vrd is applied to the third dummy cell DC3, and the ground voltage GND is applied to the fourth dummy cell DC4. Therefore, the page buffer 20 senses the cell current of the selected word line of the second bit line BL2. Since the read voltage Vrd is applied to the first dummy cell DC1 and the ground voltage GND is applied to the second dummy cell DC2, the first bit line BL1 is connected to the second dummy cell DC2. Is blocked.

During the time period T6, the verification method according to the present invention discharges the second bit line BL2 to the ground voltage GND, and ends the verification operation.

Since the verification operation according to the present invention precharges all the bit lines at the same time, since there is no coupling capacitor between the bit lines, the verification operation can be reduced because the precharging time can be reduced and the precharge time of the second bit line can be skipped. Reduce time. In addition, the verification operation according to the present invention can be equally applied to the read operation.

Accordingly, the flash memory device according to the present invention has an effect of reducing a verification or read time by including a dummy cell in the string cell.

FIG. 5 shows the MLC program of the dummy cell shown in FIG. 2, and FIG. 6 shows the SLC program of the dummy cell shown in FIG.

2, 5 and 6, the first to eighth dummy cells DC1 to DC8 according to an embodiment of the present invention may be programmed as a multi-level cell (MLC) as shown in FIG. It is programmed as a Single Level Cell (SLC) as shown.

The first to eighth dummy cells DC1 to DC8 according to an embodiment of the present invention are programmed with SLC.

7 is a circuit diagram illustrating a dummy cell of a string cell according to a second embodiment of the present invention. Referring to FIG. 7, the string cell 110 according to the second embodiment of the present invention includes normal cells between two dummy cells.

For example, the first bit line BL1 includes a normal cell between the first dummy cell DC1 and the second dummy cell DC2, and the second bit line BL2 is the third dummy cell DC3. And a normal cell between the fourth dummy cell DC4 and the third bit line BL3 includes a normal cell between the fifth dummy cell DC5 and the sixth dummy cell DC6, and the fourth bit. The line BL4 includes a normal cell between the seventh dummy cell DC7 and the eighth dummy cell DC8.

The position of the dummy cell according to the present invention can be arbitrarily determined within the string cell.

In general, the string cell includes dummy cells at both ends of the normal cells in order to make the characteristics of the normal cells at both ends the same as the normal cells located in the middle. That is, the flash memory device according to the embodiment of the present invention uses dummy cells located at both ends.

8 is a circuit diagram illustrating a dummy cell of a string cell according to a third embodiment of the present invention. It is assumed that the flash memory device according to the third embodiment of the present invention divides and verifies all the bit lines at four times.

Referring to FIG. 8, the flash memory device according to the third exemplary embodiment sequentially verifies the first to fourth bit lines BL1 -BL4.

Each of the first to fourth bit lines BL1 to BL4 includes four dummy cells. That is, the first bit line BL1 includes first to fourth dummy cells DC01 to DC04, and the second bit line BL2 includes fifth to eighth dummy cells DC05 to DC08, The third bit line BL3 includes the ninth through twelfth dummy cells DC09-DC12, and the fourth bit line BL4 includes the thirteenth through sixteenth dummy cells DC13-DC16.

The first, sixth, eleventh, and sixteenth dummy cells DC01, DC06, DC11, and DC16 are programmed, and the remaining dummy cells DC2, DC3, DC4, DC5, DC7, DC8, DC9, DC10, and DC12 are programmed. , DC13, DC14, and DC15 are in an erased state.

Verification operations of the first to fourth bit lines BL1 to BL4 are the same as those described with reference to FIG. 4. That is, a read voltage is applied to the programmed dummy cells of the bit lines to be read among the first to fourth bit lines BL1 to BL4, and a ground voltage is applied to the erased dummy cells. In addition, a ground voltage is applied to a programmed dummy cell of a non-read bit line, and a read voltage is applied to an erased dummy cell. Therefore, the first to fourth bit lines BL1 to BL4 are simultaneously precharged and sequentially sensed.

9 is a block diagram showing a flash memory system including the first to third embodiments of the present invention.

9, a flash memory system 1000 according to an exemplary embodiment of the present invention includes a flash memory device 100, a flash memory controller 200, and a host 300.

The flash memory controller 200 may include a central processing unit (CPU) 210, a memory interface 220, an error correction code 230, a random access memory 240, and a host. A host interface 250, a read only memory 260, and a bus 270.

The flash memory device 100 according to the embodiment of the present invention includes the dummy cells shown in FIGS. 1, 7, and 8.

In FIG. 9, the flash memory controller 200 and the flash memory device 100 may be included in one storage device. Such storage devices also include removable storage devices such as USB memory and memory cards (Multi_Media Card (MMC), SD card, xD card, CF card, SIM card, etc.). In addition, such a storage device is connected to a host 110 such as a computer, a notebook, a digital camera, a mobile phone, an MP3 player, a portable multimedia player (PMP), a game machine, or the like.

When the flash memory controller 200 receives a read request for the flash memory device 100 from the host 300, the flash memory controller 200 selects a word line WL of the flash memory device 100 and performs a read operation.

The CPU 210 is configured to control a read or write operation of the flash memory device 100 in response to a request from the host 300.

The memory interface 220 is configured to interface with the flash memory device 100.

The error correction code 230 generates ECC data using data (main data) transmitted to the flash memory device 100. The ECC data thus generated is stored in a spare area of the flash memory 100. The error correction code 230 detects an error of data read from the flash memory device 100. If the detected error is within the correction range, the error correction code 230 corrects the detected error. The error correction code 230 may be located in the flash memory device 100 or may be located outside the flash memory controller 200 according to the flash memory system 1000.

The host interface 250 is configured to interface with the host 300.

The ROM 260 stores data such as a boot code and the like, and the RAM 240 is used as a buffer memory. The RAM 240 temporarily stores data read from the flash memory device 100 or data provided from the host 300. The RAM 240 also stores a Flash Translation Layer (FTL). The flash translation layer FTL is operated by the central processing unit 210. The RAM 240 may be implemented with DRAM, SRAM, or the like.

The bus 270 interconnects the CPU 210, the memory interface 220, the error correction code 230, the RAM 240, the host interface 250, and the ROM 260.

Here, the flash memory device 100 may store single bit data in one memory cell or may store multi bit data.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a block diagram illustrating a flash memory device according to the present invention.

FIG. 2 is a circuit diagram illustrating some of the plurality of string cells 10 shown in FIG. 1.

3 is a flowchart illustrating a program order of the dummy cell shown in FIG. 2.

4 is a timing diagram illustrating a verify operation of a flash memory device according to an embodiment of the present invention.

5 is an MLC program of the dummy cell shown in FIG. 2;

6 is an SLC program of the dummy cell shown in FIG. 2.

7 is a circuit diagram illustrating a dummy cell of a string cell according to a second embodiment of the present invention.

8 is a circuit diagram illustrating a dummy cell of a string cell according to a third embodiment of the present invention.

Fig. 9 is a block diagram showing a flash memory system including the first to third embodiments of the present invention.

Explanation of symbols on the main parts of the drawings

10: a plurality of string cells 20: page buffer

30: low decoder 40: control logic

100: flash memory device

Claims (14)

Each comprising a plurality of strings having first memory cells and second memory cells, One of the second memory cells belonging to each of the strings is set to a programmed state, and the other of the second memory cells is set to an erased state. The method of claim 1, And the second memory cells are dummy cells. The method of claim 1, Only one of the second memory cells belonging to the same row is set to the programmed state, the rest is set to the erased state. The method of claim 1, During the read / verify operation, a read voltage is applied to the second memory cells set to the programmed state. The method of claim 4, wherein During the read / verify operation, the strings are precharged simultaneously. The method of claim 5, wherein And the strings are read N times. The method of claim 1, And second memory cells belonging to each of the strings are selectively programmed after an erase operation and a verify operation. The method of claim 1, The number of the second memory cells is determined according to the number of reads. In the method of operating a flash memory device comprising a plurality of strings: Simultaneously precharging strings each having first memory cells and second memory cells; Sensing first strings of the strings; And Sensing second strings of the strings, One of the second memory cells belonging to each of the strings is set to a programmed state, and the other of the second memory cells is set to an erased state. The method of claim 9, And the second memory cells are dummy cells. The method of claim 9, Wherein only one of the second memory cells belonging to the same row is set to the programmed state, and the other is set to the erased state. The method of claim 9, During the read / verify operation, a read voltage is applied to the second memory cells set to the programmed state. The method of claim 9, The number of the second memory cells is determined according to the number of reads. The method of claim 9, The operation method includes a read operation and a verify operation.

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