KR20090102218A - Method for forming pattern of semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a pattern of a semiconductor device is provided to reduce misalignment using a spacer pattern method performing one mask process. CONSTITUTION: A hard mask layer including a silicon polymer is formed in an upper part of an etched layer(112) on a semiconductor substrate(110). A first photoresist pattern is formed in the upper part of the hard mask layer. A hard mask layer pattern(114a) is formed by etching the hard mask layer using the first photoresist pattern as the etching mask. A spacer layer(124) is formed in the upper part of the hard mask layer pattern. The spacer layer includes RELACS(Resist Enhancement Lithography Assisted by Chemical Shrink) material. A gap-fill layer(126) including the silicon polymer is formed in the etched layer including the spacer layer over the height of the hard mask layer pattern. The gap-fill layer is etched until the spacer layer is exposed. The gap-fill layer pattern is formed by removing the spacer layer. The etched layer pattern is formed by etching the etched layer using the gap-fill layer pattern and the hard mask layer pattern.

Description

Method for Forming Pattern of Semiconductor Device {Method for Forming Pattern of Semiconductor Device}

The present invention relates to a method of forming a pattern of a semiconductor device, and more particularly, to a method of forming a fine pattern of a semiconductor device using a simplified spacer patterning technology as a patterning technology for manufacturing a highly integrated device.

One method for improving the degree of integration of semiconductor devices is photolithography. This photolithography technique uses an exposure source using a short wavelength chemically amplified deep ultra violet (DUV) light source such as ArF (193 nm) or VUV (157 nm), and a photoresist material suitable for the exposure source. It is a technique of forming a pattern.

As the size of semiconductor devices becomes smaller and smaller, controlling the critical dimension of the pattern line width becomes an important problem when applying the photolithography technique. In general, the speed of a semiconductor device is faster as the critical dimension of the pattern line width, that is, the size of the pattern line is smaller, and the performance of the device is also improved.

However, due to the limitation of photolithography technology using ArF exposure equipment having a numerical aperture of 1.2 or less, it is difficult to form a line and space pattern of 40 nm or less in a single exposure process.

Thus, double exposure technology has been developed as part of resolution enhancement and process margin expansion of photolithography technology. This double exposure technique is a technique for exposing and developing two masks on a photoresist-coated wafer, respectively.

However, since the double exposure technique uses two different masks for patterning, the process is more complicated than using a single mask, the manufacturing cost and the efficiency against time are low, and the production rate is lowered. In addition, when a pattern having a pitch smaller than the resolution limit of the exposure equipment is formed in the cell area, the aerial image is overlapped to obtain a pattern of a desired shape, and overlay misalignment occurs during alignment. There are several disadvantages.

In order to alleviate this drawback, i) double patterning technology and ii) spacer patterning technology have been developed and applied to the semiconductor device mass production process.

1A to 1E are cross-sectional views illustrating a method of forming a pattern of a semiconductor device according to the prior art, and illustrate a method of forming a fine pattern by a conventional spacer patterning technique.

Referring to FIG. 1A, an etched layer 12 including a stacked structure of a plasma-enhanced tetraethyloxysilicate (PE-TEOS) oxide film, an amorphous carbon layer, a PE-TEOS oxide film, and a polysilicon layer is formed on the semiconductor substrate 10. After the formation, a stacked structure of the first hard mask film 14 made of an amorphous carbon layer, the second hard mask film 16 made of a silicon oxynitride film, and the antireflection film 18 is formed on the etched layer 12. .

Next, a positive or negative type photoresist composition is coated on the antireflection film 18 and then baked to form a photoresist film (not shown), and then subjected to exposure and development processes on the photoresist film to form a photoresist pattern. 20 is formed.

Referring to FIG. 1B, the antireflective film 18 and the second hard mask film 16 are etched using the photoresist pattern 20 as an etch mask to prevent the antireflective film pattern (not shown) and the second hard mask film pattern (not shown). ), And then, the first hard mask layer 14 is etched using the etching mask to form the first hard mask layer pattern 14a.

Referring to FIG. 1C, a nitride layer 22 for spacers is deposited by performing chemical vapor deposition (CVD) on the entire surface of the first hard mask layer 14 including the first hard mask layer pattern 14a.

Referring to FIG. 1D, a spacer 22a is formed on sidewalls of the first hard mask layer pattern 14a by etching the spacer nitride layer 22 by an etch back process.

Referring to FIG. 1E, after etching the first hard mask layer pattern 14a, the etched layer 12 may be etched using the remaining spacers 22a as an etch mask to form an etched layer pattern (not shown). .

As described above, in the case of using the spacer patterning technique according to the related art, a multilayer hard mask film of the first hard mask film 14 made of the amorphous carbon layer and the second hard mask film 16 made of the silicon oxynitride film is applied. Since the etching process must be repeated, the process is complicated, expensive, and process time is long.

In addition, as the line width of the spacer 22a becomes finer, the spacer 22a is deformed into a horn shape. Thus, when the lower etched layer 12 is etched, a horn shape is transferred and a pattern profile becomes poor. have.

FIG. 2 is a SEM photograph showing a method of forming a pattern of another semiconductor device according to the prior art, and shows that a low temperature oxide film 30 is formed on the photoresist pattern 20 in patterning using a spacer patterning technique.

However, as shown in FIG. 2, not only the photoresist pattern 20 is not formed in a vertical shape, but also the photoresist pattern 20 is deformed by the deposition of the low temperature oxide film 30.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and in the present invention, by using a spacer layer formed of a single-layer hard mask film and a release material containing a silicon-containing polymer instead of a multilayer hard mask film, An object of the present invention is to provide a method capable of forming a fine pattern of a semiconductor device by a spacer patterning technique.

Pattern formation method of a semiconductor device of the present invention for achieving the above object

Forming a hard mask film including a silicon-containing polymer on the etched layer on the semiconductor substrate;

Forming a first photoresist pattern on the hard mask layer;

Etching the hard mask layer using the first photoresist pattern as an etching mask to form a hard mask layer pattern;

Forming a spacer layer on the hard mask layer pattern, the spacer layer including a resist enhancement lithography assisted by chemical shrink (RELACS) material;

Forming a gap fill layer including a silicon-containing polymer on the entire upper surface of the etched layer including the spacer layer at a height greater than or equal to the height of the hard mask layer pattern;

Etching the gapfill layer on the entire surface until the spacer layer is exposed;

Removing the spacer layer to form a gap fill layer pattern; And

And etching the etched layer using the gap fill layer pattern and the hard mask layer pattern as an etch mask to form an etched layer pattern.

The forming of the hard mask layer may use a spin coating method.

The forming of the hard mask layer pattern may be performed using at least one plasma etching gas selected from the group consisting of CF ₄ , CHF ₃ , O _2, and Ar.

The hard mask layer and the gapfill layer may include a silicon-containing polymer, an organic solvent, and an additive, wherein the silicon-containing polymer includes a Si-Si-O- structure, a siloxane compound, (hydroxy phenylalkyl) It may be a ladder type silicone copolymer selected from the group consisting of a silsesquioxane compound, an alkyl silsesquioxane compound or a phenyl silsesquioxane compound and combinations thereof.

In addition, the gapfill layer may include a silicon-containing polymer, an organic solvent and a photoacid generator, wherein the salicon-containing polymer may be a polymer including a polymerization repeating unit represented by Formula 1 below:

[Formula 1]

Where

R is hydrogen or methyl; R ₁ is C ₂ -C ₁₀ straight or branched alkylene; R ₂ , R ₃ And R ₄ is a C ₁ to C ₃ alkoxy group; R ₅ is a protective group sensitive to acid or alkyl of OH, H or _{C 1 ~C 10, a: b} : relative ratio (mol) of c is from 0.3 to 1: 1 to 3: 1.

Forming the spacer layer may include baking at a temperature of 80 ° C to 150 ° C after applying the release material.

Removing the spacer layer may use a thinner or developer.

In the present invention, a single-layer hard mask film containing a silicon-containing polymer is used instead of a multi-layer hard mask film, and a photoresist material containing the hard mask film material or a silicon-containing polymer is used for the gap fill layer and a relax material is used. By performing a patterning process by employing a method of forming a spacer layer, it is possible to simplify the conventional spacer patterning technology, thereby reducing the process time and cost.

In addition, the present invention has an advantage over the double exposure process in terms of misalignment because it uses a spacer patterning technique that performs the mask process only once.

1A to 1E are cross-sectional views illustrating a method of forming a pattern of a semiconductor device according to the prior art.

2 is a SEM photograph showing a pattern formation method of another semiconductor device according to the prior art.

3A to 3E are cross-sectional views illustrating a method of forming a pattern of a semiconductor device according to the present invention.

<Brief description of the main parts of the drawing>

10, 110: semiconductor substrate 12, 112: etched layer

14: first hard mask film 14a: first hard mask film pattern

114: hard mask film 114a: hard mask film pattern

16 second hard mask film 18 antireflection film

20, 120: photoresist pattern 22: nitride film for spacer

22a: spacer 30: low temperature oxide film

124: spacer layer 126: gap fill layer

126a: gap fill layer pattern

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

Referring to FIG. 3A, an etched layer 112 including a stacked structure of a plasma-enhanced tetraethyloxysilicate (PE-TEOS) oxide film, an amorphous carbon layer, a PE-TEOS oxide film, and a polysilicon layer is formed on the semiconductor substrate 110. After the formation, a hard mask layer 114 including a silicon-containing polymer is formed on the etched layer 112.

The hard mask layer 114 may be formed by applying a hard mask layer material on the etched layer 112 to a thickness of 300 to 1000 mm by spin coating and baking at 150 to 250 ° C. for 60 to 120 seconds.

The hard mask film material includes a silicon-containing polymer containing 30 to 80 wt%, preferably 15 to 45 wt% of silicon molecules, an additive, and an organic solvent based on the total weight of the polymer.

The silicone-containing polymer is not particularly limited, for example, a compound containing a Si-Si-O- structure, a siloxane compound, a (hydroxy phenylalkyl) htdroxyphenylalkyl silses-quioxane compound or alkyl Or a ladder type silicone copolymer which consists of a phenyl silsesquioxane compound can be used.

In the present invention, NCH0987N (manufactured by Nissan Kogyo Chemical Co., Ltd.), HM21 (manufactured by TOK Corporation, Japan), and ODL series (manufactured by Shin-Etsu Corporation, Japan) are used.

In this case, the silicon content may be adjusted to obtain a desired hard mask film pattern, and other materials may be used as long as they exhibit etching properties for the same purpose.

As described above, in the present invention, since the step of forming a multi-layered hard mask film can be omitted, the process is simplified and the process time is shortened.

Next, a conventional chemically amplified photoresist composition of a positive or negative type is applied on the hard mask film 114 and then baked to form a photoresist film (not shown), and then an exposure and development process is performed on the photoresist film. The photoresist pattern 120 is formed.

In this case, the exposure process may use an ArF light source, KrF or EUV light source.

In addition, the chemically amplified photoresist composition is US 5,750,680 (May 12, 1998), US 6,051,678 (April 18, 2000), US 6,132,926 (October 17, 2000), US 6,143,463 (Nov. 7, 2000), US 6,150,069 (Nov. 21, 2000), US 6.180.316 B1 (January 30, 2001), US 6,225,020 B1 (May 1, 2001), US 6,235,448 B1 (May 22, 2001) and US 6,235,447 B1 (2001 5. 22) and the like can be used, preferably polyvinylphenol-based, polyhydroxystyrene-based, polynorbornene-based, polyadamantyl-based, polyimide-based, polyacrylate-based, polymethacrylate-based, At least one selected from polyfluorine-based includes a base resin, a photoacid generator and an organic solvent.

In particular, the base resin is a ROMA-type polymer comprising a substituted maleic hydride as a polymerization repeating unit; A COMA polymer comprising a cycloolefin polymerization repeating unit, a polymerization repeating unit of maleic hydride and a methacrylate or acrylate polymerization repeating unit; And polymers in a hybrid type of one or more of the polymers.

Referring to FIG. 3B, the hard mask layer 114 is etched using the photoresist pattern 120 as an etch mask until the etched layer 112 is exposed, thereby forming the hard mask layer pattern 114a.

The hard mask film 114 is a mixed gas using CF ₄ 90sccm, CHF ₃ 30sccm, O ₂ 11sccm and Ar 600sccm plasma gas in a FLEX etching chamber (manufactured by Lam, USA) under a pressure of 160mT and a power of 150W. Can be done with

Referring to FIG. 3C, after applying the release material on the top of the hard mask pattern 114a and baking for 60 to 120 seconds at 80 ° C. to 150 ° C., the surface of the hard mask layer pattern 114a and the release material are reacted. The spacer layer 124 having a thickness of about 40 kHz is formed.

Relaxation material is a material commercialized under license from AZ Electronic Materials, and is mainly used for the process of reducing the size of contact holes. Specifically, the photoresist pattern is formed by performing an exposure process and a development process on a semiconductor substrate, and then, by coating a relax material on the entire surface of the photoresist pattern and performing a bake process, a crosslinking reaction between the relax material and the photoresist pattern is performed. This happens. Accordingly, the distance between the patterns is reduced by the finally obtained pattern, thereby reducing the size of the contact hole.

In the present invention, by using a relax material having a different degree of adhesion to the hard mask film pattern 114a according to the temperature, the thickness of the spacer layer 124 can be adjusted as desired according to the change of the design rule, and also correlated with temperature. It is also possible to use relax materials that exhibit certain properties.

Referring to FIG. 3D, the gap fill layer 126 including the silicon-containing polymer is formed on the entire surface of the etching layer 112 including the spacer layer 124 to be greater than or equal to the height of the hard mask layer pattern 114a. The pattern 114a is embedded by the gapfill layer 126.

The gap fill layer 126 may be formed of the same material as the hard mask film material forming the hard mask film 114, or may be formed of a photoresist material including a silicon-containing polymer, an organic solvent, and a photoacid generator. have.

When the gapfill layer 126 is formed of the hard mask layer 114 material, the etching layer 112 including the spacer layer 124 may be formed of a hard mask layer material including a silicon-containing polymer, an organic solvent, and an additive. After coating to a thickness of 300 to 1000Å on the upper front, it may be formed by baking at 150 to 250 ℃ for 60 to 120 seconds.

In this case, since the hard mask film material can be used again, the cost reduction effect is excellent.

Meanwhile, when the gapfill layer 126 is formed of a photoresist material, a photoresist material including a silicon-containing polymer, an organic solvent, and an additive is 300 on the entire surface of the etched layer 112 including the spacer layer 124. After coating to a thickness of 1000 to 1000 Pa, it can be formed by baking at 150 to 250 ℃ for 60 to 120 seconds.

The silicone-containing polymer is not particularly limited, but for example, a polymer including a polymerization repeating unit represented by Chemical Formula 1 below, Korean Patent Publication No. 10-2005-002384, Korean Patent No. 575120 or Korean Patent No. 78087 Copolymers such as those disclosed herein may be used. In the present invention, SHB-A629 (manufactured by Shin-Etsu Japan) or SAX-100K (manufactured by JSR Japan) is used.

[Formula 1]

Where

R is hydrogen or methyl; R ₁ is C ₂ -C ₁₀ straight or branched alkylene; R ₂ , R ₃ And R ₄ is a C ₁ to C ₃ alkoxy group; R ₅ is a protective group sensitive to acid or alkyl of OH, H or _{C 1 ~C 10, a: b} : relative ratio (mol) of c is from 0.3 to 1: 1 to 3: 1.

Referring to FIG. 3E, the gap fill layer 126 is etched back by a dry or wet method until the spacer layer 124 is exposed, and then the spacer layer 124 is removed using thinner or developer. The gap fill layer pattern 126a is formed.

In this case, since the gap fill layer pattern 126a is formed of a hard mask film material or a photoresist material including a silicon-containing polymer, the gap fill layer pattern 126a has the same physical properties as the hard mask film pattern 114a. In addition, the gap fill layer pattern 126a formed by the above method has a vertical shape.

Next, the etching target layer 112 is etched using the gap fill layer pattern 126a and the hard mask layer pattern 114a as an etching mask to form an etching target layer pattern (not shown).

On the other hand, the preferred embodiment of the present invention for the purpose of illustration, those skilled in the art will be possible to various modifications, changes, replacements and additions through the spirit and scope of the appended claims, such modifications and changes are as follows It should be regarded as belonging to the claims.

Claims (10)

Forming a hard mask film including a silicon-containing polymer on the etched layer on the semiconductor substrate; Forming a first photoresist pattern on the hard mask layer; Etching the hard mask layer using the first photoresist pattern as an etching mask to form a hard mask layer pattern; Forming a spacer layer on the hard mask layer pattern, the spacer layer including a resist enhancement lithography assisted by chemical shrink (RELACS) material; Forming a gap fill layer including a silicon-containing polymer on the entire upper surface of the etched layer including the spacer layer at a height greater than or equal to the height of the hard mask layer pattern; Etching the gapfill layer on the entire surface until the spacer layer is exposed; Removing the spacer layer to form a gap fill layer pattern; And And etching the etched layer using the gap fill layer pattern and the hard mask layer pattern as an etch mask to form an etched layer pattern. The method according to claim 1, Forming the hard mask film is a pattern forming method of a semiconductor device, characterized in that using a spin coating method. The method according to claim 1, The forming of the hard mask layer pattern may include performing at least one plasma etching gas selected from the group consisting of CF ₄ , CHF ₃ , O _2, and Ar. The method according to claim 1, The hard mask film comprises a silicon-containing polymer, an organic solvent and an additive, the pattern forming method of a semiconductor device. The method according to claim 1, The gap fill layer includes a silicon-containing polymer, an organic solvent, and an additive. The method according to claim 4 or 5, The silicone-containing polymer may be a compound comprising a Si-Si-O- structure, a siloxane compound, a (hydroxy phenylalkyl) silsesquioxane compound, an alkyl silsesquioxane compound or a phenyl silsesquioxane compound and combinations thereof The method of forming a pattern of a semiconductor device, characterized in that the ladder-type silicone copolymer selected from the group consisting of. The method according to claim 1, The gap fill layer includes a silicon-containing polymer, an organic solvent and a photoacid generator. The method according to claim 7, The method of forming a pattern of a semiconductor device, characterized in that the salicon-containing polymer is a polymer comprising a polymerized repeating unit of Formula 1 below: [Formula 1] Where R is hydrogen or methyl; R ₁ is C ₂ -C ₁₀ straight or branched alkylene; R ₂ , R ₃ And R ₄ is a C ₁ to C ₃ alkoxy group; R ₅ is a protective group sensitive to acid or alkyl of OH, H or _{C 1 ~C 10, a: b} : relative ratio (mol) of c is from 0.3 to 1: 1 to 3: 1. The method according to claim 1, The forming of the spacer layer may include baking the resin at a temperature of 80 ° C. to 150 ° C. after applying the release material. The method according to claim 1, The removing of the spacer layer is a pattern forming method of a semiconductor device, characterized in that using a thinner or developer.