KR20090099415A - Manufacturing method of semiconductor device using spacer patterning technology - Google Patents

Abstract

A method for manufacturing a semiconductor device using a spacer patterning process is provided to prevent a photoresist scum by forming the photoresist pattern containing Si in an upper part after coating a spin on carbon layer on the spacer pattern. A first mask layer(112) and a second mask layer(114) are deposited in an upper part of an etched layer of a semiconductor substrate(110). A first photo resist pattern is formed in an upper part of a second mask layer by a lithography process. A second mask pattern is formed by patterning the second mask layer using a first photoresist pattern. A spacer is formed in a sidewall of a second mask pattern. A spacer pattern(132') is formed by removing the second mask pattern. A second photoresist pattern exposing the spacer pattern section is formed in the front surface including the spacer pattern.

Description

Manufacturing method of semiconductor device using spacer patterning technology

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device using a spacer patterning process in a double exposure process technology, and more particularly, after coating a spin-on carbon film having excellent planarization properties after forming a spacer pattern, Si is contained thereon as a pad mask pattern. The present invention relates to a spacer patterning process in which a pattern defect, pattern lifting, or photoresist scum does not occur even when a pad pattern is formed without forming a photoresist pattern.

As the design rule decreases, due to the limitation of current ArF immersion exposure equipment with a numerical aperture (NA) of 1.35 or less, a typical single exposure cannot form a line / space pattern of 40 nm or less. Even with a much higher numerical aperture using high index fluid (HIF) materials, a 30 nm line / space pattern cannot be obtained, and the use of an exposure source with extreme ultra violet (EUV) wavelength can be used for exposure light sources, equipment, and resists. Insufficient back to reach application stage.

Accordingly, in the lithography process, studies on double exposure technology (DPT) have been actively conducted to improve resolution.

The DPT process is a technique for exposing and etching a pattern having twice the period of the pattern cycle called DE2T (Double Expose Etch Technology) process and exposing and etching the second pattern having the same double cycle in between. It can be divided into a process using a spacer called a (Spacer Patterning Technology) process.

The DE2T process may be formed by a process of negative tone and positive tone, respectively. The negative tone DE2T process removes the pattern formed in the first mask process from the second mask process to form a desired pattern. The positive tone DE2T process combines the patterns formed in the first mask process and the second mask process to form a desired pattern. How to form.

The DE2T process can achieve the desired resolution by performing the second mask process and the etching process after the first mask process and the etching process, but the number of additional processes can be complicated and the first mask process commonly called overlay Miss alignment of the pattern obtained in the first mask process may occur.

The SPT process is a self alignment that eliminates the disadvantage of misalignment because the mask process only needs to be performed once to pattern the cell region. However, a pad mask for forming a pad pattern to be formed to be connected with the contact, and a cutting mask process for separating the spacer portion of the line end region resulting from the spacer formation are additionally required. Uneven deposition and a horn-shaped asymmetrical spacer are formed, which makes CD control difficult and can result in lack of CD uniformity.

1A to 1H are cross-sectional views and plan views illustrating a method of forming a pattern using an SPT process according to the related art.

First, referring to (i) of FIG. 1A, various mask films, for example, an amorphous carbon film 12, a SiON film 14, a polysilicon film 16, are formed on an etched layer 10 of a semiconductor substrate. After the amorphous carbon film 18 and the SiON film 20 are sequentially applied, the antireflection film 22 and the first photoresist pattern 24 'are formed. (A) of FIG. 1A is a top view of (i), and (i) is sectional drawing A-A 'of (ii).

Referring to FIG. 1B, the anti-reflection film 22, the SiON film 20, and the amorphous carbon film 18 are sequentially patterned using the first photoresist pattern 24 ′ as an etch mask to form the amorphous carbon film pattern 18 ′. Form.

Referring to FIG. 1C, an insulating film is deposited on the entire surface of the amorphous carbon film pattern 18 ′ (not shown) and etched to form a spacer 32 on sidewalls of the amorphous carbon film pattern 18 ′.

Referring to FIG. 1D, the amorphous carbon film pattern 18 ′ is removed using the spacer 32 as an etch mask to form the spacer pattern 32 ′.

Referring to (i) and (ii) of FIG. 1E, a second photoresist film (not shown) is formed on the entire surface including the spacer pattern 32 ′, followed by an exposure and development process to finish the spacer pattern. A second photoresist pattern 26 exposing (B) is formed.

Subsequently, when the second photoresist pattern 26 is removed by etching the spacer pattern end portion B by an etching mask and then the second photoresist pattern 26 is removed, as shown in FIGS. 1F (i) and (ii). .

In the case of the control gate (CGT) of the NAND flash memory, select transistors are provided at both ends of a word line composed of 16 or 32, and a source selection line (SSL) is connected to a source contact. The other drain selection line (DSL) is connected to the drain contact.

In general, SSL and DSL have a sharp deterioration in the aerial image as the defocus increases at both ends of the word line, so the DOF of Focus Margin is relatively inferior to the word line. Accurate CD control is required because it is associated with the turn-on of the channel. In addition, since the select line has a larger CD size than the word line, the select line may be formed during the pad mask process in the SPT process.

Referring to (i) and (ii) of FIG. 1G, a pad pattern photoresist pattern 28 ′ is formed on the pad region P. FIG. At this time, as described above, the selection transistors SSL and DSL are formed.

Referring to FIG. 1H, the lower mask layer 16, 14, and 12 are etched using the spacer pattern 32 ′ and the photoresist pattern 28 ′ for the pad pattern as an etch mask to form the lower mask layer pattern and the pad pattern. (14 ', 12').

In the conventional process as described above, it is difficult to coat BARC because high spacers are formed during the pad mask process as shown in FIG. 1G, which may cause photoresist profiles and pattern defects.

BARC coatings control substrate reflectance in the wavelength range, forming photoresist patterns without standing waves or notching, and helping to even out CDs, so lithography using DUV light sources such as ArF or KrF It is an essential process in the process, and also plays a role of improving the adhesion between the substrate and the photoresist.

However, when the BARC coating is applied to form the pad mask pattern as shown in FIG. 1G in the state shown in FIG. 1F, the BARC is filled between the spacers as shown in FIG. 2. In FIG. 2, the BARC-filled thickness is 786Å at point ①, 816Å at point ②, and 428Å at point ③. In general, when coating the conformal BARC 430 에지, the edge region E without spacers is coated with 430 그대로 as it is, but the valley between the spacers is filled with 800 Å BARC level.

Although the photoresist profile and pattern may be improved according to the application of BARC, there is a separate step of removing BARC using photoresist as an etching mask when etching the lower poly after pad mask formation. ArF photoresist, which should be considerably thick, has a problem that it is not easy to synthesize thick due to its chemical structure. In addition, when the photoresist thickness is thick, process margins are generally not secured.

In addition, when the BARC is removed, an etching gas, which is a CF ₄ base, is used. Since the poly, nitride and oxide films are also etched, the spacer and the bottom poly of the present invention are formed during BARC etching after forming a pad mask by applying BARC. The layer may be attacked to reduce its height, resulting in insufficient selectivity to etch the underlying layers.

Therefore, since BARC is not applicable, forming a pad mask without BARC occurs as shown in FIGS. 3A and 3B.

Referring to FIG. 3A, the spacer reflects light and notching occurs, thereby causing a pad pattern defect such as an adjacent SSL and DSL region.

Referring to FIG. 3B, pad pattern lifting due to poor adhesion occurs.

Meanwhile, referring to FIG. 3C, the photoresist scum S may be present between narrow spaces between the spacer patterns because the spacer pattern is high so that the exposure source does not enter or is not developed in the developer.

In the present invention, the BARC coating process cannot be performed when the pad pattern is formed during the space patterning process, so that a pattern defect, a pattern lift, or a photoresist scum occurs.

The present invention provides a method for manufacturing a semiconductor device, comprising: depositing a first mask layer and a second mask layer on an etched layer of a semiconductor substrate;

Forming a first photoresist pattern on the second mask layer by a lithography process;

Patterning the second mask layer using the first photoresist pattern to form a second mask pattern;

Forming a spacer on sidewalls of the second mask pattern;

Removing the second mask pattern to form a spacer pattern;

Forming a second photoresist pattern exposing a spacer pattern end on the entire surface including the spacer pattern;

Removing an end portion of a spacer pattern by using the second photoresist pattern as an etching mask, and removing the second photoresist pattern;

Forming a third mask layer on the entire surface of the spacer pattern from which the end portion is removed;

Forming a Si-containing photoresist pattern as a pad pattern mask pattern in a peripheral circuit region above the third mask film;

Etching the third mask layer by using the pad pattern mask pattern as an etching mask to form a third mask pattern; And

It provides a method of manufacturing a semiconductor device comprising the step of patterning the first mask film using the spacer pattern and the third mask pattern as an etching mask.

In this case, the first photoresist pattern is preferably formed such that the length of the line: space has a ratio of 1: 3.

Preferably, the second mask film is made of amorphous carbon.

The second mask pattern is preferably removed by a strip process using O ₂ plasma.

Preferably, the third mask film is a spin-on-carbon film,

In this case, the spin on carbon is preferably a material having a carbon content of 80 wt% or more and 95 wt% or less.

The photoresist composition for forming the Si-containing photoresist pattern preferably contains at least 15% by weight of Si, preferably at least 15% by weight and at most 30% by weight of Si.

Since the third mask layer is formed by the spin-on coating method, the manufacturing cost is reduced and the unit operation time is faster than the CVD process.

In the forming of the third mask layer, the third mask layer is coated with a thickness to fill all the spacer patterns, and then planarized.

The third mask layer etching is Ar, O _2, H _2, CO, or it is preferred the dry etching using a source gas containing a mixed gas, this time to the Si component and the etching gas in the Si-containing photoresist reaction SiO ₂ It is possible to enhance the etching selectivity by forming a.

The present invention also provides a semiconductor device manufactured using the spacer patterning method.

According to the spacer patterning process of the present invention, even if the BARC coating process is not performed during the pad pattern formation, the spacer patterning process may be performed without pattern defects, pattern lifting, or photoresist scum.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

4A to 4I are cross-sectional views and plan views illustrating a method of forming a pattern using the SPT process according to the present invention.

First, referring to FIG. 4A (i), various mask films, for example, an amorphous carbon film 112, a SiON film 114, a polysilicon film 116, are formed on an etched layer 110 of a semiconductor substrate. After the amorphous carbon film 118 and the SiON film 120 are sequentially applied, the antireflection film 122 and the first photoresist pattern 124 'are formed. (A) is a top view of (i), (i) is A-A 'sectional drawing of (ii).

In this case, the first photoresist pattern 124 ′ is preferably formed such that the length of the line: space is about 1: 3.

Referring to FIG. 4B, the anti-reflection film 122, the SiON film 120, and the amorphous carbon film 118 are sequentially patterned using the first photoresist pattern 124 ′ as an etch mask to form the amorphous carbon film pattern 118 ′. Form.

Referring to FIG. 4C, an insulating film is deposited on the entire surface of the amorphous carbon film pattern 118 ′ (not shown) and etched to form a spacer 132 on the sidewall of the amorphous carbon film pattern 118 ′.

Referring to FIG. 4D, the amorphous carbon film pattern 118 ′ is removed using the spacer 132 as an etch mask to form the spacer pattern 132 ′.

At this time, the amorphous carbon film pattern 118 ′ is preferably removed by a strip process using an O ₂ plasma.

Referring to (i) and (ii) of FIG. 4E, a second photoresist film (not shown) is formed on the entire surface including the spacer pattern 132 ′, and then an exposure and development process is performed to finish the spacer pattern end. A second photoresist pattern 126 exposing (B) is formed.

Subsequently, when the second photoresist pattern is removed by etching the spacer pattern end (B) with an etching mask and then removing the second photoresist pattern, the second photoresist pattern is as shown in FIGS. 4F and 4.

Referring to (i) and (ii) of FIG. 4G, the spin-on carbon film 142 is sequentially formed as a third mask on the entire structure of FIG. 4F by a spin-on coating method, and the pad pattern is disposed on the pad region P. FIG. A Si-containing photoresist pattern 128 'is formed.

In this case, the spin on carbon is preferably a material having a carbon content of 80% by weight or more and 95% by weight or less.

In addition, when forming the third mask film, it is preferable to coat the third mask film to a thickness in which all of the spacer patterns are embedded, and then planarize, and to form a pad pattern photoresist pattern on the planarized third mask film.

In this case, the third mask layer is preferably formed by spin-on coating.

In this case, as the spin-on carbon film, SHN18 of Nissan Chemical Co., Ltd. may be used.

In addition, the spin-on carbon film used as the third mask film is a material film that can sufficiently replace the amorphous carbon film because the carbon content is 80% by weight or more, and the optical constant (refractive index n, extinction coefficient k) of the spin-on carbon film is sufficient. The combination can adjust the reflectivity of the substrate without applying BARC.

In addition, photoresist scum that is not removed during development due to undelivered light or undiffusion of acid does not occur because spin-on carbon is gapfilled between spacers.

The spin-on carbon film has an excellent planarization property and can be formed by a spin-on coating method, thereby reducing manufacturing costs and shortening time compared with the CVD process.

5 is a cross-sectional SEM photograph showing that the spin-on carbon film 142 is coated on the spacer pattern 132 'and then flattened.

Referring to FIG. 4H, the spin-on carbon film 142 is etched using the Si-containing photoresist pattern 128 ′ for the pad pattern as an etching mask to form the spin-on carbon film pattern 142 ′.

In this case, the etching of the spin-on carbon film is preferably a dry etching process using a source gas containing Ar, O ₂ , H ₂ , CO, or a mixture thereof.

At this time, since the Si content of the Si-containing photoresist pattern influences the etching selectivity of the lower spin-on carbon film, the higher the Si content of the Si-containing photoresist is advantageous. In the present invention, although a Si-containing photoresist material, SHB-A629 (manufactured by Shinetsu Japan) or SAX-100K (manufactured by JSR Japan) can be used, but is not limited thereto.

Referring to FIG. 4I, the lower mask layers 116, 114, and 112 are etched using the spacer pattern 132 ′ and the spin-on carbon layer pattern 142 ′ as an etch mask to form the lower mask layer pattern and the pad pattern 114. ', 112').

Preferred embodiments of the present invention are for the purpose of illustration, and those skilled in the art will be able to make various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, and such modifications may be made by the following claims. Should be seen as belonging to.

1A to 1H are cross-sectional views illustrating a method of forming a pattern using the SPT process according to the prior art.

2 is a cross-sectional view showing that BARC is embedded between spacers.

3A to 3C are cross-sectional views and planar photographs illustrating problems in the case of forming a pad mask without applying BARC.

4A to 4I are cross-sectional views illustrating a method of forming a pattern using the SPT process according to the present invention.

Fig. 5 is a cross-sectional SEM photograph showing that the spin-on carbon film is coated on the spacer pattern and then planarized.

<Code description>

110: semiconductor substrate

112, 14, 116, 118, 120, 142: mask film

124 ', 126, 128': photoresist pattern

132: spacer, 132 ': spacer pattern

Claims (11)

Depositing a first mask layer and a second mask layer on the etched layer of the semiconductor substrate; Forming a first photoresist pattern on the second mask layer by a lithography process; Patterning the second mask layer using the first photoresist pattern to form a second mask pattern; Forming a spacer on sidewalls of the second mask pattern; Removing the second mask pattern to form a spacer pattern; Forming a second photoresist pattern exposing a spacer pattern end on the entire surface including the spacer pattern; Removing an end portion of a spacer pattern by using the second photoresist pattern as an etching mask, and removing the second photoresist pattern; Forming a third mask layer on the entire surface of the spacer pattern from which the end portion is removed; Forming a Si-containing photoresist pattern as a pad pattern mask pattern in a peripheral circuit region above the third mask film; Etching the third mask layer by using the pad pattern mask pattern as an etching mask to form a third mask pattern; And And patterning the first mask layer by using the spacer pattern and the third mask pattern as an etch mask. The method according to claim 1, The first photoresist pattern is a semiconductor device manufacturing method, characterized in that the length of the line: space having a ratio of 1: 3. The method according to claim 1, And the second mask layer is made of amorphous carbon. The method according to claim 1, And the second mask pattern is removed by a strip process using O ₂ plasma. The method according to claim 1, And the third mask film is a spin-on-carbon film. The method according to claim 5, The spin on carbon is a method of manufacturing a semiconductor device, characterized in that the carbon content of more than 80% by weight to 95% by weight. The method according to claim 1, The method of manufacturing a semiconductor device, characterized in that the photoresist composition forming the Si-containing photoresist pattern comprises 15% to 30% by weight of Si of the photoresist polymer. The method according to claim 1 or 5, The third mask layer is a method of manufacturing a semiconductor device, characterized in that formed by spin-on coating. The method according to claim 1, The forming of the third mask layer may include coating the third mask layer to a thickness in which all of the spacer patterns are embedded, and then planarizing the third mask layer. The method according to claim 1 or 5, The etching of the third mask layer is a dry etching method using a dry etching using a source gas containing Ar, O ₂ , H ₂ , CO or a mixture of these. A semiconductor device manufactured using the method of claim 1.

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