KR20090064279A - Protective layer to enable damage free gap fill - Google Patents

Abstract

A gap having a high aspect ratio (typically 6: 1 or more, for example 7: 1 or more) and having a narrow width (typically 0.13 micron or less, for example 0.1 micron or less) An in-situ semiconductor process is provided that is capable of filling without damaging the features and causing little or no void, or vulnerable portions. After a protective layer is formed or maintained that lines the gap, deposition of the fill material to partially fill the gap, ALR etching of a portion of the fill material to reduce the aspect ratio of the gap, and This is followed by final deposition of the filling material to fill. The protective layer has a high etch selectivity relative to the fill material and may be silicon nitride, silicon oxynitride, or silicon rich oxide. The layer can be formed by nitriding a portion, or a portion of silicon oxide lining a deposition portion. During the first deposition of the fill material, the layer can be formed by heating with plasma without oxygen and delaying the bias power application. Deposition and ALR etching may be repeated as needed to completely fill the gap, with or without forming an intermediate protective layer.

Description

PROTECTIVE LAYER TO ENABLE DAMAGE FREE GAP FILL}

The present invention relates to an electronic device assembly process and a related device. More specifically, the present invention relates to chemical vapor deposition and dry etching processes for forming dielectric layers, in particular for forming dielectric layers when filling gaps with high aspect ratios. .

In semiconductor processing, filling the high aspect ratio gap with insulating material is essential. This is true in the case of shallow trench isolation (STI), inter-metal dielectric (IMD) layers, inter-layer dielectric (ILD) layers, pre-metal dielectric (PMD) layers, passivation layers, and the like. As device geometry shrinks and heat dissipation costs decrease, due to the limitations of existing deposition processes, it has a narrow width (eg 0.13 μm gap width) and high aspect ratio (AR) (eg AR> 6: 1) Filling wealth without voids becomes increasingly difficult.

High density plasma (HDP) chemical vapor deposition (CVD) and directional (bottom-top) CVD processes are currently used for high aspect ratio gap filling. HDP CVD deposits more material at the bottom, than at the sidewalls, in high aspect ratio structures. This is done by directing the dielectric precursor species downward, towards the bottom of the gap, and at the same time removing material deposited on top of the trench through sputtering using deflected RF power applied to the substrate. The ratio of sputtering (S / D) to deposition determines the properties of the deposited material. More homogeneous layers with more desirable step coverage are obtained using higher S / D ratios.

However, by HDP CVD gap filling, at the inlet portion of the gap to be filled, a cusp, called an overhang, is formed. This formation is derived from the sputtering and redeposition process. The directional aspect of the deposition process creates a highly intrusive charged species that sputters the material away from inside the gap. The sputtered material tends to be deposited again on the sidewalls of the high AR structure. Thus, before the bottom-up fill is completed at the bottom, the entrance area of the structure can be closed, leaving voids or weak spots in the high aspect ratio structure. This phenomenon, known as “pinch-off,” is exacerbated in narrow features. Overhangs cannot be completely removed. Because non-directional reactions, and sputtering and redeposition reactions, of neutral species are inherent in the physical and chemical properties of the HDP CVD process.

In addition, as the aspect ratio increases, the shape of the gap itself can cause problems. High aspect ratio gaps often show reentrant features, making gap filling even more difficult. The most problematic reentrant feature is the narrow top of the gap, with the sidewalls inclined inward near the top of the gap. For a given aspect ratio feature, this increases the ratio of the volume of the gap to be filled to the gap inlet region exhibited by the precursor species during deposition. Therefore, there is a much higher chance of having voids or weak spots.

In addition to undesirable formation inside the features, a peak of dielectric material called a "top hat" is formed on the top surface of the substrate, on the sides of the features. The top hat is a deposit of material in the form of peaks with a downward slope towards the inlet of the gap. The top hat is an additional source of redeposition species that, if not removed, increases the rate of overhang growth, thereby resulting in a much higher aspect ratio of the gap.

In some gap fill applications, particularly for small features with high aspect ratios, a multi-step deposition / etch back process to remove overhangs, reduce top hats, and promote void-free gap fill. This has been used. For example, deposition and etching processes using HDP CVD deposition and aqueous HF dip have been used. However, this requires the wafer to cycle between the plasma deposition system and the wet etch back system for several cycles. This results in a long cycle time and, therefore, a large capital investment to operate multiple steps for gap filling.

In-situ multi-stage plasma deposition / etching processes have also been used to prevent inlets from closing the gap before the gap is filled. Such in-position HDP CVD deposition and etch back processes are described, for example, in US Pat. Nos. 7,163,896, 6,030,881, 6,395,150, and 6,867,086, the disclosures of which are incorporated herein by reference. Some of these in-situ plasma etch back processes use high-energy ions to produce anisotropic sputter etching. Other in-situ etch back processes use chemically reactive etching gases (eg, nitrogen trifluoride, NF ₃ ) to produce anisotropic plasma etch.

In many cases, these sputter etch and reactive plasma etch processes damage the underlying structures of the features on the substrate. When the gap is opened again by the etching process, the oxide filled material on the sidewalls and bottom of the trench is exposed to the etching reaction. For example, when an anisotropic plasma etch step is used, the top sidewall of the structure can be corroded, and by the etch step, almost all of the material that was deposited in the previous etch step can be removed. Through either of these chemical or physical pathways, compromised device performance (eg, higher leakage currents) can result when the underlying structure is corroded. Therefore, during the gap filling operation, it is desirable to reduce the corrosion of the underlying structure.

Typically, the blueprint of the device has regions with different feature densities on the substrate. There may be one or more zones with high feature density and one or more zones with isolated features. These zones of different feature densities react differently to deposition and etching processes, resulting in varying degrees of filling. Zones with high feature densities are more likely to pinch-off due to their relatively higher aspect ratio. Thus, generally high density features form a maximum amount of deposition before an etching step is required. The high density feature can similarly determine the amount of etching needed to remove the overhang at the inlet of the gap and reopen the gap. However, the amount of etching needed to remove the cusp material from the zone with the high feature density results in excessive etching of the zone with isolated features. This can cause serious damage to underlying structures in isolated features. The reduced etch will protect the isolated features, but will increase the number of deposition / etch operations necessary to fully fill the gap, or in more severe cases, void formation may result. Therefore, it is desirable to develop an improved etching process that can remove overhang material without damaging underlying underlying features, over regions of high feature density and isolated features.

These in-situ multi-stage deposition and etch back processes improve the high aspect ratio gap filling capability, but have narrow width features with high aspect ratios, especially ultra-small features with aspect ratios of about 6: 1 or greater (eg, Dielectric deposition processes that can reliably fill a feature with a gap width of about 0.1 μm without leaving voids continue to be sought. It is even more difficult to uniformly fill high aspect ratio features on substrates containing zones with different feature densities. There is still a need for a method to reliably fill both high density and isolated features that have fewer operations and do not cause damage to underlying structures.

The present invention has a high aspect ratio (typically 6: 1, for example, 7: 1 or greater) on a substrate comprising regions of different feature densities, and has a narrow width (typically 0.13 microns, such as 0.1 microns or less). An in-situ semiconductor process capable of filling a gap with) without damaging the underlying structure. Filling should be done with little or no voids, seams, or fragility. Several sequences of deposition and etching process steps can be performed to completely fill the gaps.

In one embodiment, the present invention relates to silicon nitride (SiN), silicon rich oxide (SRO), silicon oxynitride (SiON), silicon carbide (SiC), aluminum oxide (Al ₂ O ₃ ), aluminum Nitride (AlN), silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), carbon (C), boron nitride (BN), silicon boron nitride (SiBN), silicon boron carbide (SiBC), boron carbide (BC), methods for filling gaps lined with germanium nitride (GeN) and germanium carbide (GeC) without damaging the underlying structure. Conventional HDP CVD deposition processes expose the liner to plasma containing silicon, oxygen and inert species. The oxygen species may partially oxidize the liner, which may reduce the selectivity of the liner for subsequent chemical etching steps. Oxidation deteriorates when bias power is applied to the substrate that attracts plasma species toward the substrate surface. The present invention modifies the HDP CVD deposition process to prevent the liner from oxidizing in order to effectively protect the underlying structure against the etching operation. The method includes heating the substrate with plasma without oxygen, or radiant heat, and initially depositing the fill material on the feature without applying bias power to the substrate until the overhang structure of the fill material partially blocks the opening of the gap. Includes steps. The overhang fill material may then be chemically reacted with one or more reactants to form a solid reaction product, which subsequently decomposes and removes the reaction product to expose the unreacted fill material at the bottom of the feature. can do. Reaction, decomposition and removal operations are also referred to as atomic layer removal (ALR) processes. If necessary, additional deposition and etching steps may be performed to fill the features. These additional deposition steps can be SACVD, spin-on dielectrics, flowable CVD, ALD, or PDL.

Silicon nitride has a preferred ALR etch selectivity to the fill material, while partially oxidized silicon nitride does not. Since silicon nitride liners can be oxidized by exposure to plasma containing oxygen species (eg, high density plasma in HDP CVD deposition), no oxygen should be used in the preheat plasma. The substrate may be heated by plasma containing, for example, non-oxygen species such as helium or hydrogen or nitrogen or argon. In some cases, other methods for heating the substrate may be used, for example, exposing the substrate to a heated pedestal, or radiant heat from a heated reaction chamber. In order to reduce the exposure of the silicon nitride liner to the species of the HDP CVD plasma, the substrate bias during the initial portion of the fill material deposition step, preferably until at least 2 seconds, or until 50-100 angstrom of filler material is deposited Power must be kept off or at a low level.

Deposition of the fill material using conventional HDP CVD processes continues with substrate bias power that pulls plasma species towards the substrate surface. The fill material may be, for example, a dielectric such as silicon dioxide, USG, BSG, PSG, or BPSG. Fill material is deposited on the bottom or sidewalls of the gap and on the surface of the substrate. Deposition continues until the filling material at the opening of the gap forms an overhang structure, which partially blocks the opening.

The overhang structure is etched using an ALR process by first reacting the filler material with one or more reactants to form a solid reaction product having a higher specific volume than the spent filler material. In other words, the solid reaction product will take up more space than the packed material. Higher specific volume can be at least two times the fill material, and generally at least three times the fill material. The solid reaction product, in particular, fully or completely blocks the partially blocked opening of the features of the dense zone so that no further reactants reach the bottom of the gap and react with the filling material, whereas the overhang and tower The reaction continues with the filling material of the hat structure. The reactants are ammonia (NH ₃ ), dry hydrogen fluoride (HF), hydrogen (H ₂ ), nitrogen trifluoride (NF ₃ ), nitrogen (N ₂ ), water vapor (H ₂ O), ammonium fluoride (NH ₄ F) and NH ₄ F: HF, or may be extracted from them. In one example, the gaseous reactant may have a ratio of about diammonium to tritium fluoride. Inert gases such as helium (He) and argon (Ar) may also be used diluted.

In some embodiments, it may be desirable to expose the substrate to only one of the reactants for a period of 1-30 seconds, preferably about 10 seconds, prior to introducing the remaining reactants. For example, following initial exposure, or “wetting” with ammonia, simultaneous exposure to ammonia and draft hydrogen fluoride can lead to more uniform nucleation of the fill material.

In another embodiment, the substrate is exposed to a series of doses of the mixture of reactants. Each reactant may enter the substrate for a period of about 0.1 seconds to 60 seconds. Typically, an inert gas purge, or pumping step is followed for a period of about 0.1 seconds to 60 seconds to remove excess reaction product, or to react the by-products. But purging the above. Or the pumping step is optional. One "cycle" includes exposure to the first reactant, an optional purging / pumping step, exposure to a second reactant, and an optional purging / pumping step. Solid reaction products are formed by reactions that are similar to simultaneous exposure to the reactants. The thickness etched increases with the number of cycles. As with the previous example, the thickness that is etched when the solid reaction product becomes too thick so that the reactants can no longer diffuse into the solid reaction product, so that the surface of the filler material located below it does not react Eventually becomes saturated.

The solid reaction product may then be desorbed to expose the unreacted filler material located underneath the feature. The desorption operation involves first decomposing the solid reaction product and then removing the decomposed reaction product. Decomposition is accomplished by heating the substrate to the sublimation temperature of the solid reaction product, such as up to about 100 ° C., or preferably up to about 100-150 ° C. The solid reaction product can be decomposed or sublimed into gaseous by-products, after which the gaseous by-products can be removed by venting or gas purging.

Small amounts of silicon nitride liners can be removed by an ALR etch process without significantly affecting device performance. The ALR etch selectivity of silicon nitride relative to the fill material may be about 5: 1 or greater, preferably 25: 1 or greater. The ALR etch reaction is self-limiting such that the repeatedly controlled amount of fill material can be removed by allowing the reaction to reach completion. However, this means that some silicon nitride can also be removed. For example, given a selectivity of 25: 1, about 4 angstroms of silicon nitride will be removed for a 200 angstrom fill material. Thus, silicon nitride can be substantially protected.

After the solid reaction product is removed, a second ALR process may be repeated, another protective liner may be deposited, and another deposition / etch of the fill material (using an ARL etch step, or an HDP plasma etch step). The sequence can be performed or the last deposition of the fill material to fill the gap can be performed. The optional second protective liner may be a sacrificial layer that is designed to be mostly or completely consumed by the subsequent etching process. An optional second protective liner is silicon rich oxide (SRO), or silicon nitride (SiN), or silicon oxynitride (SiON), or silicon carbide (SiC), or aluminum oxide (Al ₂ O ₃ ), or It may be a nitrided fill material.

In some cases, only the last one deposition is required to fill the gap, and no second ALR selective liner is formed. In general, when the aspect ratio is about 3: 1 or less, and the gap opening is about 90 angstroms or more, the HDP CVD process may fill the gap in one deposition step. However, after the ALR step, if the geometry of the remaining gaps cannot be filled in one deposition operation, the sequence of deposition and etching may be repeated.

In another aspect, the present invention relates to a method for filling a gap on a substrate that has no liner already present or that has a poor selectivity to an ALR etch process. As mentioned above, depending on the device to be manufactured, a liner is not always present in the device structure, for example in a particular flash or logic device. Even if the liner is present, it can include materials that have a poor etch selectivity to the fill material when exposed to an ALR etch process. The first protective liner is first formed to line the gap to sufficiently protect the underlying structure from the ALR etch co-response. The protective liner should have an ALR etch selectivity to a fill material of at least about 5: 1, preferably at least 25: 1. By nitriding a portion of the already existing oxide layer, the liner can be formed. The thickness of 10 to 100 angstroms in the oxide layer may be nitrided, preferably the thickness of 20 to 85 angstroms may be nitrided, more preferably the thickness of 40 to 70 angstroms. It is preferred that only part of the oxide layer is consumed by nitriding.

The oxide layer can be nitrided by exposure to plasma containing nitrogen species (eg, high density plasma used for HDP CVD and plasma used in plasma enhanced chemical vapor deposition (PECVD)). Nitrogen species can be obtained from any nitrogen containing gas, such as nitrogen (N ₂ ), or ammonia (NH ₃ ) gas. The nitriding process may heat the substrate to a temperature suitable for depositing the fill material. In addition to the nitrogen-containing gas, other gases, inert (or reactive) gases may be used. For example, helium, hydrogen, or argon may be added. The nitrided layer may have an ALR etch selectivity to a fill material similar to that of silicon nitride. The ALR etch selectivity may be at least 5: 1, or preferably at least about 25: 1.

In yet another embodiment, the protective liner may be formed by vapor deposition. Silicon nitride, silicon oxynitride, silicon rich oxide, Al ₂ O ₃ , SiC, AlN, SiCO, SiCN, SiOC, C, BN, SiBN, SiBC, BC, GeN and GeC, which may be integrally formed into the gap Or a layer of material with other high ALR etch selectivity may be deposited. After the etching process, while some of the liners remain in the gap, some of the layers during the ALR etching process, in particular portions of the upper edge of the gap and sidewalls may be removed. Ultimately only a small amount of liner can be integrated into the gap.

After the ALR selective layer is formed, the layer should not be oxidized because the selectivity can be compromised. Thus, when the substrate is heated, it can be heated with plasma without coral, or by using radiant heat from a heated pedestal, or a heated reaction chamber. In order to minimize the exposure of the plasma to the species, during the initial cycle of filling material deposition, little or no substrate bias power should be applied. The bias power may be off for at least about 2 seconds, or until about 50 to 100 angstrom of filler material is deposited.

Fill material deposition and ALR etching operations of this aspect of the invention can be repeated as necessary to fill the gap. Optionally, another protective liner may be formed after ALR etching. This additional liner may or may not be the same material as the original liner. For example, one embodiment of the process exposes a substrate to a succinct-containing plasma, deposits a fill material until the gap opening is partially blocked, and reacts some or all of the fill material with one or more reactants. Can be used to form a nitrided layer by depositing SRO as a second protective liner prior to generating a solid reaction product, desorbing the solid reaction product, and repeating the packing material deposition and ALR etching process. . Finally, after the gap is etched into a geometric state where one or more deposition operations will fill, the filler material is finally filled into the gap.

In some embodiments, the subsequent etching step may comprise an HDP plasma etching process. For example, after the initial fill material deposition and ALR etch process, a second fill material deposition can be performed using conventional HDP CVD conditions (ie, bias power is applied to the substrate). Deposition continues until the fill material begins to form an overhang structure at the gap opening, partially blocking the opening. The overhang structure can then be removed using HDP sputter etching, reactive plasma etching, or a combination of both (in order or simultaneously). As needed to fill the gap, additional deposition / etch steps may be performed. These additional deposition steps can be SACVD, spin-on dielectrics, flowable CVD, ALD, or PDL. Those skilled in the art will appreciate that any number of deposition and ALR etch steps may be performed before or after the plasma etch step is used.

In another aspect, the invention relates to a semiconductor processing apparatus configured to perform the methods described herein. The apparatus may comprise a plurality of wafer processing chambers. One or more chambers may be configured to form a protective liner, via deposition or nitriding. One or more chambers may also be configured to deposit the fill material onto the substrate. In some embodiments, the at least one chamber for forming the protective liner is the same chamber as the at least one chamber for depositing the fill material. In another embodiment, the chambers are different. One or more chambers may be configured to perform an HDP plasma etch step (sputter etch, or reactive plasma etch). These one or more chambers for performing an HDP plasma etch may be the same chamber as the one or more chambers for forming a protective liner or depositing a fill material.

The apparatus also includes one or more wafer processing chambers configured to react a portion of the substrate to form a solid reaction product and to perform an ALR process to desorb the solid reaction product. The ALR etch process chamber may include one or more wafer processing stations that perform reaction and desorption operations simultaneously or sequentially in the same chamber. The one or more wafer processing stations may be configured to each perform only one of the ALR etch process steps, or may be configured to perform two or more of the etch process steps in order. In one embodiment, the ALR etch chamber has four stations. That is, it has two stations for carrying out the solid reaction product reaction and two stations for desorbing the solid reaction product through decomposition and removal of the solid reaction byproduct. In yet another embodiment, the ALR etch chamber includes two stations for temperature control, one station for reaction, and one station for desorption. In another embodiment, an ALR step may be performed between deposition cycles in the HDP chamber. Those skilled in the art will appreciate that other configurations of ALR etch chambers are possible. That is, other configurations are possible by varying the number of wafer processing stations and by determining which station will perform which of the etching process steps.

The apparatus may also include a controller configured to execute the set of instructions. The set of instructions includes instructions for depositing a fill material and reacting one or more reactants with a portion of the fill material to form a solid reaction product until the overhang structure partially blocks the gap opening; It may be an instruction to desorb the solid reaction product. The set of instructions may also include instructions to form a protective liner before the first fill material deposition, or after any ALR etching step. The set of instructions may also include instructions for performing a conventional HDP CVD deposition / etching step. These instructions may be for performing the operations described in the method embodiments of the present invention. Using the device, a high aspect ratio gap of the substrate can be filled with little or no damage to the underlying structure, or liner, or without the existing device.

A gap having a high aspect ratio (typically 6: 1 or more, for example 7: 1 or more) and having a narrow width (typically 0.13 micron or less, for example 0.1 micron or less) An in-situ semiconductor process is provided that is capable of filling without damaging the features and causing little or no void, or vulnerable portions.

Embodiments of the present invention are described in the context of filling gaps with dielectric material for Shallow Trench Isolation (STI). Those skilled in the art will appreciate that the following description of the present invention is for illustrative purposes only and is not intended to be limiting. Still other embodiments of the present invention will be apparent to those skilled in the art. For example, although STI applications are discussed, the methods of the present invention can be applied to other kinds of cases (eg, IMD, ILD, PMD and passivation layers). In addition, the concepts discussed herein may be applied when etching a patterned blanket dielectric layer.

Details of embodiments of the present invention may be referred to by the accompanying drawings. The same reference numerals will be used throughout the drawings and the following detailed description. In this case, the terms “workpiece”, “wafer” and “substrate” may be used interchangeably. The following detailed description assumes that the invention is implemented on a wafer. The invention is not so limited, the workpiece may be a workpiece of various shapes, sizes and materials, such as displays of various sizes.

The present invention relates to depositing, forming, or maintaining an etch-selective liner to protect underlying structures during an improved deposition / etch / deposition gap fill process using an ALR chemical etch process. . This protective liner has an etching selectivity of at least about 5: 1 (preferably at least 25: 1) relative to the fill material when exposed to an ALR process used to selectively remove a portion of the fill material. Has Suitable ALR methods are described in Natzle et al. Patent 6,335,261 “Drectional CVD Process with Optimized Etchback”, the relevant part of which is incorporated herein by reference. This application describes an optimized chemical oxide removal process in which the filler material is reacted to form a solid reaction product having a specific volume greater than the filler material consumed. The overhang structure is thus converted into a reaction product structure that blocks gap openings. Thereafter, the reaction product is decomposed and removed, thereby opening up the gap and exposing unreacted filler material located below the gap. Thereafter, the deposition and etching processes are repeated as necessary to fill the gap.

As with the anisotropic plasma etch, the COR etch process lacks the selectivity between the fill oxide and the oxide structure underlying it, which can result in damage to the device. In particular, damage may result in the upper edge of the feature. This is partially in certain structures (eg, STI features in certain DRAMs or logic devices) that use silicon nitride (SiN), or silicon oxynitride (SiON) liners to protect underlying oxide layers. Is relaxed. However, in HDP CVD deposition processes, the performance of the liner can be threatened through several physical and chemical pathways, thereby reducing the selectivity for COR etching processes.

The present invention improves the method described in Natzle et al. Patents by disclosing a method for performing an etching process without damaging the underlying structure. This method has another advantage in estimating the uniformity of gap filling across zones with various feature densities.

As mentioned above, the substrate may include two or more zones having different feature densities. Usually, one or more zones will have high feature density and one or more zones will have isolated features. A cross-sectional view of a substrate having these zones is shown in FIG. 1A. Zones with high feature density, ie, “high density regions,” are indicated by arrows 126. This zone 126 includes two gaps 110 and a structure 102. Zones with lower feature densities, ie “isolated features regions,” are indicated by arrows 128. This zone 128 includes one gap 112 and one structure 118. Only a portion of the structure 118 is shown in FIG. 1A.

The gap may be formed with a bottom 104, sidewalls 106, and an inlet zone 108. The gaps 110 and 112 are typically lined with an oxide layer, eg, a thermally grown silicon oxide layer 114. Similarly, a thin layer of silicon oxide 114 (eg, 10-200 angstroms, eg, 100 angstroms) forms on the bottom 104 and sidewalls 106 of the gap before the gap is filled with the gap fill material. do.

The silicon oxide 114 passivates the silicon surface of the structure 102/118 and provides an electrically stable interface between the silicon and the gap fill material. For example, a layer of silicon nitride may be deposited over top of silicon oxide 114 to fabricate devices such as DRAM and some logic devices. For other devices, for example FLASH and some logic devices, no silicon nitride is typically deposited.

1B shows a cross section of a substrate including a protective liner 116. This liner can be formed in several ways. First, this liner 116 may be a silicon nitride layer deposited during device fabrication. This layer 116 may also be a nitrided portion of the oxide layer 114 and may have a high etch selectivity relative to a layer of silicon oxynitride, or a layer of silicon rich oxide, or a fill material. It may be another material. This protective liner 116 will function at the sidewalls and edges of the structure 102, in part as a sacrificial layer, or an etch stop layer against ALR etching.

1C shows a partially filled gap. Initial deposition partially fills the gap 110/112 with dielectric 1020 deposited by a high density plasma chemical vapor deposition (HDP CVD) process, which performs filling from the bottom to the top of the gap, This results in a thicker film on the bottom 104 than on the sidewalls 106. However, as mentioned above, in the inlet region 108 of the gap 110, an overhang 124 that makes it difficult to connect to the gap. There are several problematic depositions that result in the following: Also, a top hat shape 122 is formed on the substrate surface adjacent to the gap opening, as mentioned above, the overhang of the neutral species of the plasma reactor This results from non-directional deposition reactions and sputtering / redeposition processes, the limitations due to overhang geometry as the width of the gap to be filled decreases and as the aspect ratio increases, and The additional reentrant, the more severe (ie, the overhang structure is more severe in dense features) .On top of the wider structure 118, little top hat and overhang are formed, or fully formed. More filling material may be deposited at the bottom of the gap 112 than the gap 110. Because the filling material for the smaller gap opening 108 to be deposited at the bottom of the gap may be accessible to the gap. This is because the angle of incidence is limited: For gaps 112 with sufficiently low aspect ratios, the thickness of the underlying fill material may be the same or nearly the same on the top of the structure 118.

A portion of filler material 102 may react with one or more reactants to form solid reaction product 130. In FIG. 1D, solid reaction product 130 appears as a cross-hatched region. The solid reaction product 130 has a specific volume greater than the spent filler material 120. For example, it has a specific volume of three times or more, preferably four times or more. The substrate is exposed to a gaseous reactant reacting at the surface of the filler material. As the solid reaction product 130 is built up, the solid reaction product 130 prevents the diffusion of the reactant into the filling material 120 located below. The reaction thus reaches a self-limiting point which becomes too thick to allow further reaction of the filling material under which the solid reaction product 130 is located.

After exposure to the reactant, on either side of the gap opening, the solid reaction product 130 formed in the overhang 124 substantially or completely closes the gap 110 of the feature in the tight zone. Thus, the fill material at the bottom of the gap is consumed little or no to form the reaction product. However, the reactants continue to react with the fill material on the surface of the substrate, such as the top hat 122 and the top of the structure 118, until the reaction is complete. The reaction also continues in all regions, including the sidewalls and the bottom of the features of the isolated zone. Thus, more dense material is removed from the top of the gap than the bottom of the gap in the dense features, while almost the same amount of material is removed in all regions of the isolated features. Since the gap bottom of the dense features generally contains less original fill material deposit than the isolated features, this can result in more uniform gap filling across all areas of the substrate. In dense features, preserving the gap bottom reduces the aspect ratio of the unfilled gap while reducing the fill material on the sidewall and top hat height, which makes filling easier with subsequent deposition steps.

Small amounts of protective liners at the sidewalls and top edges of the gap may also react with the reactants. The etching selectivity ratio of the protective liner to the fill material may be about 5: 1 or greater, or preferably 25: 1 or greater. The reaction is self limiting, so the amount of filler material that is repeatedly controlled can be eliminated by allowing the reaction to complete. However, this also means that some protective liners will also be removed. Given a selectivity of 25: 1, for 200 angstrom packed material, about 4 angstroms of silicon nitride will be removed. By varying the partial pressure of the reactants, the chamber pressure, and the substrate temperature, the saturation point of the reaction can be controlled. In another embodiment, the range of the reaction can also be controlled by intermediate the reaction, also after a period of time. By stopping the reaction before completion, the amount of liner removed by the reaction can be reduced because all the filler material deposited on the ALR selective layer will be reacted first.

Solid reaction product 130 is removed by deposition. After the solid reaction product is removed, the unreacted filler material 120 is exposed, as shown in FIG. 1E. The solid reaction product is first broken down into gaseous by-products and removed by evacuation, or purging. Such decomposition can be accomplished by heating the substrate above the sublimation temperature of the solid reaction product (eg, above about 100 ° C., or preferably about 100 to 150 ° C.). After desorption and removal, the unreacted filler material and the partially underlying layer are exposed. At the bottom of the gap of the dense features, unreacted filler material remains because the solid reaction product in the gap opening sufficiently blocks the passage of the reactant to the bottom of the gap. On the side walls of the dense features, most, if not all, of the fill material is reacted and desorbed, leaving the exposed surface of the protective liner. The ALR etching process (reaction and desorption) removes more material from the gap 112 bottom of the isolated feature than the gap 110 bottom of the dense feature. After an ALR etch, depending on the amount removed in proportion to the thickness of the initially deposited fill material, the thickness below the gap 110 may be larger or smaller than the thickness below the gap 112.

1F shows the gap fill after the second deposition of the fill material. In some cases, a second deposition of this fill material will result in a fully filled gap. 1F illustrates the case where at least three depositions of the fill material are required to fill the gap. The second deposition leads to partially filled gaps 110 and 112. Once again, more fill material is deposited in the gap 112 than in the gap 110. Top hat and overhang structures are formed in the high density region of the substrate and are preferably removed by a second etching process, either by ALR or plasma etching.

1G shows the result of the second exposure to the ALR reactant. The solid reaction product 130 from the overhang closes the gap opening, so that little or all of the filler material under the gap is not reacted. Thereafter, as shown in FIG. 1H, the solid reaction product 130 is desorbed to expose the unreacted fill material and protective liner. Thereafter, as shown in FIG. 1I, the last deposition of the fill material fills the gaps 110 and 112, without any gaps, voids, or fragile portions.

fair( Process )

One method embodiment of the present invention is shown in FIG. 2, which is a process flow diagram. In operation 201, a substrate is first provided that includes a gap having an exposed surface of silicon oxide. The substrate may have high density regions and isolated feature regions. However, this method can be used on substrates that do not have different feature densities. In some cases, in certain DRAM devices, the substrate may include a protective liner layer, such as a SiN layer, that may protect the underlying structure from being exposed with an ALR etch reactant. In another case, a protective liner is formed at operation 203.

The protective liner may be formed by nitriding a smaller portion than all of the exposed oxide surface. A thickness of 10 to 100 angstroms (preferably 20 to 85 angstroms, more preferably 40 to 70 angstroms) in oxide may be nitrided. In another case, up to 50% of the oxide thickness, or preferably up to 25% of the oxide thickness may be nitrided. The nitrided layer may have an ALR etch selectivity similar to that of silicon nitride, relative to the fill material. The ALR etch selectivity is about 5: 1 or greater, preferably 25: 1 or greater.

The layer may be nitrided by exposure to nitrogen-containing plasma (eg, plasma used in low-frequency radio-frequency plasma and plasma enhanced chemical vapor deposition (PECVD) used for HDP CVD). . The plasma may be formed by a gas based on nitrogen, ammonia, or other nitrogen. An inert gas, or reactive gas, such as helium, or hydrogen, or argon may further be used to form the plasma. To draw more nitrogen ions towards the substrate, high frequency radio frequency (HF RF) bias power may or may not be applied. The nitriding process may heat the substrate to a high temperature, such as 300 ° C. or higher, or 350 ° C. or higher. The temperature may also be suitable for filling material deposition. Examples of suitable process parameters for nitriding an oxide layer in an HDP CVD chamber are as follows.

He flow rate (sccm) 0-500 N ₂ flow rate (sccm) 100-1000 Chamber pressure (mTorr) 1-20 Source (LF RF) Power (W) 1000-20000 Bias (HF RF) Power (W) 0-1000 Wafer temperature (C) 50-850 Time (s) 10-300

Also protective liners can be formed by vapor deposition. Silicon nitride, silicon oxynitride, silicon rich oxide, Al ₂ O ₃ , SiC, AlN, SiCO, SiCN, SiOC, C, BN, SiBN, SiBC, BC, GeN and GeC, which may be integrally formed into the gap Or a layer of material with other high ALR etch selectivity may be deposited. After the etching process, while some of the liners remain in the gap, some of the layers during the ALR etching process, in particular portions of the upper edge of the gap and sidewalls may be removed. Ultimately only a small amount of liner can be integrated into the gap. Such sacrificial layers are negligible unless their incorporation has a sufficient effect on the performance of the semiconductor device.

The protective liner that is deposited or already located may be modified. In some cases, silicon nitride liners may already be deposited on the trenches, for example using SACVD, or PECVD processes. In order to increase the selectivity of the already deposited liner, high density plasma can be used. Nitrogen, or argon gas, or combinations thereof (with or without other gases) may be used in the plasma to enrich the liner material and increase its selection ratio.

A selectivity ratio to at least 50: 1 silicon oxide can be obtained. The protective liner may also be heat treated. Heat treatment in the HDP CVD chamber also enriches the protective liner and increases its selectivity. The heat treatment can be used simultaneously with the plasma treatment or alone. Modifying an already existing protective liner changes the properties of the liner, so that HDP deposited liners with higher density, more desirable dielectric breakdown strength, and reduced wet etch rate Make it similar to that of

The protective liner forming operation heats the substrate to a temperature sufficient for deposition of the fill material. In embodiments in which a silicon nitride liner is already present, in selection operation 203, the substrate may be heated to a high temperature prior to filling the deposition material. In general, preheat plasma is applied to the substrate before HDP CVD deposition. In a conventional process, oxygen is used for the preheat plasma. Oxygen of the preheat plasma may oxidize a portion of the protective liner and reduce the etch selectivity. Thus, gases other than oxygen can be used in the preheating plasma, for example helium, or hydrogen, or nitrogen. In some cases, other methods for heating the substrate may be used, such as exposing the substrate to, for example, a heated pedestal, or radiant heat from a heated chamber.

In operation 207, a fill material is deposited using an HDP CVD process. Such in-situ HDP CVD deposition and etch back processes are described, for example, in US Pat. Nos. 6,335,261, 6,030,881, 6,395,150, and 6,867,086, the contents of which are incorporated herein by reference. In this invention, the fill material is first deposited without applying bias power to the substrate. This is to reduce the exposure of the protective liner to the species of plasma. The HDP CVD plasma may include oxygen and the coral will oxidize the liner if a layer of fill material is not deposited first. By not using bias power, or low levels of power, the exposure of the liner to the damaging species during HDP CVD during this initial deposition is minimized. This initial deposition can last for at least 2 seconds or until deposition of 50-100 angstrom of filler material. The process parameters for this initial deposition are as follows.

SiH ₄ flow rate (sccm) 2-300 O ₂ flow rate (sccm) 5-1000 H ₂ flow rate (sccm) 0-5000 He flow rate (sccm) 0-200 Chamber pressure (mTorr) 2-500 Source (LF RF) Power (W) 100-20000 Bias (HF RF) Power (W) 0-1000 Pedestal Temperature (C) 50-450 Time (s) 2-15

In operation 209, deposition of the fill material is continued using a conventional HDP CVD process in the same chamber using substrate bias power to attract plasma species towards the substrate surface. The filling material may be a dielectric such as silicon dioxide, USG, BSG, PSG, or BPSG. The fill material is deposited on the bottom and sidewalls of the gap and on the surface of the substrate. Deposition continues until the fill material begins to form an overhang structure (see FIG. 1C) that partially blocks the opening at the gap opening.

In some embodiments, operations 203 through 209 may occur in a different HDP CVD chamber than the operation that follows. These operations may even occur with semiconductor processing tools that are completely different from the operations that follow. An advantage of the present invention is that all operations are completely made with the same semiconductor tool, and the same vacuum environment can be used for all operations, but is not required. Fill material may be deposited using an HDP CVD chamber (eg, Ultima chamber) configured on the tool, and the remaining process operations may be completed on another tool configured with another HDP CVD chamber (eg, SPEED chamber). have. If more than two filling operations are required, any of the filling operations can be completed independently of each other following the different tools.

In stacking 211, if the substrate temperature is too high before the next operation 213, the substrate is optionally cooled. In operation 213, the substrate may be exposed to one or more reactants such that a portion of the fill material may react with the reactants to form a solid reaction product. If the substrate temperature is too high, the solid reaction product may sublimate. The solid reaction product has a higher specific volume than the fill material. In the dense features, the specific volume of the reaction product is such that the reaction product formed around the overhang blocks the gap opening sufficiently or completely to prevent the reactant from contacting the filling material below the gap (see FIG. 1D). 2 times, or preferably 3 times.

In some embodiments, the gaseous reactants are ammonia (NH ₃ ) and dry hydrogen fluoride (HF) and have a ratio of 2 ammonia to about 3 hydrogen fluoride. The scheme is as follows.

2NH ₃ + 3HF-> NH ₄ F + NH ₄ FHF

NH ₄ F + NH ₄ FHF + SiO _2- > (NH ₄ ) ₂ SiF ₆ (Solid) + H ₂ O

The solid reaction product may be ammonia hexafluorosilicate.

In another embodiment, the reactants may include hydrogen (H ₂ ), nitrogen trifluoride (NF ₃ ), NH ₄ F and NH ₄ F: HF. Ammonia fluoride (NH ₄ F), or ammonia bifluoride (NH ₄ F.HF) may be used for ammonia and hydrogen fluoride, or other reactants (e.g., ammonia (NH ₃ ), hydrogen fluoride (HF)). , Instead of being formed from hydrogen (H ₂ ), nitrogen trifluoride (NF ₃ ), nitrogen (N ₂ ) and water vapor (H ₂ O), can be introduced directly into the chamber.

For about 10 to 600 seconds, preferably for about 60 to 120 seconds, the substrate is exposed to a mixture of 1 dose of reactant. 3 shows a plot of etched (of reacted fill material) thickness versus time. The etched thickness increases with time, but the slope decreases with time (ie, the reaction rate decreases with time). After sufficient time passes, the reaction reaches a self-limit (eg, about 400-500 angstroms or more) in which prolonged exposure does not substantially elicit an additional response. If the solid reaction product becomes too thick, it is believed that the reactant no longer diffuses through the solid reaction product, thereby preventing the surface of the underlying filling material from reacting.

The partial pressure of the reactants, the chamber pressure, and the temperature of the substrate can also determine the amount of filler material that reacts. 4A shows a plot of etched oxide thickness over time, for various chamber pressures. As the pressure increases, more oxides react over a given time range. In other words, as the chamber pressure increases, the branch limit becomes higher. Still, for each chamber pressure, the reaction is self-limiting. Thus, by the chamber pressure and the exposure time, the reaction can be controlled.

The substrate temperature can also determine the amount of filler material that reacts. 4B shows a plot of the thickness of etched oxide versus pressure for various substrate temperatures. The lower the substrate temperature, the stronger the pressure increases. More oxide is etched at lower substrate temperatures, and at higher chamber pressures. On the other hand, the oxide thickness removed is not very sensitive to chamber pressure at higher substrate temperatures.

Another way to control the amount of oxide etched is to repeat the exposure and deposition operation. After the particular oxide thickness is controlled, it becomes clear from the chart that oxide is less removed with additional time. In some cases, the total process time can be improved by repeating the exposure operation and the deposition operation instead of waiting for the exposure reaction until the self-limiting completion is reached. The exposure reaction is not simply repeated. Other repeated operations include wafer movement, wafer heating and desorption (described below). For very thick oxides of about 400 to 500 angstroms or more, repeating the exposure and deposition operations can reduce the overall process time. Those skilled in the art will be able to set these (and other) process parameters to remove a specified amount of filler material, given the constraints.

In some embodiments, it may be desirable to expose the substrate to only one of the reactants for a period of about 1 to 30 seconds before introducing other reactants. For example, following initial exposure, or “wetting” with ammonia, simultaneous exposure to ammonia and draft hydrogen fluoride can lead to more uniform nucleation of the fill material.

In another embodiment, the substrate is exposed to a series of doses of the mixture of reactants. Each reactant may enter the substrate for a period of about 0.1 seconds to 60 seconds. Typically, an inert gas purge, or pumping step is followed for a period of about 0.1 seconds to 60 seconds to remove excess reaction product, or to react the byproduct. But purging the above. Or the pumping step is optional. One "cycle" includes exposure to the first reactant, an optional purging / pumping step, exposure to a second reactant, and an optional purging / pumping step. Solid reaction products are formed by reactions that are similar to simultaneous exposure to the reactants. The same reactants can be used in any order of exposure. 5 shows a plot of the thickness removed over the number of exposure cycles. The thickness etched increases with the number of cycles. Since the amount etched in each cycle is small and the number of cycles is easily controlled, this embodiment is particularly suitable for the sophisticated etching of small amounts of material. As in the previous example, over several cycles, when the solid reaction product becomes so thick that the reactants are no longer diffused into the solid reaction product, the surface of the filling material underlying it is etched away. The thickness eventually becomes saturated.

After the desired amount of filler material has been reacted, the solid reaction product in operation 215 may be removed by decomposition and evacuation, or purging. The solid reaction product, ie ammonium hexafluorosilicate, will decompose and sublimate at a temperature of about 100 ° C. or higher, preferably at a temperature of 100 to 150 ° C. The decomposition and sublimation reactions are as follows.

(NH ₄ ) ₂ SiF _6- > SiF ₄ ↑ + NH ₃ ↑ + HF ↑

Decomposition products of SiF ₄ , NH ₃ and HF are all gases that can be easily vented or purged. With (or without) an inert purging gas, removal may be accomplished by one or more vacuum sources connected to the chamber or station. Removal of the solid reaction product exposes the unreacted fill material located below, and in some areas a protective liner may be exposed (see FIG. 1E).

The aspect ratio of the unfilled portions of the gaps 110/112 is reduced by ALR etching. This is more evident in the sign 110 in the dense zone. In dense features, the fill material at the bottom of the gap is substantially unreacted, while the fill material at the sidewalls and peaks (ie, top corners) of the gap is preferably sufficiently reacted. Top hat is also reduced. Thus the depth of the gap decreases and the width increases, resulting in a lower aspect ratio.

In some cases, only one deposition is required to fill the remaining gap after ALR etching. In general, when the aspect ratio is about 3: 1 or less, and the gap opening is 700 angstroms or more, the HDP CVD process may fill the gap in one deposition. In some cases, however, two or more deposition / etch sequences are required to completely fill the gap. In one embodiment, if the remaining gap cannot be filled in one deposition, operations 203-215 can be repeated as needed to fully fill the gap (see operation 217). In other embodiments, operations 213-215 in a series of deposition / etch sequences can be replaced by HDP plasma etching (sputter etching, or reactive plasma etching, or a combination of both). For example, after the first fill material deposition and the ALR etch process, a second fill material deposition can be performed using conventional HDP CVD conditions (ie, applying bias power to the substrate). The deposition continues until the fill material forms an overhang structure at the gap opening, which partially starts blocking the opening. The overhang structure can then be removed using HDP sputter etching, or reactive plasma etching, or a series / simultaneous combination thereof. Additional HDP CVD deposition / etch steps may be performed as needed to fill the gap. Any number of deposition and ALR etch steps may be performed by one skilled in the art before or after the HDP plasma etch step is used.

A second protective liner can be formed to protect the unreacted fill material. This second liner may or may not be the same material as the first protective liner. Suitable second liner materials may be SRO, or SiN, or SiON, or nitrided fill material. The thickness of the second liner can be adjusted so that most, if not all, of the second liner is etched during the second ALR etch. Incorporating different materials into the features of a sufficiently sacrificial second protective liner may reduce any negative effects on device performance.

Oxidation concerns for the second protective liner are essentially the same as for the first layer. Thus, when the second liner is formed, during the initial time period during HDP CVD deposition, oxygen should not be used in the preheat plasma, and substrate ice power should not be applied.

When the remaining gap has a geometry that can be filled by one deposition, the filler material is deposited to fill the gap. (See operation 219) The process parameters for the final deposition may be similar to that of the deposition during that time. Since there is no subsequent ALR etch, the final deposition can be performed under conventional, unmodified HDP CVD processes.

Device( Apparatus )

In one embodiment, a single semiconductor process tool may be configured to perform every operation of the method embodiments of the present invention. 6 shows an example of a semiconductor process tool 600 that includes two HDP CVD chambers 605/607 and a multi-station chamber 609 that can perform the operation of an ALR etch method embodiment.

Partially assembled semiconductor substrates enter system 600 from cassette 601 or from a front-opening unified pod (FOUP). By an atmospheric robot (not shown in the figure), the substrate is moved from the FOUP to an atmospheric chamber 619 individually, in one of two load locks. After the load lock pressure is pumped low to the pressure of the moving chamber 603, a moving chamber robot (not shown in the figure) moves the substrate to the first process chamber module 605, or 607. Each process chamber module may or may be configured to perform both protective liner formation, HDP CVD fill material deposition, and HDP plasma etching (optional). In some embodiments, the chamber module may be specialized for protective liner formation, or fill material deposition operations. In one embodiment, the substrate enters chamber 605 to form a protective liner by nitriding the oxide surface, and then into chamber 607 to deposit the fill material. In yet another embodiment, operations are performed in sequence in the same chamber 605, or 607, by varying process gas and flow rate, and varying chamber pressure, source RF power, bias power, substrate pedestal temperature.

An ALR etch operation may be performed in a multi-station chamber, such as chamber 609 of FIG. 6. The ALR etch module 209 may have more than one station. As shown, the module has four stations. Each station may perform the same operation or different operations. In one embodiment, station 1 611 delivers an ALR reactant that causes a reaction to form a solid reaction product. By decomposing or subliming the solid reaction product, and by removing the byproduct gas, station 2 613 removes the solid reaction product. Station 3 615 may repeat the exposure of the reactant causing a further etch reaction. Station 4617 may then remove additional solid reaction product. In this configuration, unwanted material can be further removed from the top and sidewalls of the substrate.

In another configuration, two of the stations (eg, 611 and 613) can be used to control the temperature of the substrate using a pedestal having a controlled temperature, or other heating (cooling) source. One of the remaining two stations 615 can be used to deliver the reactants to form a solid reaction product. The last remaining station 617 can be used to decompose the solid reaction product and remove the by-product gas.

In an additional configuration, one of the stations (eg, 613) can be used to deliver the first reactant and to perform an optional post exposure purge, or evacuation step. Then another station (eg, 615) can be used to deliver the second reactant and to perform an optional post-exposure purging, or evacuation step. As mentioned above, the last remaining station 617 can be used to decompose the solid reaction product and remove the byproduct gas. In this example, as mentioned above, a first station (eg, 613) can be used to control the temperature of the substrate.

Individual stations in the multi-station chamber 609 may be micro-volume stations. The micro-volume station may have a volume of 1 liter or less, preferably 500 milliliters. Using a micro-volume station can reduce the amount of reactants used and save material costs. Individual stations may also have a clam shell configuration such that the volume inside the station can be isolated inside the larger chamber 609. Individual stations may be isolated by gas curtains. Of course, other configurations for isolating the internal volume of the station, as well as configurations in which the station is not isolated, may be used.

After an ALR etch operation in chamber 609, if no further deposition and etching is required, the substrate is returned to load lock 621 for cooling before exiting tool 600 through FOUP 601. . Alternatively, load lock 621 may be used for cooling after an HDP CVD deposition operation. However, in most embodiments, after an ALR etch operation in chamber 609, the substrate is moved to one of the HDP CVD chambers 605/607 for deposition of fill material.

In yet another embodiment, the semiconductor process tool may have several single station chambers each specialized for one operation or configured to perform all the operations in sequence. For example, chamber 609 may be a single-station chamber that may be configured to perform an ALR etch operation. In addition, two or more chambers 609 may be configured on the tool.

The apparatus may also include a controller configured to execute the set of instructions. The set of instructions includes instructions for depositing a fill material up to EO where the overhang structure will partially block the gap opening, instructions for reacting one or more reactants with a portion of the fill material to form a solid reaction product, and a solid half It may be an instruction to desrob the product. The set of instructions may also include instructions for forming a protective liner before the first fill material deposition step, or after any ALR etch step. The set of instructions may also include instructions for performing a conventional HDP CVD deposition / etching step. These instructions are for performing operations in the method embodiments of the present invention using various chambers of the device for different operations.

Suitable semiconductor process tools can be C2, or C3 SPEED from Novellus System, Inc. (San Jose, Calif.), Comprising one or more HDP CVD chambers and an ALR etch module. Another suitable semiconductor process tool may be a SiCoNo tool from Applied Material, Inc. (Santa Clara, Calif.), Or Centura, comprising one or more Ultima chambers and other chambers.

In yet other embodiments, two or more semiconductor processing tools may be used to perform the operations of the method embodiments. For example, the ALR optional layer can be formed with different tools, such as VECTOR, or SEQUEL tools from Novellus Systems, Inc. The ALR etch process can be performed in a modified PDL tool from Novellus Systems, Inc.

Experimental data

Tests were conducted to test the improvement of the ALR etch selectivity using the embodiments of the invention mentioned above. On two identical substrates with SiN layers of nominal thickness 45 nm +/- 1 nm, an ALR etch process was performed. For the first substrate, the substrate was exposed (for 30 seconds) to a preheated plasma containing oxygen and a thermal oxide fill material was deposited.

For the second substrate, the substrate was not exposed to preheated plasma containing oxygen. Two ALR cycles removed a total of 450 angstroms of thermal oxide material and 225 angstroms during each cycle. The thickness of the liner at the center of the substrate is summarized as follows.

Board One 2 fair Conventional HDP Preheating HDP non-preheat Average SiN Liner Thickness 36.3 nm 43.1 nm Thickness range 26.7-40.7 nm 38.6-50.6 nm Thickness standard error 4.6 nm 3.4 nm Average etching selectivity ~ 7: 1 ~ 25: 1

This test shows that the etch selectivity of the SiN liners exposed to conventional HDP preheat plasma is about 7: 1 and the edges of the trenches have the lowest etch selectivity 4: 1. However, the etch selectivity of the SiN liner (substrate 2), which was not exposed to HDP plasma, was about 25: 1 while maintaining a larger portion of the liner. It is believed that high density plasma oxidizes a portion of the SiN liner and converts it to SiON with a lower ALR etch selectivity. This oxidation was avoided on the second substrate where the deposition was performed without HDP preheating. The test suggests that a modified HDP CVD process (without oxygen in the preheat plasma, no initial bias power applied) will be effective to maintain the etch selectivity (about 25: 1) of the SiN liner.

1A shows a cross-sectional view of a multi-stage gap filling process according to the present invention.

2 is a process flow diagram illustrating a process according to the present invention.

3 is a plot of etched thickness over time for an embodiment according to the present invention.

4A is a plot of thickness etched over time for increasing reactant pressure, in accordance with an embodiment in accordance with the present invention.

4B is a plot of thickness etched over chamber pressure for increasing substrate temperature, in accordance with an embodiment in accordance with the present invention.

5 is a plot of thickness etched over a number of cycles, in accordance with an embodiment in accordance with the present invention.

6 is a block diagram of a suitable plasma processing system for carrying out a multi-stage gap filling process according to the present invention.

Claims (29)

A method for filling a gap on a semiconductor substrate, the method comprising (a) forming a first liner in the gap (b) depositing a fill material in the gap (c) reacting said filler material with at least one reactant to form a solid reaction product having a specific volume greater than said filler material, (d) desorbing the solid reaction product, and (e) further depositing said fill material Including, wherein Oxide located beneath the liner is protected from reaction in step (c). The method of claim 1, wherein the depositing step (b) (a) heating the substrate without exposing it to oxygen, (b) initially applying no bias power to the substrate, or applying a low bias power and depositing a fill material Method for filling a gap on a semiconductor substrate comprising a. The method of claim 1, Prior to step (e), repeating steps (b) to (d) one or more times A method for filling a gap on a semiconductor substrate further comprising. The method of claim 3, wherein Prior to repeating steps (b) to (d), forming a second liner A method for filling a gap on a semiconductor substrate further comprising. 5. The method of claim 4, wherein the first liner and the second liner comprise different materials. 5. The method of claim 1 or 4, wherein forming the first liner comprises nitriding a portion of the oxide of the feature to form a nitrided oxide layer. A method for filling gaps on semiconductor substrates. The method of claim 6, wherein the nitriding step (a) exposing the oxide of the feature to a nitrogen-containing plasma A method for filling a gap on a semiconductor substrate comprising a. 7. The method of claim 6, wherein the nitrided oxide layer has a thickness of 10 to 100 angstroms. 3. The method of claim 2, wherein no bias power is applied to the substrate or at least two seconds, or a low bias power is applied. 5. The method of claim 1 or 4, wherein forming the first liner comprises depositing a dielectric material having an etch selectivity to a fill material of at least 5: 1. Way. The method of claim 1 wherein the liner material is Silicon nitride (SiN), silicon rich oxide (SRO), silicon oxynitride (SiON), silicon carbide (SiC), aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), silicon Carbon nitride (SiCN), silicon oxycarbide (SiOC), carbon (C), boron nitride (BN), silicon boron nitride (SiBN), silicon boron carbide (SiBC), boron carbide (BC), germanium nitride A method for filling a gap on a semiconductor substrate comprising one of (GeN) and germanium carbide (GeC). The method of claim 1, wherein the reacting and desorbing steps remove most of the liner. The method of claim 1, After desorbing the solid reaction product, oxidizing the remaining liner A method for filling a gap on a semiconductor substrate further comprising. The method of claim 1, wherein the detaching step (a) decomposing the solid reaction product by heating the substrate to a temperature of at least 100 ° C, and (b) removing the degraded reaction product Method for filling a gap on a semiconductor substrate comprising a. The method of claim 1, wherein the reactant Ammonia (NH ₃ ), dry hydrogen fluoride (HF), hydrogen (H ₂ ), nitrogen trifluoride (NF ₃ ), nitrogen (N ₂ ), water vapor (H ₂ O), ammonium fluoride (NH ₄ F) And NH ₄ F: HF. The method of claim 15, wherein the reactant comprises ammonia and dry hydrogen fluoride in a ratio of 2: 3. The method of claim 1, wherein the depositing comprises a high density plasma chemical vapor deposition (HDP CVD) process. The method of claim 1, (a) heating the substrate without exposing it to oxygen, (b) depositing a fill material, (c) etching the fill material using anisotropic plasma or reactive plasma, or both anisotropic plasma and reactive plasma. A method for filling a gap on a semiconductor substrate further comprising. The method of claim 1, wherein the step of reacting comprises simultaneously exposing the filling material to the first reactant and the second reactant. 20. The method of claim 19, wherein the step of reacting further comprises exposing the fill material to the first reactant prior to simultaneously exposing the fill material to the first and second reactants. Method for filling the gap. The method of claim 1, wherein the step of reacting (a) exposing the filler material to a first reactant, (b) exposing the filler material to a second reactant, and (c) repeating exposure to the reactant until the desired amount of solid reaction product is formed A method for filling a gap on a semiconductor substrate comprising a. 22. The method of claim 21 wherein the step of reacting further comprises evacuating or purging the chamber after exposure to each reactant. Way. 23. The method of claim 19, 20, 21 or 22, wherein the first reactant and the second reactant are ammonia and dry hydrogen fluoride to fill the gap on the semiconductor substrate. Way. A method for filling a gap lined with a silicon nitride layer, the method comprising (a) heating the substrate without exposing it to oxygen, (b) depositing a fill material, (c) reacting said filler material with at least one reactant to form a solid reaction product having a specific volume greater than said filler material, (d) desorbing the reaction product, thereby exposing an unreacted filler material located under the feature, and (e) further depositing said fill material Wherein the silicon nitride liner is protected from the reaction in step (c). The method of claim 24, Initial deposition of a fill material having a sputter to deposition (S / D) ratio of less than 0.1 Method for filling the gap, characterized in that further comprises. 27. The method of claim 26, wherein the initial deposition step occurs for a period of at least two seconds. The method of claim 24, (a) heating the substrate without exposing it to oxygen, (b) depositing a fill material, and (c) etching the fill material using anisotropic plasma or reactive plasma, or both anisotropic plasma and reactive plasma. Method for filling the gap, characterized in that further comprises. 28. The method of claim 18 or 27, wherein the plasma is generated using at least one of a fluorine containing gas or a hydrogen containing gas. In a semiconductor processing apparatus, the apparatus is (a) one or more wafer processing chambers configured to form a liner on a substrate comprising a gap, (b) one or more wafer processing chambers configured to deposit a fill material on the substrate, and (c) one or more wafer processing chambers configured to react a portion of the substrate to form a solid reaction product and to desorb the solid reaction product. Semiconductor processing apparatus comprising a.

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