KR20090053587A - Liquid crystal display device and method for driving the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit and a driving method of a liquid crystal display device capable of improving image quality by reducing distortion of a wireless signal. A clock modulator which generates signals and selects and outputs one of them according to a selection signal from the outside; And a mini-LVDS transmitter for converting and outputting an image display data signal from a timing controller and a modulated clock signal from the clock modulator to output low voltage differential signaling (LVDS).

LCD, LVDS, TTL, Phase Locked Loop, PLL, Clock Signal

Description

Liquid crystal display device and method for driving the same

The present invention relates to a liquid crystal display device, and more particularly, to a driving circuit and a driving method of a liquid crystal display device capable of preventing distortion of a wireless signal.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which pixel regions are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

In general, laptops have an antenna for receiving wireless signals for the Internet from the outside. The radio signal is supplied to an internal circuit portion through the antenna. Various circuit parts therein modulate and process the radio signal appropriately so that an image is displayed on the liquid crystal panel.

On the other hand, the various circuits therein modulate and process internal image display data in addition to these radio signals. In order to process such image display data, an internal circuit generates a clock signal. In the related art, since the clock pulse has a constant frequency, there is a high probability that the frequency of the clock pulse and the frequency of the radio signal are synchronized with each other. Thus, constructive interference between the two signals frequently occurs. As a result, noise in a specific band is greatly increased, which causes the wireless signal to be distorted when using a wireless signal such as the Internet.

The present invention has been made to solve the above problems, and to provide a driving circuit and a driving method of the liquid crystal display device that can prevent the distortion of the wireless signal by reducing the EMI by changing the frequency of the clock signal every time the object There is this.

The driving circuit of the liquid crystal display device according to the present invention for achieving the above object, generates a plurality of modulated clock signals having different frequencies by modulating the frequency of the clock signal supplied from the system, the selection signal from the outside A clock modulator for selecting one of these and outputting the selected one; And an LVDS transmitter for converting and outputting an image display data signal from a timing controller and a modulated clock signal from the clock modulator to output low voltage differential signaling (LVDS).

In addition, the driving method of the liquid crystal display according to the present invention for achieving the above object comprises the steps of generating a plurality of modulated clock signals having different frequencies by modulating the frequency of the clock signal supplied from the system; And selecting one of the modulated clock signals according to a selection signal, and converting and outputting the selected modulated clock signal by low voltage differential signaling (LVDS).

The liquid crystal display and the driving method according to the present invention have the following effects.

According to the present invention, the clock modulator periodically changes the clock signal to a clock signal having a different frequency, thereby drastically reducing the constructive interference between the frequency of the clock signal and the frequency of the radio signal. Accordingly, noise can be greatly reduced in a specific band, thereby preventing distortion of the wireless signal when using a wireless signal such as the Internet.

1 illustrates a driving circuit of a liquid crystal display according to an exemplary embodiment of the present invention.

The driving circuit of the liquid crystal display according to the exemplary embodiment of the present invention is for driving a liquid crystal panel, and the liquid crystal panel includes a plurality of gate lines and a plurality of data (R / G / B) lines crossing each other. A pixel is formed in each pixel area where the gate lines and the data (R / G / B) lines are vertically intersected, and the pixel electrode of the pixel area is a source of a thin film transistor (TFT) as a switching element. It is connected to the data (R / G / B) line via a terminal and a drain terminal. The thin film transistor is turned on by a scan pulse applied to a gate terminal via the gate line, and the data (R / G / B) signal of the data (R / G / B) line is charged to the pixel electrode. Be sure to

As shown in FIG. 1, the driving circuit of the liquid crystal display according to the present invention for driving the liquid crystal panel includes an antenna 201, a signal processor 202, a system 203, a timing controller TC, The mini-LVDS transmitter mLTx, the mini-LVDS receiver mLRx, the gate driver GD, and the data driver DD are included.

The antenna 201 receives data transmitted wirelessly from an external base station and supplies it to the signal processor 202.

The signal processor 202 processes the data appropriately for processing by the system 203 and supplies the data to the system 203.

The system 203 uses the data for image display data (R / G / B), horizontal synchronization signal (Hsync), vertical synchronization signal (Vsync), data enable signal (DE), and clock signal (CLK). ) The horizontal synchronization signal Hsync, the horizontal synchronization signal Hsync, the data enable signal DE, and the image display data R / G / B are supplied to the timing controller TC, and the clock is rotated. The signal CLK is supplied to the clock modulator 222. At this time, the image display data R / G / B, the vertical synchronization signal Vsync, the data enable signal DE, and the clock signal CLK from the system 203 are LVDS transmitter LTx and LVDS. The timing controller TC is supplied to the timing controller TC via the receiver LRx. That is, the image display data R / G / B, the vertical synchronization signal Vsync, the data enable signal DE, and the clock signal CLK supplied to the system 203 are TTL (Transistor Transistor Logic). As a signal of the scheme, these signals are converted into the LVDS scheme through the LVDS transmitter LTx. The signals converted to the LVDS scheme are converted back to the TTL scheme through the LVDS receiver LRx. The LVDS transmitter LTx may be embedded in the system 203.

The timing controller TC includes a control signal generator 312 and a data processor 313. The horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, and the data enable signal DE from the LVDS receiver LRx are provided to the control signal generator 312, and are supplied from the LVDS receiver LRx. Image display data R / G / B is supplied to the data processing unit 313.

The control signal generator 312 may include a gate control signal for controlling the operation of the gate driver GD using the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, and the data enable signal DE. A data control signal DCS for controlling the GCS and the data driver DD is generated.

The data processing unit 313 basically plays a role of rearranging and outputting the data R / G / B from the system 203. In addition to the basic role, the data for displaying the image in order to increase the quality of the image. It may further include various known components capable of modulating (R / G / B). For example, the data processor 313 may further include an overdriving circuit that modulates the data R / G / B to compensate for the response time of the liquid crystal.

The clock modulator 222 receives the clock signal CLK from the LVDS receiver LRx and multiplies or divides the clock signal CLK to generate a plurality of modulated clock signals MCLK. Then, any one of the generated modulated clock signals MCLK is selected and output according to the selection signal SS from the outside. Each of the modulated clock signals MCLK has a different frequency and has the same phase as the clock signal CLK. The modulated clock signal MCLK may have a higher frequency or a lower frequency than the clock signal CLK.

According to the present invention, the clock modulator 222 periodically changes the clock signal CLK to a clock signal CLK of a different frequency, for example, every frame period. The constructive interference between frequencies of the signal can be greatly reduced. Accordingly, noise can be greatly reduced in a specific band, thereby preventing distortion of the wireless signal when using a wireless signal such as the Internet.

The data R / G / B from the data processor 313 and the modulated clock signal MCLK from the clock modulator 222 are supplied to the mini-LVDS transmitter mLTx. The mini-LVDS transmitter mLTx converts the modulated clock signal MCLK and the data R / G / B into a low voltage differential signaling (LVDS) scheme, and converts the modulated clock signal MCLK and data. (R / G / B) is supplied to the mini-LVDS receiver (mLRx).

The mini-LVDS receiver mLRx converts the modulated clock signal MCLK and the data R / G / B of the LVDS method into the TTL method, and the converted modulated clock signal MCLK and the data R / G. / B) is supplied to the data driver DD.

After the data driver DD latches the data R / G / B in synchronization with the modulation clock signal MCLK, the data driver DD corrects the latched data R / G / B according to a gamma voltage. The data driver DD converts the data (R / G / B) corrected by the gamma voltage into analog data (R / G / B) and supplies the data (R / G / B) lines one by one. do. The mini-LVDS receiver LRx may be embedded in the data driver DD.

FIG. 2 is a detailed configuration diagram of the clock modulator 222 of FIG. 1, and FIG. 3 is a diagram illustrating a waveform of a selection signal SS supplied to a selector included in the clock modulator 222 of FIG. 2. .

As illustrated in FIG. 2, the clock modulator 222 includes a phase locked loop 355 and a selector 380.

The phase locked loop unit 355 multiplies or divides the clock signal CLK from the system 203 to generate a plurality of modulated clock signals MCLK1 to MCLKn having different frequencies. To this end, the phase locked loop 355 includes a plurality of phase locked loop circuits PLL1 to PLLn. Each of the phase locked loops PLL1 to PLLn receives the clock signal CLK from the LVDS receiver LRx and multiplies or divides the clock signal CLK in different multiples. Accordingly, the frequencies of the modulated clock signals MCLK1 to MCLKn outputted from the respective phase locked loop circuits PLL1 to PLLn are different. However, the phases of each of the modulation clock signals MCLK1 to MCLKn are the same.

The selector 380 selects and outputs any one of a plurality of modulated clock signals MCLK1 to MCLKn from the phase locked loop 355 according to an external selection signal SS. That is, the selector 380 receives the modulated clock signals MCLK1 to MCLKn from the phase locked loop circuits PLL1 to PLLn and modulates the clock signal according to a selection signal SS from the outside. One of the signals MCLK1 to MCLKn is selected and output.

The selector 380 may randomly select and output any one of the plurality of modulation clock signals MCLK1 to MCLKn every frame period according to the selection signal SS.

In addition, the selector 380 sequentially outputs first to p-th modulation clock signals (p is a natural number greater than 1) once during the first to p-frame periods according to the selection signal SS. The first to p-th modulation clock signals may be sequentially output from the p + 1 frame period having the same length as the first to p-th frame period again during the q th frame period (q is a natural number greater than p + 1). .

For example, assuming that there are three phase locked loop circuits (first to third phase locked loops PLL1 to PLL3) in the clock modulator 222, the clock modulator 222 has different frequencies. Three modulation clock signals (first to third modulation clock signals MCLK1 to MCLK3) may be generated, as shown in Fig. 4, when the selection signal SS is generated in the first frame period. The unit 380 selects and outputs the first modulated clock signal MCLK1 in response to the first selection signal SS. Then, when the second frame and the selection signal SS are generated again, the selection unit ( 380 selects and outputs the second modulated clock signal MCLK2 in response to the second select signal SS. Next, when the select signal SS is generated again in the third frame period, the selector 380 selects and outputs the third modulated clock signal MCLK3 in response to the third selection signal SS. Thereafter, during the fourth frame period, the selector 380 selects and outputs the first modulated clock signal MCLK1 again in response to the fourth select signal SS. In case of three, the selector 380 selects the first modulated clock signal MCLK1 in the 3k + 1 frame period, selects the second modulated clock signal MCLK2 in the 3k + 2 frame period, and In the third k + 3 frame period, the third modulated clock signal MCLK3 is selected.

4 is a detailed block diagram of the mini-LVDS transmitter mLTx of FIG. 3.

The mini-LVDS transmitter mLTx includes an LVDS converter 444 and a plurality of buffers 540, as shown in FIG. 4.

The data (R / G / B) includes red image data (R), green image data (G), and blue image data (B), wherein the k-bit red image data (R) and the k-bit green color Image data G, k-bit blue image data B, and a modulated clock signal MCLK are supplied to the LVDS converter 444 via respective transmission lines. For example, if the red image data (R), the green image data (G), and the blue image data (B) are 6 bits each, 18 transmission lines for these data (R / G / B) and the A total of 19 transmission lines are required, including one transmission line for transmitting the modulated clock signal MCLK.

The LVDS converter 444 converts the data R / G / B into the LVDS method using the modulated clock signal MCLK, and also converts the modulated clock signal MCLK itself into the LVDS method. The modulated clock signal MCLK and data R / G / B converted by the LVDS method are supplied to the mini-LVDS receiver mLRx through the buffer 540. The clock modulator 222 may be embedded in the mini-LVDS transmitter LTx.

The selection unit 380 may be controlled by using the vertical synchronization signal Vsync or the data enable signal DE instead of the selection signal SS.

FIG. 5 is a diagram illustrating a waveform of the vertical synchronization signal Vsync supplied to the selector 380 included in the clock modulator 222 of FIG. 4.

As shown in FIG. 5, the vertical synchronization signal Vsync is a signal indicating the start period of every frame, and the vertical synchronization signal Vsync has a period of one frame period. The selector 380 selects one of the modulated clock signals MCLK1 to MCLKn according to the vertical synchronization signal Vsync from the LVDS receiver LRx. For example, the selector 380 selects one of the modulation clock signals MCLK at every rising edge period when the vertical synchronization signal Vsync transitions from a low state to a high state, and the selected modulation clock signal is selected. It can be maintained to be output during the high state period. The modulated clock signal MCLK may be selected randomly or regularly as described above.

FIG. 6 is a diagram illustrating a waveform of the data enable signal DE supplied to the selector 380 included in the clock modulator 222 of FIG. 4.

As shown in FIG. 6, the data enable signal DE indicates a signal R / G / B of one horizontal line, and the data enable signal DE corresponds to one horizontal period of one horizontal period. Has a cycle. As illustrated in FIG. 6, the selector 380 selects one of the modulated clock signals CLK according to the data enable signal DE from the LVDS receiver LRx. For example, the selector 380 selects one of the modulation clock signals MCLK1 to MCLKn for each rising edge period in which the data enable signal DE transitions from a low state to a high state, and selects the selected modulation. The clock signal can be maintained to be output during the high state period. The modulated clock signal MCLK may be selected randomly or regularly as described above.

7A to 7D are diagrams for comparing the magnitudes of noise generated in a notebook computer having a drive circuit according to an embodiment of the present invention and noise generated in a notebook computer having a conventional drive circuit.

The inside of the notebook computer is equipped with two antennas (left antenna, right antenna) for wireless internet communication. FIGS. 7A and 7C show the amount of noise inside the notebook that affects the wireless signal input through the left antenna. As shown, Figure 7a shows the noise level generated during communication in the 200khz band (band width), Figure 7d shows the noise level generated during communication in the 5Mhz band. 7B and 7D are diagrams illustrating the amount of noise in a notebook that affects a wireless signal input through a right antenna, and FIG. 7B illustrates the amount of noise generated during communication in a 200khz band. Shows the noise generated when communicating in the 5Mhz band.

7A to 7D, graphs A (gr_A) represent noise levels required by the buyer side, and graphs B (gr_B) and C (gr_C) represent noise levels generated in a notebook computer having a conventional driving circuit. The graph D (gr_D) shows the magnitude of noise generated in the notebook computer having the drive circuit of the present invention.

Looking at these graphs, it can be seen that the magnitude of the noise generated in the notebook computer having the drive circuit of the present invention is smaller than the noise generated in the notebook computer having the conventional drive circuit, which is close to the noise level required by the buyer. Can be.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1 illustrates a driving circuit of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a detailed configuration diagram of the clock modulator of FIG. 1. FIG.

3 is a view illustrating waveforms of a selection signal supplied to a selection unit included in the clock modulator of FIG. 2.

4 is a detailed block diagram of the mini-LVDS transmitter of FIG.

FIG. 5 is a diagram illustrating a waveform of a vertical synchronization signal supplied to a selector included in the clock modulator of FIG. 2.

FIG. 6 is a diagram illustrating a waveform of a data enable signal supplied to a selector included in the clock modulator of FIG. 2. FIG.

7A to 7D are diagrams for comparing the magnitudes of noise generated in a notebook computer having a drive circuit and noise generated in a notebook computer having a conventional drive circuit according to an embodiment of the present invention.

* Description of the main parts of the drawings

201: antenna 202: signal processor

203: system LTx: LVDS transmitter

LRx: LVDS Receiver TC: Timing Controller

312: control signal generation unit 313: data processing unit

222: clock modulator mLTx: mini-LVDS transmitter

mLRx: mini-LVDS receiver GD: gate driver

DD: Data Driver

Claims (10)

A clock modulator for modulating a frequency of a clock signal supplied from a system to generate a plurality of modulated clock signals having different frequencies, and selecting and outputting one of them according to a selection signal from an external device; And, And a mini-LVDS transmitter for converting and outputting an image display data signal from a timing controller and a modulated clock signal from the clock modulator to output low voltage differential signaling (LVDS). The method of claim 1, The clock modulator, A phase locked loop unit multiplying or dividing a clock signal from the system to generate a plurality of modulated clock signals having different frequencies; And, And a selection unit for selecting and outputting any one of a plurality of modulation clock signals from the phase-locked loop unit according to a selection signal from an external device. The method of claim 2, The phase fixing loop portion, And a plurality of phase-locked loop circuits receiving a clock signal from the system and multiplying or dividing the clock signal by different multiples. The method of claim 2, And the selection signal is generated once in one frame period. The method of claim 4, wherein And the selector randomly selects and outputs any one of a plurality of modulated clock signals in every frame period according to the selection signal. The method of claim 4, wherein The selector sequentially outputs first to pth modulated clock signals (p is a natural number greater than 1) once in a first to pth frame period according to the selection signal, and is equal to the first to pth frame period. And the first to pth modulated clock signals are sequentially output from the p + 1 frame period having a length to the q th frame period (q is a natural number larger than p + 1). The method of claim 1, The timing controller, A data processor for rearranging the data signals from the system and performing modulation for various effects and transmitting the modulated data to the LVDS transmitter; And, And a control signal generator for outputting a gate control signal and a data control signal by using a horizontal synchronization signal, a vertical synchronization signal, and a data enable signal from the system. The method of claim 1, A mini-LVDS receiver which receives an LVDS type data signal and a modulated clock signal from the mini-LVDS transmitter and converts it into a TTL scheme; And, And a data driver receiving the data signal and the clock signal from the mini-LVDS receiver to generate an analog pixel voltage signal. The method of claim 1, And the selection signal is a vertical synchronization signal indicating a start of one frame period or a data enable signal indicating a data of one horizontal period. Modulating a frequency of a clock signal supplied from the system to generate a plurality of modulated clock signals having different frequencies; And, And selecting one of the modulated clock signals according to a selection signal, and outputting the selected modulated clock signal by converting a low voltage differential signaling (LVDS) signal.

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