KR20090046944A - Modular command structure for memory and memory system - Google Patents

Abstract

A system including a memory system and a memory controller is coupled to the host system. The memory system has at least one memory device for storing data. The controller translates the request from the host system into one or more separable commands that can be interpreted by the at least one memory device. Each command has a modular structure that includes an address identifier for one of the at least one memory device and a command identifier that represents an operation to be executed by one of the at least one memory device. . The at least one memory device and the controller are in a series-connected configuration for communication, such that only one memory element is in communication with the controller for input into the memory system. The memory system may include a plurality of memory devices connected to a common bus.

Description

Modular command structure for memory system and memory {MODULAR COMMAND STRUCTURE FOR MEMORY AND MEMORY SYSTEM}

This application claims U.S. Provisional Application No. 60 / 839,329, filed Aug. 22, 2006, U.S. Provisional Application No. 60 / 902,003, filed Feb. 16, 2007, and U.S. Provisional Application No. 60 / 892,705 (2007). Claim the benefit of priority).

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to semiconductor memory devices and, more particularly, to systems having multiple interconnected semiconductor memory devices with command structures for memory devices.

Semiconductor memory devices are commonly found in many industrial and consumer electronics. Increasing demands for higher memory capacities, along with increasing demands for smaller sizes, lead to a desire for memory with densities that are difficult to achieve. As a result, multiple memory devices are often connected together to meet large memory requirements. Such multi-device memory systems may be implemented together in a single package (ie, multi-chip system) or in multiple memory device packages grouped together on a printed circuit board.

In the case where multiple semiconductor memory devices are interconnected to function as a single system, the controller includes data between the individual memory devices and an external interface that provides a request to store data, access data, and process the data in the system. Manage the flow The command structure is used by the controller to provide the requests to the individual memory devices containing the data. The command structure may depend on the structure of interconnected memory devices and adversely affect the performance of the system. For example, if individual memory devices are communicated with a controller via a common bus, only one of the individual memory devices may be asserted at any given time. If individual memory devices are serially interconnected in a chain structure in which only one memory device is connected to the controller, the commands for the memory devices located later in the chain are executing commands that cannot be interrupted. By earlier memory devices, there may be a significant delay. In the structure of serially connected memory devices, the processing of a command in one device stops all subsequent transmission of the command to the memory devices, resulting in the suspension of any further processing in the system.

According to an aspect of the present invention, a device identifier includes an address for one memory device of a plurality of memory devices and a bank address for one memory bank of a plurality of memory banks in one of the plurality of memory devices. ; And a command identifier including an operation code representing an operation to be executed by one of the plurality of memory devices.

According to another aspect of the invention, there is provided a plurality of separable commands representing a request from a processor for accessing one of the plurality of memory devices; Each of the plurality of separation commands includes an address for one of the plurality of memory devices and a bank address for one of the plurality of memory banks in one of the plurality of memory devices. Identifier; And a command identifier comprising an operation code representing an operation to be executed by one of the plurality of memory devices.

According to another aspect of the invention, a memory system including at least one memory device for storing data; A processor for managing a request to access the memory system; And a controller for translating a request from the processor into one or more separable commands that can be interpreted by the at least one memory device, wherein each command is associated with an address identifier for one of the at least one memory device. A controller having a modular structure that includes a command identifier representing an operation to be executed by one of the at least one memory device; The system is provided with the at least one memory device and the controller connected in series for communication.

According to another aspect of the present invention, there is provided a controller for a system having a plurality of memory devices for storing data, the controller being in a serial configuration for communication with the plurality of memory devices, wherein the controller is configured for the plurality of memory devices. A first connector for receiving a request from a processor to access a memory device; A translator for translating a request from the processor into a plurality of separable commands that can be interpreted by the plurality of memory devices, each command comprising an address identifier and a plurality of address identifiers for one of the plurality of memory devices; A translator having a modular structure including a command identifier representing an operation to be executed by one of the memory devices; And a second connection in serial communication with one of the plurality of memory devices for issuing the plurality of separable commands.

According to another aspect of the invention, there is provided a method comprising determining an address comprising an address for at least one memory device; Identifying a plurality of operations to jointly execute a request to access the at least one memory device; And providing a plurality of separable commands to the at least one memory device, each command including a device identifier comprising an address and a command identifier comprising one of the plurality of operations, wherein the command A method is provided for requesting access to at least one memory device, wherein the identifier can be interpreted by the memory device.

According to one embodiment of the invention, a command structure is provided that includes a plurality of separable commands that represent a request to access one of the plurality of memory devices. Each of the plurality of disconnect commands includes an address for one of the plurality of memory devices and a bank address for one of the plurality of memory banks in one of the plurality of memory devices. ; And a command identifier including an operation code representing an operation to be executed by one of the plurality of memory devices.

According to another embodiment of the present invention, an apparatus comprising an address for one memory device of a plurality of memory devices and a bank address for one memory bank of a plurality of memory banks in one of the plurality of memory devices Identifier; And a command identifier comprising an operation code representing an operation to be executed by one of the plurality of memory devices.

According to another embodiment of the invention, a memory system including at least one memory device for storing data; A processor for managing a request to access the memory system; And a controller for translating a request from the processor into one or more separable commands that can be interpreted by the at least one memory device, wherein each command is associated with an address identifier for one of the at least one memory device. A controller having a modular structure that includes a command identifier representing an operation to be executed by one of the at least one memory device; The system is provided with the at least one memory device and the controller connected in series for communication.

For example, at least one memory device includes at least one memory bank. The address identifier may include a device address for one of the at least one memory device and a bank address for one of the at least one memory bank. For example, the memory device is a flash device, such as a NAND-type flash memory device.

If the memory system includes a plurality of memory devices, the devices can be connected in series or on a common bus.

According to another embodiment of the present invention, a controller for a system having a plurality of memory devices for storing data is provided, the controller being in a serial interconnect configuration for communication with the plurality of memory devices. The controller may include a first connection unit for receiving a request to access the plurality of memory devices; A translator for translating the request into a plurality of separable commands that can be interpreted by the plurality of memory devices, each command being an address identifier for one of the plurality of memory devices and one of the plurality of memory devices; A translator having a modular structure including a command identifier representing an operation to be executed by one memory device; And a second connection for communicating with one of the plurality of memory devices for issuing the plurality of separable commands.

According to another embodiment of the invention, determining an address including a memory device address; Identifying a plurality of operations to execute a request to access a memory; And providing a plurality of separable commands for the memory, each command including a device identifier having a memory device address and a command identifier having one of the plurality of operations. Is provided.

Advantageously, the method is used to translate a request to access a memory device into a plurality of separable commands that can be interpreted by the memory device. The method can be used to translate a request to access a memory device into a plurality of separable commands that can be interpreted by the memory device.

Other aspects and features of the present invention will become apparent to those skilled in the art upon examination of the following detailed description of specific embodiments of the present invention in conjunction with the accompanying drawings.

Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings.

1 illustrates a system and host system having a memory system and a memory controller to which embodiments of the present invention may be applied.

FIG. 2 is a block diagram illustrating a memory system including a controller and a plurality of memory devices connected to the memory system through a common bus to which embodiments of the present invention may be applied.

3 is a block diagram illustrating a memory system having a controller coupled to a memory device and a plurality of serially interconnected memory devices to which embodiments of the present invention may be applied.

4 is a block diagram illustrating an example of a general configuration of a flash memory device to which embodiments of the present invention may be applied.

5A, 5B and 5C illustrate examples of modular command structures for use with NAND flash memory, to which embodiments of the present invention may be applied.

6A is a block diagram illustrating a configuration of a flash controller to which embodiments of the present invention can be applied.

FIG. 6B is a block diagram illustrating the functional components of the flash command engine shown in FIG. 6A.

FIG. 7 is a flowchart illustrating a process performed by a page read command from a controller, using a modular command structure.

8 illustrates the timing of a page read operation with a set wait period from flash memory using a modular command structure.

9 illustrates the timing of a page read operation from a flash memory device with a status request, using a modular command structure.

10 is a flowchart illustrating a process performed by a page program command from a controller, using a modular command structure.

11 illustrates the timing of a page program operation from a flash memory device with a single data input, using a modular command structure.

12 illustrates the timing of a page program operation from a flash memory device with two data inputs using a modular command structure.

13 is a flowchart illustrating a process performed by a block erase command from a controller using a modular command structure.

Figure 14 illustrates the timing of a block erase operation with a single block address for erasing from a flash memory device using a modular command structure.

Figure 15 illustrates the timing of a block erase operation with two block addresses to delete from a flash memory device using a modular command structure.

16 is a flowchart illustrating a process performed by a simultaneous page read command from a controller for two memory banks of the same flash memory device using a modular command structure.

FIG. 17 illustrates the timing from flash memory of a concurrent page read operation for two memory banks of the same flash memory device using a modular command structure.

18 is a flowchart illustrating a process performed by concurrent page program commands from a controller for two memory banks of the same flash memory device using a modular command structure.

19 illustrates the timing from flash memory of a concurrent page program operation for two memory banks of the same flash memory device using a modular command structure.

20 is a flowchart illustrating a process performed by a concurrent block erase command from a controller for two memory banks of the same flash memory device using a modular command structure.

Figure 21 illustrates the timing from flash memory of a concurrent block erase operation for two memory banks of the same flash memory device using a modular command structure.

FIG. 22 is a flowchart illustrating a process performed by interleaved page reads and page program commands from a controller for two memory banks of the same flash memory device using a modular command structure.

FIG. 23 illustrates the timing from flash memory of interleaved page read and page program operations for two memory banks of the same flash memory device using a modular command structure.

FIG. 24 is a flowchart illustrating a process performed by a paused and resumed page read and page program commands from a controller for two memory banks of the same flash memory device using a modular command structure.

FIG. 25 illustrates timing from flash memory of paused and resumed page read and page program operations for two memory banks of the same flash memory device using a modular command structure.

FIG. 26 illustrates an example of interleaved and concurrent page read, block delete, page program and page-pair erase commands / operations for multiple flash memory devices, each having multiple memory banks.

27 illustrates an example of interleaved and concurrent page read commands / operations for multiple flash memory devices, each having multiple memory banks.

FIG. 28 illustrates an example of interleaved and simultaneously suspended and resumed page reads, block erases, page programs and commands / operations for multiple flash memory devices, each having multiple memory banks.

In the following detailed description of the example embodiments, reference is made to the accompanying drawings which form a part hereof and in which particular example embodiments are illustrated. These embodiments have been described in sufficient detail to enable those skilled in the art to practice the invention, and it is understood that logical, structural, electrical and other modifications can be made and other embodiments may be used without departing from the scope of the invention. . The following detailed description, therefore, is not to be taken in a limiting sense.

Semiconductor memory devices are often interconnected to form a large memory system. 1 illustrates a system to which embodiments of the present invention may be applied. Referring to FIG. 1, a host system 102 having a processor 103 therein is connected to a system including a memory system 106 and a controller 104 for controlling the memory system. The memory system 106 includes at least one memory device (eg, two flash memory devices 107-0, 107-1.) The controller 104 receives a request from the host system 102 to store the request. Translate into commands that can be interpreted by the system 106. The controller 104 also translates logical addresses for the memory system 106 used by the host system 102 into physical addresses of the memory system 106. The controller 104 ensures that data to be stored in the memory system 106 is distributed among the memory devices 107-0 and 107-1.Error correction code to check for errors in the execution of the command. (error correcting code; “ECC”) is also generated by the controller 104.

2 shows an example of a system configuration to which embodiments of the present invention can be applied. Referring to FIG. 2, the controller 112 communicates with a memory system including a plurality of memory devices (eg, four flash memory devices 108-0 through 108-3) over a common bus 114. . The controller 112 uses a common bus 114 to transfer data into and out of the memory devices 108-0 through 108-3. Only the designated flash memory device is asserted simultaneously in this configuration by asserting a chip enable signal.

3 shows another example of a system configuration to which embodiments of the present invention can be applied. The memory system includes memory devices connected in series. Referring to FIG. 3, a memory system including a controller 116 and a plurality of memory devices (eg, four flash memory devices 109-0 to 109-3) are interconnected in a loop structure. Since devices 109-0 through 109-3 are interconnected in series, only one device receives data and messages that are introduced into the memory system through controller 116. Each memory device 109-0 through 109 -3) is connected to at most two different memory devices (ie, front and back devices) As described above, data and messages introduced into the memory system pass through all other memory devices and end up in a serial connection. Reach the device 109-3.

The flash memory device may be any type of flash memory, for example NAND-, NOR-, AND-type flash memory. Also, the memory device may be a random access memory.

NAND flash memory devices are generally interconnected to provide low cost, high density memory. 4 illustrates the functional components of a NAND flash device 400. In NAND flash device 400, commands, addresses, and data are multiplexed through common I / O pins in the chip of the device. NAND flash device 400 has a memory bank 402 which is a cell array structure having a plurality (n) of erasable blocks. Each erasable block is divided into a plurality (m) of programmable pages. Each page consists of (j + K) bytes. The pages are further divided into j-byte data storage areas where separate k-bytes and data are typically used for error management functions. Each page typically contains 2,112 bytes, of which 2,048 bytes are used for data storage and 64 bytes are used for error management. The memory bank 402 is accessed by pages. Although FIG. 4 shows a single memory bank 402, the NAND flash device 400 may have one or more memory banks 402. Each of the memory banks 402 may execute simultaneous page read, page program, page erase and block erase operations.

Commands for accessing the memory bank 402 are received by the command register 414 and the control logic section 416 from a controller (eg, the controller 116 shown in FIG. 3). The received command is entered into the command register 414 and remains there until execution. The control logic section 416 converts the command into a form that can be executed on the memory bank 402. Commands generally enter NAND flash device 400 through the assertion of different pins, which can be used to represent different commands on the chip's external packaging. For example, the command may include chip enable, read enable, write enable, and write protection. While the delete command is executed based on the block, the read and write commands are executed based on the page.

When the command is received by the command register 414 and the control logic section 416, the address for the page of the memory bank 402 to which the command belongs is received by the output driver 412. The address is provided to the address buffer and latch 418, and then controlled and predecoder 406, detection amplifier (S / A) and data register (to access the page indicated by the address). 404 and a row decoder 408. The data register 404 is then provided to an I / O (in / out) buffer and latch 410 and then to an output driver 414 for output from the NAND flash device 400. Receive a complete page.

For example, a read command is received by command register 414 and control logic 416 and the accompanying address is received by address buffer and latch 418. The address buffer and latch 418 determine the page on which the address is located and provides the row decoder 408 with the row address (s) corresponding to the page. The corresponding row is activated. The data register and S / A 404 detect the page and transfer the data from the page into the data register 404. Once the data from the entire page has been transferred to the data register, the data is read sequentially from the device via the I / O buffer and latch 410 and output driver 412.

Program commands are also processed based on the page. The program command is received by the command register 414 and the control logic section 416, the accompanying address is received by the address buffer 418, and the input data is received by the output driver 412. Input data is transferred to data register 404 via I / O buffer and latch 410. Once all input data is in the data register 404, the page in which the input data is to be stored is programmed with the input data.

The delete command is processed based on the block. The delete command is received by the command register 414 and the control logic section 416, and the block address is received by the address buffer 418.

A typical NAND flash memory command uses two cycles of commands to complete loading of the command. Table 1 shows a command set of example NAND flash memories.

function 1st cycle 2nd cycle read 00h 30h Read for Copy Back 00h 35h ID read 90h - reset FFh - Page programs 80h 10h Cache program 80h 15h Copyback program 85h 10h Delete block 60h D0h Random data input 85h - Random data output 05h E0h Read status 70h

Table 1: Command Sets for NAND Flash

Many commands issued to NAND flash memory in two command cycles are considered as one procedure and as being unable to be discarded, interrupted, stopped or resumed. If the NAND flash memory receives these two command cycles, it cannot accept any additional commands other than reset and read status commands. In a flash memory device having multiple memory banks, this command structure limits the use of banks because one bank remains inactive while another bank processes the command. If a command with a long internal key operation is being executed, it results in low input / output usage (eg, 20 ms page read, 200 ms page program, and 1.5 ms block erase). In a system with multiple flash memories interconnected in series, this command structure speeds up the entire system because the flash memory device that is processing the command does not pass other commands to the next flash memory until the processing is completed. Can be reduced.

An example of a command structure that can be applied to a system according to an embodiment of the present invention includes a command field with byte (s). For example, the command field has a first byte for the device and a bank address and a second byte for the operation code.

5A shows an example of a modular command structure for use with a NAND flash memory. In this particular example, the modular command structure is byte based. Referring to FIG. 5A, the modular command structure 500 includes first and second bytes 502, 508 (byte 1 and byte 2), each having a plurality of bits. In this particular example, the first and second bytes 502, 508 of the command structure include an 8-bit address and an 8-bit operation code, respectively. The first byte 502 has a six-bit address 504 for the memory device of the destination. The six-bit address 504 is used by the system to distinguish between memory devices that include a plurality of memory devices. The first byte 502 also includes a 2-bit address 506 for the memory bank of the memory device for use with the memory device having a plurality of memory banks. The second byte 508 of the command structure includes an 8-bit operation code 510 that indicates the command to be executed by the memory device. Table 2 illustrates an example of operation codes.

2nd byte (OP7-OP0) Command Address input 0 0 0 0 0 0 0 0 Page read (00h) low 0 0 0 0 0 0 One One Burst data read (03h) column 0 0 0 0 0 One 0 One Read copy page (05h) low 0 0 0 0 One 0 0 One Start Burst Data Load (09h) column 0 0 0 0 One 0 One 0 Burst Data Load (0Ah) column 0 0 0 0 One One One One Page program (0Fh) low 0 0 0 One 0 0 One 0 Address input for block deletion (12h) low 0 0 0 One 0 One One One Delete block (17h) none 0 0 0 One 0 One 0 0 Address input for page-pair deletion (14h) low 0 0 0 One One One One 0 Delete page-pair (1Eh) none 0 0 One One 0 0 One One Read device status (33h) none 0 0 One One 0 One 0 One Read device ID (35h) none 0 0 One One One 0 0 One Write device address (39h) none 0 0 One One One 0 One 0 Write Configuration Register (3Ah) none 0 0 One One One One One One Reset (3Fh) none

Table 2: Example of Action Codes for the 2nd Byte

The command structure has many variations. Another example of a two-byte command structure is that the first byte has an 8-bit device address (DA) and the second byte has a 4-bit OP code and a 4-bit bank address (BA).

5B shows another example of a modular command structure for use with a NAND flash memory. Referring to FIG. 5B, the command structure 520 includes a plurality of bytes. In the illustrated example, the command structure 520 has a 3-byte row address 522 (bytes 3 to 5) in addition to the 2-byte modular command structures (bytes 1 and 2). The structure of a part of the 2-byte modular command in FIG. 5B coincides with the 2-byte modular command structure shown in FIG. 5A. The first byte 502 has a six-bit address 504 for the destination memory device and a two-bit address 506 for the memory bank. The second byte 508 has an 8-bit operation code 510. 3-byte row address 522 provides a 24-bit address 524 for the row (s) in the indicated memory bank at first byte 502. The 24-bit (ie 3-byte) row address 524 is used for commands where a row address is required to specify the row position where the command is to be executed.

5C shows another example of a modular command structure for use with a NAND flash memory. Referring to FIG. 5C, the command structure 540 includes a plurality of bytes. In the illustrated example, command structure 540 has a two-byte modular command structure (bytes 1 and 2) as well as a two-byte column address 542 (bytes 3-4). Some of the structures of the 2-byte modular command in FIG. 5C include a first byte 502 having a 6-bit address 504 for the destination memory device and a 2-bit address 506 for the memory bank. This corresponds to the two-byte modular command in FIG. 5B. The second byte 508 has an 8-bit operation code 510. The 2-byte address 542 provides the 16-bit address 544 for the column (s) in the indicated memory bank at the first byte 502. A 16-bit (ie 2-byte) column address 544 is used for commands where a column address is required to specify the column location where the command is to be executed.

The command structures 500, 520, and 540 depend on the commands sent to the memory device. As indicated in Table 2, some commands require additional addresses (i.e. row or column addresses) to be supplied with the command. Thus, command structures 500, 520, and 540 depend on the operation code in second byte 508.

1 and 5A-5C, the controller 104 translates a request from the host system 102 into one of the command structures 500, 520, and 540 that can then be interpreted by the flash memory device. . Based on the operation code 510, the controller 104 determines whether a row address, column address, or no address is supplied to the memory device. The controller 104 forms the commands used by the memory devices 107-0 and 107-1 to perform operations.

Each command structure 500, 520, 540 includes both a memory device address 504 and a bank address 506. Thus, the processing of the command can be discarded and stopped by different memory devices. In addition, since the first byte 502 contains all addressing information, each memory device can determine whether the indicated command at the second byte 508 is directed to them or passed to the next memory device. Can be evaluated quickly.

Although modular command structures 500, 520, 540 can be used in NAND flash memory devices, the following examples are used in modular command structures 500, 520, 540, using, for example, HLNAND ™ (HyperLink NAND) flash devices. Describes the processing of various commands. HLNAND ™ flash devices are described in detail in US Provisional Application No. 60 / 839,329, filed Aug. 22, 2006.

For HLNAND ™ flash devices, an exemplary input order of modular command structures 500, 520, 540 according to specific commands in the operation code is shown in Table 3. All commands, addresses, and data are shifted into and out of the device, starting with the most significant bit (“MSB”). In HLNAND ™ flash devices, the serial data input (SDn) is sampled at the positive or negative clock edge while the serial data input enable (SDE) is “high”. In the specific example shown in Table 3, each command is represented by a one-byte target address expressed by “TDA” (first byte) and represented by the command structures 500, 520, and 540 shown in Figs. 5A to 5C. Contains a one-byte action code (second byte). Once the SCE advances to a logic "high", the one-byte address is shifted followed by the one-byte operation code. The exception is that the write device address to which the first byte is input is a page read command. Depending on the command, the three-byte row address is represented as "R" in Table 3 or the two-byte column address is represented as "C" in Table 3, or either (third to fifth bytes). If data is provided to a flash device, the data is (appropriately) entered into the device after any row or column address and represented by “D” in Table 3.

Command Input byte number 1 ^st 2 ^nd 3 ^rd 4 ^th 5 ^th 6 ^th 7 ^th … 2115 ^th 2116 ^th Read page TDA 00h R R R - - - - - Read burst data TDA 03h C C - - - - - - Read copy page TDA 05h R R R - - - - - Start to load burst data TDA 09h C C D D D … D D Burst Data Load TDA 0Ah C C D D D … D D Page programs TDA 0Fh R R R - - - - - Address input for block deletion TDA 12h R R R - - - - - Delete block TDA 17h - - - - - - - - Input address for page-pair deletion TDA 14h R R R - - - - - Delete page-pair TDA 1Eh - - - - - - - - Read device status TDA 33h - - - - - - - - Read device ID TDA 35h - - - - - - - - Write device address 00h 39h - - - - - - - - Write configuration register TDA 3Ah D - - - - - - - reset TDA 3Fh - - - - - - - -

Table 3: Modular Command Input Order

An example of operation of an HLNAND ™ flash device using modular command structures 500, 520, 540 for various operations is described below. The following example includes a timing diagram illustrating processing memory devices (eg, the memory devices shown in FIGS. 1-3). The signals in the timing diagram are shown, for example, for an HLNAND ™ flash device. The chip enable (CE #) signal indicates that the memory device is enabled when this signal is " low. &Quot; Serial data input (SDn) signals represent commands, addresses, and input data. The serial data output (SQn) signal represents the transfer of output data during a read operation. The serial data input enable (SDE) signal controls the data input such that when this signal is "high", the command address and input data SDn are latched into the device. The serial data output enable signal SDE enables the output SQn when this signal is “high”.

When device addresses are assigned to all of the serially connected devices (eg, the configuration shown in FIG. 3) at the start of system operation, the first byte of the command does not require a write device address. Assignment of sequential device addresses is disclosed in U.S. Provisional Application No. 60 / 787,710, filed Mar. 28, 2006, and U.S. Provisional Application No. 60 / 802,645, filed March 23, 2006.

6A shows an example of a flash controller to which embodiments of the present invention can be applied. The flash controller corresponds to the controllers 104, 112, 116 shown in FIGS. 1, 2, and 3.

Referring to FIG. 6A, the flash controller 310 includes a central processing unit (CPU) 312; Memory 314 has random access memory (RAM) 316 and read-only memory (ROM) 318. The flash controller 310 also includes a flash command engine 322, an error correction code (ECC) manager 324, and a flash interface 326. In addition, the flash controller 310 includes a host interface controller 332 and a host interface 334. CPU 312, memory 314, flash command engine 322, and host interface controller 332 are connected via a common bus 330. The host interface 334 may be externally connected via a bus, a connection link, or an interface (eg, Advanced Technology Attachment (ATA), Parallel ATA (PATA), Serial ATA (SATA), or Universal Serial Bus (USB)). For connection to the device. The host interface 334 is controlled by the host interface controller 332. The CPU 312 operates with instructions stored in the ROM 318 and processed data stored in the RAM 316. The flash command engine 322 interprets the commands and the flash controller 310 controls the operation of the flash device via the flash device interface 326. ECC manager 324 generates ECC, and ECC verification is performed. In case of an error, an error message is generated. The flash controller 310 may be configured as a system on chip, a system in package, or multiple chips.

6B shows an example of the functional components of the flash command engine 322 of FIG. 6A when issuing a command to the flash device. 1, 6A and 6B, the flash command engine 322 interprets a request from the host system 102 into a plurality of separable commands that can be interpreted by the flash memory device. Thus, the flash controller 310 translates the request to access the flash memory device into at least one command using the modular command structure shown in FIGS. 5A-5C. Flash controller 310 includes a connection with bus 330 connected to host interface controller 332. The connection enables communication with the host system 102 to receive a request from the processor 103 of the host system 102 to access the flash memory device. The flash controller 310 also includes a flash device interface 326 in communication with the flash memory device. The flash device interface 326 functions as another connection for issuing commands to the flash memory device of the memory system.

The flash memory engine 322 includes a command structure mechanism 558, a bank interleaving mechanism 560, a device interleaving mechanism 562, an address identification mechanism 564, a command identification mechanism 566, a row address identification mechanism 568. , And column address identification mechanism 570. The command structure mechanism 558 processes the modular command structure (eg, the modular command structure shown in FIGS. 5A-5C) to be used by the memory device. The address identification mechanism 564 and the command identification mechanism 566 analyze the request from the host system 102 and extract the memory device and / or bank address and command therefrom, respectively. The command identification mechanism 566 determines whether multiple commands will be used to fulfill the request. Each command is detachable and jointly executes a request from the host system 102. The command identification mechanism 566 collects information to format the command, including the address from the address identification mechanism 564. If either of the commands making a request relates to a row or a column address, the command identification mechanism 566 obtains the cooperation of the use of the row address identification mechanism 568 or the column address identification mechanism 570, respectively, to form part of the command. Acquire a row or column address.

Bank interleave mechanism 560 and device interleave mechanism 562 instruct multiple commands to be sent to multiple memory banks or memory devices, respectively, via device interface 326. The modular command structure is configured such that a flash memory device having multiple memory banks can process each memory bank simultaneously. Similarly, the modular command structure is configured such that serially connected memory devices can be processed simultaneously. The bank interleave mechanism 560 interleaves commands for different memory banks in the same memory device (see FIGS. 16-21 for examples of simultaneous operation of multiple memory banks). Device interleave mechanism 562 interleaves commands for different memory devices in the same memory system (see FIGS. 22-28).

The ECC manager 324 generates an error correction code (ECC) to verify that the particular command was executed successfully and completely.

6B illustrates the functional components of flash command engine 322 and may be realized as a number of configurations that will be appreciated by those skilled in the art.

The modular command may include a page read command. In the command structure, the first cycle of page read command is input followed by the column address for the start column address in the target page address and the row address for the target page address. The page read command of the second cycle is input and thereafter the device is busy for a period of time (eg, 20 ms) to complete the internal page read operation. After the waiting period, a burst data read operation is performed to retrieve data from the device's buffer. This operation starts until the burst data reading ends from that time, and the device cannot execute any other operations.

7 shows the flow of the page read command. The controller for the system, in step 602, generates a page read command that includes a flash device address of the destination, a memory bank address, a page read operation code, and a 3-byte row address for the row (s) defining the page to be read. do. The page read command passes through the flash devices that make up the system until the flash device address of the destination matches the flash device that receives the page read command. The page read command containing the row address (es) is received by the flash device of the destination. The page read command is then provided to the command register of the destination flash, where an address latch cycle begins to input a 3-byte row address. Once the address latch cycle ends, a page read operation is initiated within the flash device and data on the selected page is detected and transferred to the data register in less than time t _R (transfer time from the memory bank to the data register, e.g. 20ms). do.

The controller waits for t _R to collect data from the page, or the controller generates and sends a device status question to the flash device to receive a notification when the page is accessed. If the controller generates a device status command, the command is sent to the flash device at step 604. The flash device will respond to this request with a continuous busy indication until the page is accessed, and when the page is accessed, the flash device indicates that the memory bank is ready and no longer busy. The controller continues to check at step 606 to determine if the memory bank is ready.

Once the memory bank is ready or the controller waits for t _R , a burst data read command with device address and column address is issued in step 608. If the controller does not send a device status query and instead waits for t _R , steps 604 and 606 are not executed. Once the device receives the burst data read, the SQE signal is enabled, and the page data in the data register is read at step 610, starting from the column address given with the command. This read continues through SQn until SQE goes low.

The error correction code (ECC) is generated by the controller in step 612 and verified in step 614. If the ECC is not verified, an error message is issued at step 616. If the ECC is verified, the page read operation is successful and the operation is completed at step 618. For example, the flash device controller generates an ECC parity bit for 2048 bytes of input data per page. Thus, 2048 byte data with ECC parity bits are programmed (generally 1-byte ECC per 512 bytes, 4 bytes ECC total per 2048 bytes) in the page. The ECC parity bits are programmed into a 64 byte spare field in the page. During the page read, the flash device controller reads 2048 byte data with ECC parity information. The flash device controller verifies 2048 data with 4-byte ECC information. Thus, ECC processing is executed by the flash device controller and the flash memory device stores only ECC parity information.

8 illustrates a timing diagram for a page read operation in terms of a flash device, in which the controller waits for the expiration of t _R to obtain the requested data. If a burst data read command is notified and SQE is enabled during the bank busy period t _R , all output data will be invalidated.

9 illustrates a timing diagram for a page read operation by device state from a controller in terms of a flash device.

The modular command may include a page program command. In the command structure, a first cycle page program command is input followed by a column address for the start column address in the target page address and a row address for the target page address. The input data is loaded followed by the second program's fat program command. The device busy during the period after the second cycle (eg, 200 ms) during the completion of the internal page program operation. These steps are all considered as one procedure that cannot be interrupted once the page program operation is complete.

10 illustrates the flow of a page program command from a flash device controller. The controller for the system, in step 902, generates a burst data load start command that includes a flash device address of the destination, a memory bank address, a burst data load start code, and a 2-byte column address for the column (s) to be programmed. do. The burst data load start command passes through the flash devices that make up the system until the flash device address of the destination matches the flash device that receives the burst data load start command. The burst data load start command is provided to the command register of the destination flash device along with the two-byte column address in step 904 and then with the input data in step 906. The burst data load start command resets all data registers in the flash device of the destination. If the burst data load start operation does not enter all the data into the flash device, the next burst data load command can be used to locate all the data in the device.

The flash device controller, at step 908, issues a page program command that again specifies the row address (s) specifying the page program operation code and the row to be written in the page program operation, along with the device address and memory bank address of the destination. Create The page program command is generated by the controller after the time t _{DDE at} which data is loaded into the flash device from the burst data load start command. This will program the loaded data into the selected page location.

The controller monitors the state of the page program operation using the device status command generated at step 910. The flash device will respond to this request with a continuous busy indication until the page is accessed, and when the page is accessed, the flash device indicates that the memory bank is ready and no longer busy. The controller continues to check at step 912 to determine whether the memory bank is ready. Once the memory bank is ready, the controller checks to see if the page program operation is successful. If not, an error message is issued at step 916, otherwise the page program operation is completed at step 918.

FIG. 11 illustrates a timing diagram for page program operation in terms of a flash device, where the start of burst data loading is sufficient to load all data into the device. 12 illustrates a timing diagram for a page program operation in which a burst data load operation is required after a burst data load start operation to load all data into the device.

The modular command may include a block delete command. In the command structure, a block erase command of the first cycle is input followed by a row address for the target block address. After the device has been busy for 1.5 ms to complete the internal block erase operation, a second cycle of block erase command is input.

13 is a flow of block erase operation from a controller. The flash device controller for the system generates an address input for the block erase command in step 1202, including the device address, memory bank address, operation code, and 3-byte row address in step 1204. If, at step 1206, one or more blocks are deleted at the same time, an additional address input for the block delete command is generated by the controller to specify these additional blocks. If all blocks are specified, then at step 1208 the controller generates a block delete command to start the flash device to execute the block delete operation for the selected block. The block erase command generated by the controller includes a device address, a memory bank address, and an operation code.

The controller issues, at step 1210, a status command used to determine when the memory bank is available and the block erase operation is complete. The controller continues to check the device state at step 1212 until the memory bank is available. When the block erase operation is complete, the controller checks in step 1214 to verify that the operation was successful. If the operation was not successful, an error is issued at step 1216, otherwise the block erase operation is completed at step 1218.

14 illustrates a timing diagram for a block erase operation in terms of a flash device where only a single block is deleted. 15 illustrates a timing diagram for a block erase operation in which multiple blocks are deleted.

The modular command structure illustrated in FIGS. 5A-5C provides the memory bank address to be provided in the first byte along with the device address. This is used to specify the memory bank to which the command is directed when the flash memory device has more than one memory bank. Since a command with a modular command structure designates a memory bank address in the command, a flash device having a configuration in which each memory bank operates independently may be able to simultaneously execute operations on one or more memory banks in the flash device. The HLNAND ™ flash device is an example of one such flash memory.

The pin configuration of multiple HLNAND ™ flash devices cascaded at the top level can match one of the single devices. In a serial interconnect configuration, each device introduces additional half clock cycle latency, for example on a cascaded path. As noted above, multiple cascaded devices determine the total clock latency of the operation of the serial interconnect configuration. In a multiple devices configuration with multiple memory banks interconnected, the controller can effectively schedule many different procedures that consume time to access key operations by interleaving the commands.

16-21 illustrate simultaneous operations executed on two memory banks within a single flash memory device.

16 illustrates a flow for a simultaneous page read operation from two memory banks within the same flash memory device. The page read command is given to memory bank 0 in step 1502. Memory bank 0 then proceeds to process the request by accessing the requested page. While memory bank 0 processes the page read command, a second page read command is given to memory bank 1 in step 1504. Memory bank 1 then proceeds to process the request by accessing the requested page, while memory bank 0 simultaneously processes its own request. In order to access the data resulting from the page read command issued in step 1502, the time t _R1 after the page read request is granted to memory bank 0 in step 1506, the burst data read command is entered in step 1508. It is allowed to elapse before being assigned to memory bank 0. In order to access the data resulting from the page read command issued in step 1504, the time t _R2 after the page read request is granted to memory bank 1 in step 1510 is the burst data read command in step 1512. It is allowed to elapse before being assigned to memory bank 1.

FIG. 17 illustrates the timing of the simultaneous page read operation illustrated in FIG. 16.

18 illustrates a flow for simultaneous page program operation in two memory banks of the same flash memory device. In step 1702, a burst data load start command is given to memory bank 0 along with the data to be programmed into memory bank 0. In step 1704, a burst data load start command is given to memory bank 1 along with the data to be programmed into memory bank 1. In step 1706 a page program command is given to memory bank 0 and in step 1708 a page program command is given to memory bank 1. A read status command is given to memory bank 0 in step 1710 and to memory bank 1 in step 1712 to monitor the progress of each memory bank when completing the page program operation. If the status returns a pass for each memory bank, the page program operation is complete and other operations can be executed by the memory bank.

18 shows a burst data load start command given to each memory bank before the page program command provided to each bank. The burst data load start and page program commands can both be given to memory bank 0 before any of the commands are given to memory bank 1. 19 illustrates the timing of a concurrent page program operation in which a burst data load start and page program command is given to memory bank 0 before any one of the commands is given to memory bank 1.

20 illustrates a flow for a simultaneous block erase operation of two memory banks of the same flash memory device. In step 1902, an address input for the block erase command is given to memory bank 0 along with the address of the block to be deleted. In step 1904, an address input for a block erase command is given to memory bank 1 along with the address of the block to be deleted. Upon receiving that the block indicated in the address input for the block delete command received at step 1902 has been deleted, at step 1906 a block delete command is provided to memory bank 0. Upon receiving that the block indicated in the address input for the block delete command received at step 1904 has been deleted, at step 1908, a block delete command is provided to memory bank 1. A read status command is given to memory bank 0 in step 1910 and also to memory bank 1 in step 1912 to monitor the progress of the block erase operation. If the status returns a pass for each memory bank, the block erase operation is completed and other operations can be executed by the memory bank.

20 shows an address input for a block erase command given to each memory bank before a block erase command provided to each bank. Both the block erase and block erase commands may be given to memory bank 0 before any one of the commands is given to memory bank 1. 21 illustrates the timing of a concurrent block erase operation in which block erase and block erase commands are given to memory bank 0 before any one of the commands is given to memory bank 1.

Operations executed simultaneously by the memory banks are not necessarily the same operation. 22-25 illustrate different operations executed simultaneously by two memory banks of the same flash memory device.

22 illustrates a flow for simultaneous page read and page program operations in two memory banks of the same flash memory device. A page read command is given to memory bank 0 in step 2102. While memory bank 0 accesses the page indicated in the page read command, in step 2104, a burst data load start command is given to memory bank 1 along with the data to be programmed into memory bank 1. In step 2106, a page program command is given to memory bank 1 to begin programming of data into memory bank 1. After a page read command is given in step 2102 to allow memory bank 0 to retrieve the requested data, a burst data read command in step 2110 is issued to memory bank 0 to access the data retrieved from the page read operation. Before being granted, time t _R is allowed to elapse in step 2108. In step 2112 a read status command is given to memory bank 1 to monitor the progress of the page program operation. If the status returns a pass for memory bank 1, the page program operation is complete and other operations can be executed by memory bank 1.

FIG. 23 illustrates the timing of simultaneous page read and page program operations from FIG. 22.

FIG. 24 illustrates a flow for a suspend and resume operation executed in two memory banks of the same flat memory device, in which a page read operation is executed in memory bank 0 and a page program operation is executed in memory bank 1. FIG. In step 2302, a burst data load start is given to memory bank 1 along with the data programmed into memory bank 1. This operation is stopped when a page read command is given to memory bank 0 in step 2306 before all data in the burst data load start operation is loaded into memory bank 1. After the page read command has been completely received by memory bank 0 and while memory bank 0 is accessing the requested page, the operation on memory bank 1 may be terminated at step 2308 using a burst data load operation with the remaining data. Resumed. Once the data is provided to memory bank 1, a page program command is given to memory bank 1 at step 2310 to begin programming of the data therein. The time t _R is allowed to elapse in step 2312 after the page read command is granted to memory bank 1 in step 2306. Once t _R has elapsed, a burst data read command is given to memory bank 0 in step 2314 to begin extraction of the requested data from memory bank 0. When a read state command is given to memory bank 1 in step 2318 to monitor the state of the memory bank, in step 2316 the burst data read command is stopped. Once the read status command is received, the burst data read command is resumed at step 2320. When the page program operation is complete, memory bank 1 returns a pass for the read status command and another operation may be executed by memory bank 1.

FIG. 25 illustrates paused and resumed page read and page program operations from FIG. 24.

26-28 illustrate interleaving of operations between multiple devices. 25 shows a page read operation in both flash device 0 and memory bank 0 and memory bank 1 of flash device 1, a block erase operation in memory bank 0 of flash device 2, and flash in memory bank 1 of flash device 2; A page program operation in memory bank 0 of device 3 and a pair-pair erase operation in memory bank 1 of flash device 3 are shown. 26 shows page read operations in memory banks 0 and 1 of flash devices 0, 1, 2, and 3. FIG. 28 shows a page program operation in memory bank 0 of flash device 0 followed by a page read operation, and a block erase operation in memory bank 1 of flash device 0 following the page read operation, flash device 1 and Block erase operation in memory bank 0 of 3 and in memory bank 1 of flash devices 2 and 3, page program operation in memory bank 1 of flash device 1, and following the page read operation followed by memory of flash device 2 The page program operation in bank 0 is shown.

In the above embodiments, the memory device has been described as a flash memory device. It will be apparent to those skilled in the art that the memory device may be a random access memory device: for example, dynamic random access memory (DRAM), static random access memory (SRAM), magnetoresistive random access memory (MRAM). Also, the plurality of memory devices included in the memory system may be devices having the same device type or mixed device types. The construction of a serially connected multiple devices of mixed type is disclosed in US Provisional Application No. 60 / 868,773 filed December 6, 2006.

In the above embodiments, device elements and circuits are connected to each other as shown in the figures for the purpose of simplicity. In practical applications, these devices, device circuits, and the like may be directly connected to each other or indirectly through other devices, devices, circuits, and the like. Thus, in an actual configuration, elements, circuits, and devices are connected directly or indirectly to each other.

The above embodiments of the present invention are intended for illustration only. Modifications, variations, and changes may be made to the specific embodiments by those skilled in the art without departing from the scope of the invention, which is defined solely by the claims appended hereto.

Claims (35)

A command structure comprising a plurality of separable commands representing a request to access one of the plurality of memory devices, the command structure comprising: Each of the plurality of separation commands, A device identifier comprising an address for one of the plurality of memory devices and a bank address for one of the plurality of memory banks in one of the plurality of memory devices; And And a command identifier comprising an operation code representing an operation to be executed by one of the plurality of memory devices. The memory device of claim 1, wherein the one memory device includes at least one memory bank, and an address identifier is a device address of one of the at least one memory devices and a memory bank of the at least one memory bank. A command structure comprising a bank address for. The command structure of claim 2, wherein the address identifier comprises an m-byte identifier and m is an integer. 4. The command structure of claim 3, wherein the device address comprises an n-bit address, the bank address comprises a p-bit address, and each of n and p is an integer. The command structure of claim 1, wherein the command identifier comprises a q-byte command identifier and q is an integer. The command structure of claim 1, wherein the modular structure further comprises a row address specifying a row in a memory bank of the at least one memory device to which the operation of the command identifier is to be applied. The command structure of claim 1, wherein the modular structure further comprises a row address specifying a row in a memory bank of the at least one memory device to which the operation of the command identifier is to be applied when the operation is of a determined type. 7. The command structure of claim 6, wherein the row address comprises an r-byte address and r is an integer. The command structure of claim 1, wherein the modular structure further comprises a column address specifying a column in a memory bank of the at least one memory device to which the operation of the command identifier is to be applied. The command structure of claim 1, wherein the modular structure further comprises a column address specifying a column in a memory bank of the at least one memory device to which the operation of the command identifier is to be applied when the operation is of a determined type. The command structure of claim 9, wherein the column address comprises an s-byte address and s is an integer. 12. The memory device of claim 11, wherein the one memory device comprises at least one memory bank, wherein an address identifier is a device address for one of the at least one memory devices and a memory bank of the at least one memory bank. A modular command structure containing a bank address for. The modular command structure of claim 12, wherein the command identifier comprises a q-byte identifier and q is an integer. The modular command structure of claim 12, wherein the modular structure further comprises a row address specifying a row in a memory bank of the at least one memory device to which the operation of the command identifier is to be applied. The modular command structure of claim 12, wherein the modular structure further comprises a row address specifying a row in a memory bank of the at least one memory device to which the operation of the command identifier is to be applied when the operation is of a determined type. . The modular command structure of claim 15, wherein the row address comprises an r-byte address and r is an integer. The modular command structure of claim 12, wherein the modular structure further comprises a column address specifying a column in a memory bank of the at least one memory device to which the operation of the command identifier is to be applied. The modular command structure of claim 12, wherein the modular structure further includes a column address specifying a column in a memory bank of the at least one memory device to which the operation of the command identifier is to be applied when the operation is of a determined type. . The method according to claim 4, The m-byte identifier comprises a one-byte identifier; The n-bit address comprises a 6-bit address; And the p-bit address comprises a 2-bit address. The command structure of claim 8, wherein the r-byte row address comprises a 3-byte address. 6. The command structure of claim 5, wherein the q-byte command identifier comprises a 1-byte operation code. A device identifier comprising an address for one of the plurality of memory devices and a bank address for one of the plurality of memory banks in one of the plurality of memory devices; And And a command identifier comprising an operation code representing an operation to be executed by one of the plurality of memory devices. A memory system including at least one memory device for storing data; A processor for managing a request to access the memory system; And A controller for translating a request from the processor into one or more separable commands that can be interpreted by the at least one memory device, each command being an address identifier for one of the at least one memory device. A controller having a modular structure that includes a command identifier representing an operation to be executed by one of the at least one memory device; And the at least one memory device and the controller are serially connected for communication. 24. The apparatus of claim 23, wherein the at least one memory device comprises at least one memory bank, and wherein the address identifier is a device address for one of the at least one memory device and one of the at least one memory bank. A bank address for a memory bank. The system of claim 24, wherein the controller generates one or more separable commands for different memory devices and interleaves the issuance of these one or more separable commands for different memory devices. 26. The device of claim 25, wherein the at least one memory device comprises at least two memory banks, and wherein the controller generates one or more separable commands for each of the at least two memory banks, Interleaving the issuance of these one or more separable commands to simultaneously process the issued one or more separable commands. The system of claim 23, wherein the memory device of the memory system is connected to a common bus. The system of claim 23, wherein the memory device of the memory system is connected in series. The system of claim 23, wherein the memory device comprises a NAND flash memory device. A controller for a system having a plurality of memory devices for storing data, wherein the controller is in a serial interconnect configuration for communication with the plurality of memory devices, wherein the controller comprises: A first connector for receiving a request to access the plurality of memory devices; A translator for translating the request into a plurality of separable commands that can be interpreted by the plurality of memory devices, each command being an address identifier for one of the plurality of memory devices and one of the plurality of memory devices; A translator having a modular structure including a command identifier representing an operation to be executed by one memory device; And And a second connection for communicating with one of said plurality of memory devices for issuing said plurality of separable commands. Determining an address comprising a memory device address; Identifying a plurality of operations to execute a request to access a memory; And Providing a plurality of separable commands to the memory, each of the commands comprising a device identifier having a memory device address and a command identifier having one of the plurality of operations. The method of claim 31, wherein the method is for translating a request to access a memory device into a plurality of separable commands that can be interpreted by the memory device, The determining step includes determining an address for the memory device and an address for a memory bank of the memory device; The identifying step includes identifying a plurality of operations of jointly executing the request; The providing step includes providing the plurality of separable commands, each command including a device identifier comprising the memory device address and a memory bank address, and a command identifier comprising one of the plurality of operations. And the command identifier may be interpreted by the memory device, and wherein the plurality of separable commands are issued to the memory device. The method according to claim 31, The providing step, generating an m-byte device identifier in which m is an integer; generating an n-bit memory device address and a p-bit memory bank address, wherein each of n and p is an integer; And generating a q-byte command identifier wherein q is an integer, Interleaving each issue of the plurality of separable commands having a different device identifier. 32. The method of claim 31, wherein the memory device comprises at least two memory banks, and the method controls the at least two memory banks simultaneously, The determining step includes determining an address for the memory device and an address for each of the at least two memory banks; The identifying step includes identifying a plurality of operations that jointly execute a request to access each of the at least two memory banks; The providing step includes generating the plurality of separable commands for each of the at least two memory banks, wherein each of the plurality of separable commands is issued to the memory device. The method of claim 31, wherein the method is for interleaving a request to access a plurality of memory devices,  The determining step includes an address for each of the plurality of memory devices; The identifying step includes identifying a plurality of operations of executing each request jointly; The providing step includes a plurality of separable for each request for each of the plurality of memory devices, each command including a device identifier having the memory device address and a command identifier having one of the plurality of operations. Generating a command, wherein the command identifier can be interpreted by the memory device, wherein each of the plurality of separable commands is issued to the memory device.

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