KR20090019806A - Circular register arrays of a computer - Google Patents

Abstract

A stack processor comprises a data stack with a T register, an S register, and eight hardwired bottom registers which function in a circular repeating pattern. The stack processor also comprises a return stack containing an R register, and eight hardwired bottom registers which function in a circular repeating pattern. The circular register arrays described herein eliminate overflow and underflow stack conditions.

Description

Circular register array in a computer {CIRCULAR REGISTER ARRAYS OF A COMPUTER}

This application is filed on June 30, 2006, in US Provisional Application No. Priority to 60 / 818,084, which is part of the continuous application (CIP) of serial number 11/441, 818, "Method and Apparatus for Monitoring Inputs to a Computer," filed May 26, 2006, which is It is also part of the serial application 11 / 355,513, filed on February 16, 2006, entitled "Asynchronous Power Saving Computer." This application also claims provisional application no. 60 / 788,265, and provisional application No. filed May 3, 2006. Claim priority on 60 / 797,345. All of the above cited applications are incorporated herein by reference.

TECHNICAL FIELD The present invention relates to the field of computers and computer processors, and more particularly, to more efficient use and means of use of a stack inside a stack computer processor.

Stacked machines have less processor complexity than Complex Instruction Set Computers (CICS), and the overall system is less complex than either CICS machines or Reduced Instruction Set Computers (RICs). While less complex, they do not require cache control hardware or complex compilers for good performance. They also show excellent raw performance and excellent performance for a given price in most programming environments. Their first successful application area outweighs other system design approaches in performance in a real-time embedded control environment. Most of the stacks have been previously held in program memory, while new stack machines either maintain separate memory chips or maintain on-chip memory areas for the stacks. These stack machines provide very fast subroutine call capability and provide excellent performance for interrupt handling and task switching.

However, there is no hardware detection for stack overflow or underflow conditions. Stack overflow occurs when there are not enough registers available, which continues to enter the stack, causing the lower register (s) to be overwritten. Stack underflow occurs when all registers are emptied and causes the stack's popping to continue, producing unintended or incorrect results. Some other stack processors use stack pointers and memory management to cause an error condition to be flagged when the stack pointer goes beyond the range of memory allocated to the stack. U.S. Patent No. 6,367,005 (Zahir et al.) Discloses a register stack engine that stores enough registers in a register stack in memory to provide more available registers within the event of a stack overflow. The register stack engine also delays the microprocessor until the engine can recover the proper number of registers in the event of stack underflow.

U.S. Patent No. 6,219,685 discloses a method of comparing the result of an operation to a threshold. However, this approach does not distinguish between results that equal the threshold (which will cause an overflow exception) and results that occur equal to the threshold. Another method disclosed by the patent is to read and write hardware flags to identify overflow or underflow conditions. However, since the instructions must be executed sequentially, any instructions following the register read / write cannot proceed until the read / write operation is completed, which causes a slow process.

If there are stacks in memory, overflow or underflow will use stack items that either overwrite stack items or are not part of the stack. There is a need for an improved method of eliminating or reducing overflow or underflow within a stack.

It is an object of the present invention to provide a method and apparatus in which the data stack and return stack of a dual stack processor are hardwires accessed by individual dedicated shift registers, rather than arrays in memory accessed by stack pointers.

It is another object of the present invention to eliminate or reduce overflow and underflow of data or return stacks.

It is another object of the present invention to minimize the length of electrical connections between the 1 bit stack registers of one bidirectional stack register, thereby minimizing the required driver size and minimizing buffering.

These and other objects can be achieved by the invention described herein, that is, the invention in which a conventional stack is replaced by an array of registers operating in a circular, repeating pattern. This cyclical, repeating pattern is achieved through the use of an associated bi-directional shift register comprising a plurality of 1-bit shift registers electrically interconnected in an alternating pattern. This configuration prevents reading from the outside of the stack and prevents reading unintended empty register values.

The dual stack processor described above can function as an independently functioning processor or can be used with other similar processors or different processors in an interconnected computer array.

1 is a block diagram illustrating a general layout of a stack computer.

2 is a data stack in accordance with the present invention.

3 is a detailed view of a single register of the stack.

4 is a return stack in accordance with the present invention.

5 is a diagram of a computer array in accordance with the present invention.

FIG. 6 is a detailed diagram of the interconnect data buses of FIG. 5 and a detailed diagram illustrating a subset of the computers of FIG.

The same reference numbers in the drawings represent the same or similar components, the present invention is described with reference to these drawings. Although the present invention has been described in terms of modes for achieving the objects of the present invention, there are various modifications that will enable those skilled in the art to achieve the objects of the present invention without departing from the scope or spirit of the invention as claimed in this application. You will understand.

The embodiments and variations of the invention described herein are illustrative only and are not intended to limit the scope of the invention. Although not specifically mentioned, the present invention may be variously modified, and thus, each embodiment and component of the present invention may be modified or omitted for various applications within the spirit and scope of the disclosed invention.

1 is a block diagram illustrating the general layout of a dual stack computer 12 as used in the present invention. The computer 12 is generally a self contained computer with its RAM 24 and ROM 26.

The other basic components of the computer 12 include a return stack 28, an instruction region 30, an ALU (or processor) 32, a data stack 34, and decoding instructions, including an R register 29. Decoding logic section 36. The computer is a dual stack computer with a return stack 28 separate from the data stack 34. Those skilled in the art will generally be familiar with the operation of stack-based computers, such as the computer 12 in this example.

In the presently described embodiment, the instruction area 30 includes several registers, in which the registers 40 include the A register 40a, the B register 40b, and the P register 40c. do. In this example, the A register 40a is a full 18-bit register, and the B register 40b and the P register 40c are 9-bit registers.

The present invention discloses a stack computer processor in which data and return stacks comprise an array of registers operating in a periodic, repeating, or cyclical pattern. The data stack and return stack are not arrays in memory that are accessed by the stack pointer like many prior art computers.

2 discloses an embodiment for an 18-bit data stack in accordance with the present invention. The upper two registers in the data stack are an 18-bit T register, an 18-bit S register. The rest of the data stack contains eight additional 18-bit hardware registers, which in this example are referred to as S ₂ through S ₉ . The circular register array, S ₂ -S ₉ , can operate even in the absence of the T register and the S register. However, the presence of at least an S register along with the S ₂ -S ₉ registers provides faster access circuitry and provides optimal timing, providing higher operating speed of the circular register array. The S register also acts as a buffer between the addressable S ₂ -S ₉ registers and the rest of the processor system. This provides timing independence between the S ₂ -S ₉ registers and the rest of the processor system.

This embodiment also includes a bi-directional shift register that includes a plurality of one bit shift registers. The number of 1-bit shift registers matches the number of lower registers, which are S ₂ -S ₉ located below the S register. Each one bit shift register is coupled to corresponding S ₂ -S ₉ stack registers as shown in FIG. 2. The 1-bit shift registers are electrically interconnected in an alternating pattern, so that the S ₂ -S ₉ registers of the stack operating in a sequential cyclic interconnect pattern are shown as S _2- > S _4- > S ₆ as shown in FIG. -> S _8- > S _9- > S _7- > S _5- > S _3- > S ₂ This sequential selection of lower stack registers operates in a circular repeating pattern. The interconnect leads of one bit shift registers do not extend to more than three adjacent shift registers, which eliminates the need for long leads connecting the lower and upper shift registers. These short leads require smaller drivers and buffering is also minimized. The given embodiment uses eight additional stack registers for the circular register array. However, other combinations of lower registers used for four multiples may also be used.

2 also discloses a read bus and a write bus that interconnect the S ₂ -S ₉ registers with the T register, S register. Each 1-bit shift register of the bi-directional shift register is connected to the corresponding lower stack register inside the S ₂ -S ₉ array, where only one bit of the shift register is simultaneously read on (on) and all other The bits are read as zeros. In power-up, the shift register is initialized to include exactly setting one bit to one and all other bits to zero. In the given example, the top bit of the shift register indicates or reads S ₂ and writes to the interconnected adjacent register S ₄ .

The T register, S register, and S ₂ -S ₉ registers form a deep push down stack of 10 cells. Since the lower nine registers are circular buffers, the hardware wraps without overflow or underflow. You shouldn't expect to get more than 10 registers on the stack and get them all back, and it's possible to take more copies of the last eight items that are permanently taken from the lower part of the stack. There is no underflow that means an error. Duplicating a pattern of eight words (or four, two or one) may be the fastest way, if the lower eight will be read repeatedly if the program keeps taking values from the stack. Because.

Similarly, no stack overflow occurs, which means that the stack pointers cause the stack to move somewhere. Because the stack is finite, if more than 10 items are entered into the stack, only the last 10 items will remain: the first 10 items after that will each overwrite one of the S ₂ -S ₉ registers ( overwrite). There is no need to 'initialize' the stack to a given location, but just declare that the stack is empty by starting using the stack from anywhere in the stack.

3 is an expanded view of each register within a data or return stack. Each 18-bit register contains 18 latches numbered 0 through 17. There are a set of 18 input pass gates (numbered 0 through 17), each of which is connected to the 18 latches via a read bus and a write bus. There is also a set of 18 output pass gates (numbered 0 through 17), each of which is connected to the 18 latches via the read bus and the write bus. The input pass gates are controlled by write control of inverter amplifiers; The output pass gates are controlled by read control of the inverter amplifiers.

4 discloses an 18-bit stack in accordance with the present invention. The upper register in the return stack is an 18-bit R register, and eight additional 18-bit hardware registers are below the R register, where R ₁ -R ₈ are referenced. The lower eight registers, R ₁ -R ₈ , function in an alternating pattern as a repeating circular array, similar to the data stack disclosed above.

The circular register arrays, R ₁ -R ₈ , can operate even when no R register is present. However, the presence of the R register along with the R ₁ -R ₈ registers provides faster access circuitry and provides optimal timing, which speeds up the operation of the circular register array. In addition, R register provides an independent timing between R ₁ -R ₈ address to act as a buffer between the remainder of the available register and the processor system, which is R ₁ -R ₈ remainder of the addressable register and the processor system .

This embodiment also comprises a bi-directional shift register comprising a plurality of 1 bit shift registers. The number of one bit shift registers corresponds to the number of R ₁ -R ₈ below the R register, which is an additional lower register. Each one bit shift register is coupled to the corresponding R ₁ -R ₈ lower stack register as shown in FIG. 4. The 1-bit shift registers of the bi-directional shift register are electrically interconnected in an alternating pattern such that the R ₁ -R ₈ registers of the stack operating in a sequential cyclic interconnect pattern are R as shown in FIG. 4. _1- > R _3- > R _5- > R _7- > R _8- > R _6- > R _4- > R _2- > R ₁ This recursive selection of registers operates in a recursive repeating pattern. The interconnect leads of the shift register do not extend to more than three adjacent 1-bit shift registers, which eliminates the need for long leads connecting the lower 1-bit shift register and the upper 1-bit shift register. These short leads require smaller drivers and buffering is also minimized. Eight additional return registers are disclosed in the given embodiment, but other lower register combinations of four multiples may also be used in this circular register array. The read bus and write bus interconnect the R ₁ -R ₈ registers. Each 1-bit register of the shift register is connected to the corresponding stack register inside the R ₁ -R ₈ array. Only one bit of the shift register is read (on) at one time and all other bits are read as zero. In power-up, the shift register is initialized to include exactly setting one bit to one and all other bits to zero. In the given example, the upper bits of the shift register indicate or read R ₁ and write to the interconnected adjacent register R ₃ .

In the present invention, there is no hardware detection of stack overflow or underflow conditions. Generally, prior art processors use stack pointers and memory management or the like to flag an error condition when the stack pointer goes beyond the range of memory allocated to the stack. When stacks are allocated or maintained in memory, overflow or underflow may overwrite the stack item or use the stack item differently than intended. However, because the lower registers of the present invention function as a circular array, the stacks cannot overflow or underflow beyond the stack area. Instead, circular arrays will only wrap around an array of registers. Since the stacks have a finite depth, entering anything above the stack means will overwrite the lower part. In a given embodiment, entering more than 10 items into the data stack, or entering more than nine items into the return stack will result in items being overwritten in the lower portion of the stack.

It is the software's responsibility to record the number of items on the stacks and not enter more items than each stack can hold. The hardware will not detect the overwriting of items in the lower part of the stack or flag it as an error. It should be noted that software can use circular arrays in the lower portion of the stacks in several ways. As one example, the software may simply assume that the stack is "empty" at some time. Older items will be pushed into the lower part where they will be lost as the stack is filled, so there is no need to delete old items from the stack, so there is no need to initialize the program to assume that the stack is empty.

Another advantage that can be used is to reuse register items without having to reload the register items for reuse. The lower eight items of these stacks can also be read or written in loops that take advantage of the stack wrap. After two data stack reads, T and S will have copies of two items from the circular array of lower eight stack registers. After 8 more reads, T and S will be reloaded back to the same value read back from the bottom using the stack wrap. There is no limit to the number of times these eight items can be read in a sequence of stacks without duplicating or writing back to the stack. Algorithms that cycle through a set of parameters that can be repeated in eight, four, or two cells in a data stack or return stack are stacks as the lower registers only wrap if not a stack error. Parameters can be read repeatedly from.

Although the present invention has been described as an embodiment for the data stack and return stack of a dual stack 18-bit processor, other bit size processors may also be used with the present invention.

The circular register arrays described above have been described for a single dual stack processor. However, the circular register arrays described above may also be used in an array of several self-contained computers, such as the computer array 10 shown in FIG. This computer array 10 has a plurality of (24 in the example shown) computers (sometimes referred to as "cores" or "nodes" in the example of this array). In the example shown, all of the computers 12 are located on a single die 14. In accordance with the present invention, each of the computers 12 generally functions independently of the computer. Computers 12 are interconnected by a plurality of interconnect data buses 16. In this example, the data buses 16 are bidirectional asynchronous high speed parallel data buses, which are within the scope of the present invention, and other interconnecting means within the scope of the present invention may be used for the same purpose.

Computer 12e is an example of one of computers 12 that is not in the periphery of array 10. That is, the computer 12e has four orthogonally adjacent computers 12a, 12b, 12c, 12d. This grouping of computers 12a through 12e will be used herein in the context of a more detailed discussion of communications between the computers 12 of the array 10 as illustrative. As can be seen in FIG. 5, internal computers such as computer 12e will have four other computers 12 that are the objects that can communicate directly via buses 16. In the discussion that follows, the principles discussed above allow computers 12 in the periphery of the array 10 to communicate directly with only the other three of the computers 12, or in the case of corner computers 12 only. This applies to all computers 12 that are expected to communicate directly with the other two computers.

FIG. 6 is a more detailed view of a portion of FIG. 5 showing only some of the computers 12, in particular showing the computers 12a through 12e. 6 also shows data buses 16 with read lines 18, write lines 20, and a plurality of data lines 22 (18 in this example). These data lines 22 can transmit all bits of one 18-bit command word, generally in parallel at the same time.

According to the inventive method, a computer 12, such as computer 12e, can set one, two, three, or all four of its read lines 18 high. , One, two, three, or four adjacent computers 12 may be ready to receive data. Similarly, computer 12 may also set one, two, three, or all four of its write lines 20 to high.

When one of the adjacent computers 12a, 12b, 12c, or 12d sets the write line 20 high between itself and the computer 12e, if the computer 12e Has already set the corresponding read line 18 high, the word is transmitted from computer 12a, 12b, 12c or 12d to computer 12e via combined data lines 22. . The transmitting computer 12 then transmits frees the write line 20 and the receiving computer (12e in this example) causes both the write line 20 and the read line 18 to be low. This operation of the receiving computer 12e will notify the sending computer 12 that data has been received.

As shown in FIG. 1, in this embodiment of the present invention, the computer 12 has four communication ports 38 for communicating with neighboring computers 12 as described above. These communication ports 38 are three-state drivers with an off state, a receive state (to supply signals to the computer 12), and a transmit state (send signals from the computer 12). . If a particular computer 12 is not inside the array (FIG. 5) as in the example of computer 12e, one or more communication ports 38 are not used at least for the purposes described above in that particular computer. Will not. However, such communication ports 38 at the edge of the die may have additional circuitry, which is designed into such a computer 12 or external to the computer 12, in combination with the computer 12, such that The communication port 38 causes it to operate like the external I / O port 39 (FIG. 5). Examples of such external I / O ports 39 include, but are not limited to, USB ports, RS232 serial bus ports, parallel communication ports, analog-to-digital and / or digital-to-analog conversion ports, and many other possible ports. It is not limited. In FIG. 5, an "edge" computer 12f is shown with coupled interface circuit 80 that communicates with an external device 82 via an external I / O port 39.

Various modifications may be made without departing from the spirit and scope of the invention. For example, although the invention is described as using particular computers 12, many or all of the inventive embodiments may be readily utilized in other computer designs, other computer arrays, and the like.

Although the present invention is first described with respect to communications between computers 12 in array 10 on array 10 on single die 14, the same principles and methods are for example computer 120 and its dedicated memory. It may be used or modified to achieve other inter-device communications such as inter-communication, or communication between the computer 12 and an external device in the array 10.

Similarly, although the present invention is disclosed herein with respect to a dual stack processor, the present invention may also be used for a single stack processor or a processor including more than two stacks.

All of the above is merely a part of examples of available embodiments of the present invention. Those skilled in the art will readily appreciate that many various modifications and alternatives may be made without departing from the scope and spirit of the invention. Accordingly, the disclosure of this specification should not be construed as limiting the scope of the invention, but rather as the appended claims cover the full scope of the invention.

Claims (42)

A memory for storing data and codes; A processor for processing the data and code; And A stack computer comprising a plurality of hardware registers that can be used as a stack by the processor. The method of claim 1, And wherein the registers of the plurality of hardware registers are accessed in forward order or reverse order according to a predetermined iteration sequence. The method of claim 2, When the registers are accessed in the forward order, the first of the registers in the sequence is accessed after the last of the registers in the sequence; And when the registers are accessed in the reverse order, the last one of the registers is accessed after the first one of the registers. The method of claim 1, And further comprising a bi-directional shift register comprising a plurality of single bit registers, wherein the output of each of the single bit registers is coupled to an associated one of the registers at least in part to control access, the amount A direction shift register serving as a stack pointer by shifting bits along the single bit registers. The method of claim 1, A last one of the single bit registers is coupled to a first one of the single bit registers, the single bit registers providing a circular path for the bit shifted along the single bit registers Stack computer. A data stack comprising at least one data register; And A return stack comprising at least one return register; And wherein each of the data stack and the return stack can accept an 18 bit instruction word. The method of claim 6, And said at least one data register comprises a top of a stack (T) register. The method of claim 7, wherein And said at least one data register further comprises a second location on said stack (S) register. The method of claim 6, And said at least one return register comprises an upper register (R). The method of claim 6, And the data stack further comprises an array of hardware registers. The method of claim 6, And the return stack further comprises an array of hardware registers. The method of claim 10, And the array operates in a cyclical pattern. The method of claim 11, And the array operates in a cyclical pattern. To build a computer processor: Inputting a plurality of command words into corresponding plurality of command cells of the processor; And Processing the plurality of command words, Wherein no overflow or underflow of instructions occurs due to said input and said processing. The method of claim 14, And the inputting step comprises filling all available instruction cells. The method of claim 15, The inputting step further comprises inputting additional command words after all of the available command cells have been filled. The method of claim 16, And wherein said inputting and processing are performed without using a software implementation pointer. The method of claim 14, And said processing comprises repeatedly reusing said plurality of instruction words without reloading said plurality of instruction words. An array of registers; And It consists of a shift register: And the shift register comprises a plurality of one bit shift registers interconnected by electrical leads, wherein the number of the plurality of one bit shift registers coincides with the number of registers in the array of registers. The method of claim 19, And at least one register located above the array of registers. The method of claim 19, And the array of registers further comprises a read bus and a write bus interconnecting the array. The method of claim 19, And said array of registers operate in a circular pattern. The method of claim 20, And the array of registers are stacked. The method of claim 23, And the one bit shift registers are interconnected by the electrical leads in an alternating pattern. The method of claim 19, And the processor is a data stack. The method of claim 25, And said array of registers is comprised of eight data registers. The method of claim 25, And wherein the array of registers consists of a plurality of four data registers. The method of claim 24, And the processor is a return stack. The method of claim 28, And said array of registers is comprised of eight return registers. The method of claim 28, And wherein the array of registers consists of a plurality of four return registers. An array of registers; And A computer processor comprising a bi-directional shift register hardwired to an array of registers: The bi-directional shift register further comprises a plurality of one bit shift registers interconnected by electrical leads, wherein the number of the plurality of one bit shift registers coincides with the number of registers in the array of registers. Characterized by a computer processor. The method of claim 31, wherein And at least one register located above the array of registers. The method of claim 31, wherein And the shift register serves as a hardware pointer to the array of registers. The method of claim 31, wherein And a read bus and a write bus. The method of claim 31, wherein Wherein each of the plurality of one bit shift registers corresponds to an associated register of the array of registers. 36. The method of claim 35 wherein Of said plurality of one bit shift registers, only one shift register is activated at a time. The method of claim 31, wherein And the array of registers further comprises a read bus and a write bus interconnecting the array. The method of claim 31, wherein And the plurality of one bit shift registers are interconnected by electrical leads to minimize driver size and buffering. The method of claim 31, wherein And all of the electrical leads extend between up to three adjacent one bit shift registers. The method of claim 39, And said array of registers is comprised of eight registers. The method of claim 31, wherein And the processor is a data stack. The method of claim 31, wherein And the processor is a return stack.

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