KR20090013481A - Source driver circuit and liquid crystal display device having the same - Google Patents

Abstract

A source driver circuit and a liquid crystal display including the source driver circuit are provided to reduce the power source noise level and to improve the EMI property by dispersing the power noise frequency component of the source driver circuit. A source driver circuit(1000) comprises a random number generator(1100) and a plurality of source drivers(1210,1220,1230,1240). The random number generation unit provides the random number of M (M is the natural number more than 2) bit. The enable source driver in which the enable signal is applied receives the system clock. The enable source driver generates the normal clock without delay. The disable source driver in which the enable signal is not applied receives the system clock. The disable source driver generates the delay clock delayed based on the random number of M bit. Each source driver includes a switch, a delay and a clock buffer. The switch receives the system clock and decides the output direction of the system clock. The clock buffer receives the normal clock or the delay clock.

Description

SOURCE DRIVER CIRCUIT AND LIQUID CRYSTAL DISPLAY DEVICE HAVING THE SAME}

The present invention relates to a liquid crystal display device. More specifically, the present invention relates to a source driver circuit for noise reduction and a liquid crystal display device having the source driver circuit.

As the use of various electronic devices increases, electromagnetic waves generated from them cause malfunctions of precision electronic devices. This is called electromagnetic interference (EMI), which means that disturbances occur between the electronic devices, thereby impairing the functions of the electronic devices.

In recent years, the number of source drivers used in the liquid crystal display device increases according to the size of the panel and the high resolution of the panel. Accordingly, the influence of EMI also increases.

The source driver circuit used in the liquid crystal display device includes a plurality of source drivers. Each source driver receives the enable signal sequentially and receives data from the timing controller when the enable signal is applied. That is, when the first source driver receives the enable signal from the timing controller, the first source driver receives data from the timing controller. After the first source driver receives the data, the first source driver sends an enable signal to the second source driver. When the second source driver receives the enable signal from the first source driver, the second source driver receives data from the timing controller. As such, each source driver sequentially receives an enable signal and data. On the other hand, all source drivers always receive the system clock because they must be in a waiting state to receive an enable signal from the timing controller.

The system clock received by the source driver is applied to the clock buffer to send the system clock to the data processor. Since the clock buffer has no function of varying frequency, the frequency of the clock output from the clock buffer is the same as the frequency of the input system clock. Therefore, all frequencies used by the plurality of source drivers in the source driver circuit are the same, and the power supply noise component also includes the same frequency component. This phenomenon increases the level of power supply noise and degrades EMI characteristics.

In order to solve the above problems, the present invention provides a source driver circuit that can reduce the level of power supply noise, and can improve the EMI characteristics.

In addition, the present invention can reduce the level of power supply noise, and provides a liquid crystal display including the source driver circuit to improve the EMI characteristics.

In order to achieve the above object, the source driver circuit according to an embodiment of the present invention includes a random number generator and a plurality of source drivers.

The random number generator provides a random number of M bits (M is a natural number of 2 or more). The plurality of source drivers may be configured to receive a system clock and receive a normal clock without an enable signal to which an enable signal is applied, and to enable a source clock without the enable signal to receive the system clock. A delay clock delayed based on the random number of M bits is generated.

Each of the source drivers may include a switch unit, a delay unit, and a clock buffer. The switch unit receives the system clock to determine the output direction of the system clock, the delay unit generates the delay clock based on the random number of the M bit when receiving the system clock from the switch unit, the clock buffer The normal clock or the delay clock may be received.

The switch unit may output the system clock to the clock buffer from the enable source driver and output the system clock to the delay unit from the disable source driver.

The random number generator includes M flip-flops and a logic gate cascaded to each other, and the logic gate performs a logic operation based on two outputs of the flip-flops and outputs a result of the logic operation among the flip-flops. Can be supplied to one input.

The delay unit includes a plurality of buffers cascaded to each other, switches and capacitors respectively connected between the buffers, and the switches may be turned on or off based on the random number of the M bits.

Each of the source drivers may further include a counter and a selector. The counter unit counts the number of times the enable signal is input to each of the source drivers, and the selector selects N bits (N is a natural number) among the random numbers of the M bits based on the number of times and outputs them to the delay unit. Can be.

The counter unit may include a plurality of flip-flops based on the number of source drivers, and the flip-flops may be cascaded to each other to output bits corresponding to the number of times.

The selector includes N selectors, and each selector may output one of the L bits by receiving an L (L is a natural number of two or more) bits among the random numbers of the M bits.

In order to achieve the above object, the liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal panel, a gate driver circuit, a source driver circuit, and a timing controller.

The liquid crystal panel includes a plurality of pixels formed at intersections of the plurality of gate lines and the plurality of source lines. The gate driver circuit supplies a gate signal to the gate lines. In the source driver circuit, the enable source driver to which the enable signal is applied receives a system clock to generate a normal clock without a delay, and the disable source driver to which the enable signal is not applied receives the system clock to receive an M bit. It includes a plurality of source drivers for generating a delayed clock delay based on a random number. The timing controller provides a gate control signal to the gate driver circuit, and provides the system clock and the enable signal to the source driver circuit.

Each of the source drivers may include a random number generator, a switch unit, a delay unit, and a clock buffer. The random number generator generates the random number of the M bit, the switch unit receives the system clock to determine the output direction of the system clock, and the delay unit receives the system clock from the switch unit, the random number of the M bit The delay clock is generated based on the clock buffer, and the clock buffer may receive the normal clock or the delay clock.

The switch unit may output the system clock to the clock buffer from the enable source driver and output the system clock to the delay unit from the disable source driver.

The random number generator includes M flip-flops and a logic gate cascaded to each other, and the logic gate performs a logic operation based on two outputs of the flip-flops and outputs a result of the logic operation to the flip-flops. Can be supplied to either input.

The delay unit includes a plurality of buffers cascaded to each other, switches and capacitors connected between the buffers, respectively, and the switches may be turned on or off based on the random number of the M bits.

Each of the source drivers may further include a counter and a selector. The counter unit counts the number of times that the enable signal is input to each of the source drivers, and the selector selects N bits (N is a natural number) among the random numbers of the M bits based on the number and outputs the delay unit. can do.

The counter unit may include a plurality of flip-flops based on the number of source drivers, and the flip-flops may be cascaded to each other to output bits corresponding to the number of times.

The selector includes N selectors, and each selector may output one of the L bits by receiving an L (L is a natural number of two or more) bits among the random numbers of the M bits.

The source driver circuit and the liquid crystal display according to the exemplary embodiment of the present invention may delay a system clock received from the timing controller. As a result, the disabled source drivers can generate a clock with a different frequency than the system clock. Therefore, by distributing the power supply noise frequency components of the source driver circuit, the power supply noise level can be reduced and the EMI characteristics can be improved.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in. As the inventive concept allows for various changes and numerous modifications, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. It should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well. The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a source driver circuit according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the source driver circuit 1000 includes a random number generator 1100 and a plurality of source drivers 1210, 1220, 1230, and 1240.

The random number generator 1100 generates a random number R of M (M is a natural number of two or more) bits in response to each system clock CLK when the system clock CLK is applied from the outside, thereby generating a plurality of source drivers 1210. 1220, 1230, 1240. The plurality of source drivers 1210, 1220, 1230, and 1240 are cascaded to each other and sequentially receive the enable signal SEN. Each source driver receives data when an enable signal SEN is applied. First, the first source driver 1210 receives an enable signal SEN from the outside and receives data. The first source driver 1210 receiving the data transmits an enable signal SEN to the second source driver 1220. The second source driver 1220 receives the enable signal SEN from the first source driver 1210 to receive data. In this manner, the enable signal SEN is sequentially received to the last P source driver 1240 to receive data. Therefore, when one source driver receives the enable signal SEN from among the plurality of source drivers 1210, 1220, 1230, and 1240 to receive data, the remaining source drivers receive the data because the enable signal is not applied. I never do that. On the other hand, since all of the plurality of source drivers 1210, 1220, 1230, and 1240 must be in a standby state for receiving the enable signal SEN, the system clock CLK is always received from the outside. The enable source driver to which the enable signal SEN is applied generates a normal clock that does not delay the system clock CLK by receiving the system clock CLK, and the disable source to which the enable signal SEN is not applied. The driver receives the system clock CLK and generates a delay clock that delays the system clock CLK based on the random number R of M bits.

The random number generator 1100 may be commonly used by each of the source drivers 1210, 1220, 1230, and 1240 as shown in FIG. 1, and each of the source drivers 1210, 1220, 1230, and 1240 may be a random number generator. 1100.

2 is a block diagram illustrating a source driver according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the source driver 2000 includes a switch unit 2100, a delay unit 2200, and a clock buffer 2300.

The switch unit 2100 receives the system clock CLK and determines the output direction of the system clock CLK. That is, the enable source driver outputs the system clock CLK to the clock buffer 2300 by turning on only the first switch 2110 and the second switch 2120 in response to the enabled enable signal SEN. In response to the inversion signal SENB of the enable signal SEN, the enable source driver turns on only the third switch 2130 and the fourth switch 2140 to output the system clock CLK to the delay unit 2200. When the delay unit 2200 receives the system clock CLK from the switch unit 2100, the delay unit 2200 delays the system clock CLK based on the random number R of M bits to generate the delay clock DCLK. In some embodiments, the enable source driver may turn off the operation of the delay unit 2200 to reduce power consumption. The clock buffer 2300 receives the normal clock NCLK without delaying the system clock CLK from the switch unit 2100 in the enable source driver, and the system clock CLK from the delay unit 2200 in the disable source driver. Receive a delay clock DCLK. Therefore, all the disabled source drivers may delay the system clock CLK to generate a delay clock DCLK different from the frequency of the system clock CLK.

3 is a block diagram illustrating a source driver according to another exemplary embodiment of the present invention.

Referring to FIG. 3, the source driver 3000 includes a switch unit 3100, a delay unit 3200, a clock buffer 3300, a random number generator 3400, a counter unit 3500, and a selector 3600. do.

Unlike the source driver 2000 illustrated in FIG. 2, the source driver 3000 illustrated in FIG. 3 includes a counter unit 3500 and a selector 3600, and a delay unit 3200 included in each source driver. You can change the value entered in.

The counter unit 3500 counts the number of times the enable signal SEN is input to each of the source drivers 1210, 1220, 1230, and 1240, and outputs the count number T to the selector 3600. The random number generator 3400 generates an M-bit random number R in response to each system clock CLK and provides the generated random number R to the selector 3600. The selector 3600 delays the select signal S that selects an N (N is a natural number) bit among the random numbers R of M bits based on the count number T received from the counter 3500. Output to The switch unit 3100 receives the system clock CLK and determines the output direction of the system clock CLK. That is, in the enable source driver, only the first switch 3110 and the second switch 3120 are turned on in response to the enable signal SEN, and the system clock CLK is output to the clock buffer 3300, and the disable source is turned on. The driver outputs the system clock CLK to the delay unit 3200 by turning on only the third switch 3130 and the fourth switch 3140 in response to the inversion signal SENB of the enable signal SEN. When the delay unit 3200 receives the system clock CLK from the switch unit 3100, the delay unit 3200 delays the system clock CLK based on the N-bit selection signal S to generate the delay clock DCLK. The clock buffer 3300 receives the normal clock NCLK without delaying the system clock CLK from the switch unit 3100 in the enable source driver, and the system clock CLK from the delay unit 3200 in the disable source driver. Receive a delay clock DCLK. Therefore, the disabled source drivers may generate a delay clock DCLK having a different frequency from the system clock CLK and having different frequencies.

4 is a circuit diagram illustrating a random number generator according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the random number generator 3400 includes M flip-flops 3410, 3420, 3430, and 3440 and a logic gate 3450.

The M flip-flops 3410, 3420, 3430, 3440 are cascaded with each other, and the logic gate 3450 is a logic operation based on two outputs of the M flip-flops 3410, 3420, 3430, 3440. M random numbers R1, R2, and RM are generated by supplying the result of the logical operation to one of M flip-flops 3410, 3420, 3430, and 3440. The M flip-flops 3410, 3420, 3430, and 3440 have a plurality of source drivers 1210, 1220, and 1230 when an enable signal SEN is applied to the last P source driver 1240 to receive data. 1240 is reset in response to the clock signal CLK1 for outputting the received data. The logic gate 3450 may be an XNOR logic gate.

5 is a circuit diagram illustrating an embodiment of a counter unit according to an embodiment of the present invention.

Referring to FIG. 5, the counter 3500 includes a plurality of flip flops 3510, 3520, and 3530. The counter 3500 includes a plurality of flip-flops 3510, 3520, and 3530 based on the number of source drivers 1210, 1220, 1230, and 1240. That is, if the number of source drivers is P, the number of flip-flops 3510, 3520, and 3530 is log ₂ P or more. Each of the flip-flops 3510, 3520, and 3530 is cascaded to each other so that the count T corresponds to the number of times the enable signal SEN is applied to the respective source drivers 1210, 1220, 1230, and 1240. Output each of the bits T1, T2, and TL. Also, when the enable signal SEN is applied to the last P source driver 1240 and the data is received, the plurality of source drivers 1210, 1220, 1230, and the like. 1240 is reset in response to the clock signal CLK1 for outputting the received data. For example, if the number of source drivers 1210, 1220, 1230, and 1240 included in the source driver circuit 1000 is four, each counter unit may include two flip-flops. In this case, when the enable signal is applied to the first source driver, the counters in the respective source drivers have values corresponding to '1,0,0,0' (ie, 01, 00, 00, 00), When the enable signal is applied to the second source driver, the counters in the respective source drivers have values corresponding to '2,1,0,0' (ie, 10, 01, 00, 00), and the third When the enable signal is applied to the source driver, the counters in the respective source drivers have values corresponding to '3,2,1,0' (ie, 11, 10, 01, 00), and the fourth source driver. When the enable signal is applied, the counters in the respective source drivers may be reset to have values corresponding to '0,0,0,0' (ie, 00, 00, 00, 00). Therefore, the output values of the counters included in the respective disable source drivers may be different.

6 is a circuit diagram illustrating a selector according to an exemplary embodiment of the present invention.

The selector 3600 includes N selectors 3610, 3620, 3630, and 3640. Each of the selectors 3610, 3620, 3630, and 3640 receives an L bit among the M bits of the random number R provided by the random number generator 3400, and receives one of the received L bits from the counter part 3500. The output is based on the number of times T received. For example, the selector may receive two bits among the M bits of random number R, and output one by using T1 output from the first flip-flop of the counter unit as a control signal.

7A and 7B are circuit diagrams illustrating a delay unit according to an exemplary embodiment of the present invention.

Referring to FIG. 7A, the delay unit 3200 may include a plurality of buffers 3211, 3212, 3113, 3214, and 3215, a plurality of switches 3221, 3222, and 3223, and a plurality of capacitors C1, C2,. CN). The plurality of buffers 3211, 3212, 3113, 3214, and 3215 are cascaded to each other. The first capacitor C1 is connected between the ground voltage and the first switch 3221, and the first switch 3221 is connected between the terminal N1 and the first buffer 3211 and the second buffer 3212. It is connected between the capacitor (C1). The second capacitor C2 is connected between the ground voltage and the second switch 3222, and the second switch 3222 is connected between the terminal N2 and the second buffer 3212 and the third buffer 3213. It is connected between the capacitor (C2). In this way, the Nth capacitor CN is connected between the ground voltage and the Nth switch 3223, and the Nth switch 3223 is a terminal between the Nth buffer 3214 and the N + 1st buffer 3215. It is connected between N3 and the Nth capacitor CN. The switches 3221, 3222, and 3223 are turned on / off in response to the selection signal S applied from the selection unit 3600. Therefore, the system clock CLK input to the delay unit 3200 is delayed according to the on / off of the plurality of switches 3221, 3222, and 3223. Also, since the select signal S applied from the selector 3600 may be different for each disable source driver, the delay units included in the disable source drivers may have different delay times. May occur.

Referring to FIG. 7B, the capacitors C1, C2, and CN illustrated in FIG. 7A may be replaced with MOS capacitors MP1, MP2, MPN, MN1, MN2, and MNN.

Although the switches 3221, 3222, and 3223 shown in FIGS. 7A and 7B are shown to be turned on / off in response to the selection signal S, the delay unit 2200 of the source driver 2000 is random as shown in FIG. 2. When (R) is applied, the switches 3221, 3222, and 3223 may be turned on or off in response to the random number (R).

8 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 8, the liquid crystal display 8000 includes a timing controller 8100, a gate driver circuit 8200, a source driver circuit 8300, and a liquid crystal panel 8400.

The timing controller 8100 provides the gate control signal GCS to the gate driver circuit 8200, and provides the enable signal SEN, the system clock CLK, and the data signal DATA to the source driver circuit 8300. do. The gate driver circuit 8200 supplies a gate signal to the gate lines GL1, GL2,..., GLQ. The source driver circuit 8300 supplies the data signal DATA to the source lines SL1, SL2,..., SLP. The liquid crystal panel 8400 includes a plurality of pixels formed at intersections of the plurality of gate lines GL1, GL2,..., GLQ and the plurality of source lines SL1, SL2,..., SLP. Display the data signal DATA.

The source driver circuit 8300 includes a plurality of source drivers. When one source driver receives the enable signal SEN and receives data, the remaining source drivers do not receive the enable signal SEN, and thus data. Does not receive. On the other hand, since all of the plurality of source drivers must be in a waiting state for receiving the enable signal SEN, the system clock CLK is always received from the timing controller 8100.

Each source driver includes a random number generator, a switch, a delay, and a clock buffer. The random number generator generates M-bit random numbers in response to every system clock (CLK). The switch unit receives the system clock CLK and determines the output direction of the system clock CLK. The delay unit generates a delay clock by delaying the system clock CLK based on a random number of M bits when receiving the system clock CLK. The clock buffer includes a clock buffer which receives a normal clock which does not delay the system clock CLK or a delay clock that delays the system clock CLK. Accordingly, the enable source driver to which the enable signal SEN is applied generates a normal clock that does not delay the system clock CLK by receiving the system clock CLK, and disables the disabled signal SEN. The enable source driver receives the system clock CLK and generates a delay clock that delays the system clock CLK based on a random number of M bits. Therefore, the disable source drivers may generate a delay clock DCLK having a different frequency from the system clock CLK.

In some embodiments, each of the source drivers included in the source driver circuit 8300 may further include a counter and a selector between the delay unit and the random number generator.

The counter unit counts the number of times the enable signal SEN is input to each source driver, and the selector outputs a selection signal in which the N bits are selected among the random numbers of M bits based on the number of times the counter unit counts. In this case, output values of the counter unit included in each source driver may be different. Therefore, the disable source drivers may generate a delay clock DCLK having different frequencies.

9 is a view illustrating an operation of a source driver circuit and a liquid crystal display including the same according to an embodiment of the present invention.

Referring to FIG. 9, the delay time of the delay clock DCLK is different every time the system clock CLK is applied, and a delay clock DCLK that delays the system clock CLK is generated. Therefore, it can be seen that power noise components are dispersed and power supply noise levels are lowered.

According to the present invention, the source driver circuit can delay the system clock received from the timing controller. As a result, the disable source drivers can use a clock having a different frequency than the system clock. Therefore, by distributing the power supply noise frequency components, the power supply noise level can be reduced and the EMI characteristics can be improved.

While the foregoing has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

1 is a block diagram illustrating a source driver circuit according to an exemplary embodiment of the present invention.

2 is a block diagram illustrating a source driver according to an exemplary embodiment of the present invention.

3 is a block diagram illustrating a source driver according to another exemplary embodiment of the present invention.

4 is a circuit diagram illustrating a random number generator according to an exemplary embodiment of the present invention.

5 is a circuit diagram illustrating an embodiment of a counter unit according to an embodiment of the present invention.

6 is a circuit diagram illustrating a selector according to an exemplary embodiment of the present invention.

7A and 7B are circuit diagrams illustrating a delay unit according to an exemplary embodiment of the present invention.

8 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

9 is a diagram illustrating the performance of a source driver circuit and a liquid crystal display including the same according to an embodiment of the present invention.

Claims (16)

A random number generator that provides a random number of M bits (M is a natural number of 2 or more); And The enable source driver to which the enable signal is applied receives a system clock to generate a normal clock without delay, and the disable source driver to which the enable signal is not applied is received the system clock and based on the random number of the M bits. And a plurality of source drivers for generating a delay clock which is delayed. The method of claim 1, wherein each of the source drivers, A switch unit configured to receive the system clock and determine an output direction of the system clock; A delay unit generating the delay clock based on the random number of the M bits when receiving the system clock from the switch unit; And And a clock buffer for receiving the normal clock or the delay clock. The method of claim 2, wherein the switch unit, And the system clock is output from the enable source driver to the clock buffer and the system clock is output from the disable source driver to the delay unit. 4. The logic circuit of claim 3, wherein the random number generator comprises M flip-flops and a logic gate cascaded to each other, the logic gate performing a logic operation based on two outputs of the flip-flops and a result of the logic operation. Supplying the input to one of the flip-flops. The method of claim 4, wherein the delay unit comprises a plurality of buffers cascaded to each other, switches and capacitors respectively connected between the buffers, and the switches are turned on / off based on the random number of the M bit. Source driver circuit. The method of claim 2, wherein each of the source drivers, A counter unit for counting the number of times the enable signal is input to each of the source drivers; And And a selector for selecting N bits (N is a natural number) among the random numbers of the M bits based on the number and outputting the bits to the delay unit. The source driver of claim 6, wherein the counter unit comprises a plurality of flip-flops based on the number of the source drivers, and the flip-flops are cascaded to each other to output bits corresponding to the number of times. Circuit. 7. The apparatus of claim 6, wherein the selector comprises N selectors, and each selector receives an L (L is a natural number of two or more) bits among the random numbers of the M bits and outputs one of the L bits. Source driver circuit. A liquid crystal panel having a plurality of pixels formed at intersections of the plurality of gate lines and the plurality of source lines, respectively; A gate driver circuit for supplying a gate signal to the gate lines; The enable source driver to which the enable signal is applied receives a system clock to generate a normal clock without a delay, and the disable source driver to which the enable signal is not applied receives the system clock and based on a random number of M bits A source driver circuit comprising a plurality of source drivers for generating a delayed delay clock; And And a timing controller configured to provide a gate control signal to the gate driver circuit and to provide the system clock and the enable signal to the source driver circuit. The method of claim 9, wherein each of the source drivers, A random number generator for generating a random number of the M bits; A switch unit configured to receive the system clock and determine an output direction of the system clock; A delay unit generating the delay clock based on the random number of the M bits when receiving the system clock from the switch unit; And And a clock buffer for receiving the normal clock or the delay clock. The method of claim 10, wherein the switch unit, And the system clock is output from the enable source driver to the clock buffer, and the system clock is output from the disable source driver to the delay unit. 12. The apparatus of claim 11, wherein the random number generator comprises M flip-flops and a logic gate cascaded to each other, the logic gate performing a logic operation based on two outputs of the flip-flops and a result of the logic operation. Supplying an input to one of the flip-flops. The method of claim 12, wherein the delay unit comprises a plurality of buffers cascaded to each other, switches and capacitors respectively connected between the buffers, and the switches are turned on / off based on the random number of the M bit. A liquid crystal display device. The method of claim 10, wherein each of the source drivers, A counter unit for counting the number of times the enable signal is input to each of the source drivers; And And a selector which selects N bits (N is a natural number) among the random numbers of the M bits and outputs them to the delay unit based on the number of times. 15. The liquid crystal display of claim 14, wherein the counter unit comprises a plurality of flip-flops based on the number of the plurality of source drivers, and the flip-flops are cascaded to each other to output bits corresponding to the number of times. . 15. The apparatus of claim 14, wherein the selector comprises N selectors, each selector receiving an L (L is a natural number of two or more) bits among the random numbers of the M bits and outputting one of the L bits. A liquid crystal display device.

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