KR20080105821A - Liquid crystal display device - Google Patents

Abstract

A liquid crystal display device is provided to reduce the resistance difference of the data linking part which is installed at the center part, and the edge part. A gate line(112) intersects with a data line(115). A pixel region is defined at an active region. A data line is connected to the outer part of the active area. A plurality of data link line(135a,135d) are arranged in the center part and edge part based on a data drive IC(Integrated Circuit). A plurality of gate link wring is extended from a gate line of the outer part of the active area. A gate pad and a data pad(125) are arranged in order to deliver signal to data link line.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY DEVICE}

1 is a plan view of a thin film array substrate of a liquid crystal display according to the related art.

2A and 2B are plan views showing a process cross-sectional view of a data link line and a structural cross section including a data link line having a one-layer structure according to the prior art;

3A and 3B are plan views showing a process cross-section of a data link line and a cross-sectional view of a structure including a data link line having a two-layer structure according to the prior art;

4 is a plan view of a thin film array substrate of a liquid crystal display according to an exemplary embodiment of the present invention.

5 is a cross-sectional view of a structure including a data link line of a two-layer structure of the present invention.

6A and 6B are plan views showing the process pitches of the data link lines of the edge and center portions;

7A and 7B are plan views illustrating the process pitch of the data link line of the center portion;

Explanation of symbols on the main parts of the drawings

111: thin film array substrate 112: gate wiring

112a: gate electrode 113: gate insulating film

115: data wiring 115a: source electrode

115b: drain electrode 116: protective film

117: pixel electrode 125: data pad

135a, 135b, 135c, 135d: first, second, third and fourth data link lines

140: data drive IC

The present invention relates to a liquid crystal display device, in particular, to reduce the number of data drive ICs according to the pad link design, to reduce the difference in resistance between the center portion and the edge portion with respect to the length of the link line, and to facilitate the UV curing of the seal material. It relates to a liquid crystal display device suitable for.

BACKGROUND ART Liquid crystal display devices, which have recently been in the spotlight as flat panel displays, have been actively researched due to their high contrast ratio, suitable for gradation display or moving image display, and low power consumption.

In particular, it can be manufactured with a thin thickness so that it can be used as an ultra-thin display device such as a wall-mounted TV in the future, and is light in weight and consumes significantly less power than a CRT CRT. It is being used as a next generation display device.

Such a liquid crystal display generally includes a thin film array substrate having thin film transistors and pixel electrodes in each pixel region defined by gate wirings and data wirings, and a color filter having a color filter layer, a black matrix, and a common electrode. Comprising a substrate and a liquid crystal layer interposed between the two substrates, by applying a voltage to the electrode to rearrange the liquid crystal molecules of the liquid crystal layer to control the amount of light transmitted to display an image.

At this time, the color filter substrate and the thin film array substrate are bonded by a seal material such as epoxy resin, and the driving circuit on the printed circuit board (PCB) is thin film by TCP (Tape Carrier Package) method using a drive IC. Is connected to the array substrate. In the printed circuit board, a plurality of devices such as integrated circuits are formed on a substrate to generate various control signals and data signals for driving the liquid crystal display device.

Hereinafter, a liquid crystal display according to the related art will be described with reference to the accompanying drawings.

1 is a plan view of a thin film array substrate of a liquid crystal display device according to the prior art, and FIG. 2A and FIG. 2B are plan views showing a process cross section including a data link line having a one-layer structure according to the prior art and a process pitch of the data link line, 3A and 3B are plan views showing a process cross section of a data link line and a cross-sectional view of a structure including a data link line having a two-layer structure according to the prior art.

As shown in FIG. 1, the thin film array substrate 11 includes an active region in which the unit pixels P having a matrix structure are defined by the gate wiring 12 and the data wiring 15, and the gate pad 22. And a pad portion region in which a data pad 25 is formed and connected to a driving circuit on a separately manufactured printed circuit board.

In this case, the pad portion region is divided into a gate pad portion and a data pad portion, and the gate pad portion includes a gate link line 32 extending from the gate line 12 and a gate pad formed at an end of the gate link line 32. 22 is formed, and the data pad portion includes a data link line 35 extending from the data line 15 and a data pad 25 formed at an end of the data link line 35.

In detail, as illustrated in FIGS. 1 and 2B, the plurality of gate lines 12 and the data lines 15 are formed on the glass substrate 11 in the active region so that the unit pixel P is defined. Each pixel region is filled with a thin film transistor (TFT) for switching a signal at an intersection of the gate line 12 and the data line 15, and is charged until the unit pixel area is next addressed. A storage capacitor (not shown) for maintaining a state and a pixel electrode 17 connected to the drain electrode 15b of the thin film transistor TFT to form an electric field for controlling the liquid crystal director are formed. have.

In this case, a gate insulating layer 13 is further formed between the gate line 12 and the data line 15 to insulate between the two layers, and the passivation layer 16 is formed between the thin film transistor TFT and the pixel electrode 17. ) Is further formed.

The pad portion region includes a plurality of gate link lines 32 and gate pads 22 extending from the gate lines 12 to apply gate driving signals of gate drivers to the gate lines 12, and data. In order to apply a data signal of a driver to each of the data lines 15, a plurality of data link lines 35 and data pads 25 formed when the gate lines 12 are formed are formed, respectively, to external drive circuits and electrical signals. Interface.

In this case, the gate pad 22 and the data pad 25 are formed in a group of a plurality of groups at the edge of the substrate, and a gate drive IC and a data drive IC are mounted in each group by a TCP method, respectively. It receives various signals from the printed circuit board.

The number of the gate drive IC and the data drive IC varies depending on the model or size of the liquid crystal display device. FIG. 1 shows a gate pad 22 and a data pad 25 in which one gate drive IC and two data drive ICs are to be mounted. It is shown simply.

As described above, since the pad electrodes are formed in a portion where the drive IC is to be mounted, as shown in FIG. 1, the length of the data link line 35 far from the portion where the data drive IC is to be mounted becomes longer. The length of the data link line 35 near the portion where the data drive IC is to be mounted becomes shorter. As a result, the lengths of the data link lines 35 are different from each other. The same applies to the gate link line 32.

However, when the lengths of the link lines are different, the resistance values of the link lines are also different, resulting in uneven flow rates of current passing through the link lines. In other words, the longer the link line, the higher the resistance value, so that the current flows later. The shorter the link line, the lower the resistance value, the current flows faster.

Therefore, since the currents flowing in the wirings farthest from the drive IC and the wirings closest to each other are not the same, there is a problem in that the same signals are not transmitted simultaneously.

In addition, when one data link line 35 drives one pixel region in the thin film array substrate, the actual process pitch for forming the data link line should be approximately 15 μm, and the distance between the data link lines should be approximately. It is desirable to be larger than the width of the line.

However, in practice, the pitch of the data link line 35 shown in Fig. 2B is only secured by about 9 mu m.

In order to secure the pitch of the data link lines in the thin film array substrate, the data link lines were formed in a two-layer structure.

When the data link line is formed in a two-layer structure, the data link line is presented by dividing the first and second data link lines 35a and 35b. As shown in FIGS. 3A and 3B, the first data link is shown. The line 35a is formed when the gate wiring is formed, and the second data link line 35b is formed when the data wiring is formed.

As described above, when the data link lines are formed in a two-layer structure in order to secure the pitch of the data link lines in the thin film array substrate, the width of each data link line is about 6 μm, and the first and second data link lines 35a are formed. , The spacing between the lines 35b) is approximately 1.5 µm, so that the pitch of the data link lines is secured, but the UV is hardly irradiated when the seal material is subsequently UV cured due to the incomplete opening ratio between the first and second data link lines 35a and 35b. Problems may arise.

The present invention has been made to solve the above problems, and an object of the present invention is to reduce the resistance difference between the data link portion disposed in the center portion and the edge portion, and to provide a liquid crystal display device suitable for securing an opening area of the data link portion. To provide.

According to an aspect of the present invention, there is provided a liquid crystal display device including: an active region in which gate lines and data lines are intersected and a pixel region is defined; A plurality of data link lines connected to the data line outside the active area and disposed at different lengths from a center portion and an edge portion with respect to a data drive IC; A gate link line extending from the gate line and disposed in a circumference of the active region; A gate pad and a data pad disposed outside the active region to transmit signals to the gate link line and the data link line; It is characterized in that the concave portion is provided in the data link line disposed in the center portion more than the data link line disposed in the edge portion to secure a wider opening area.

The pixel areas are defined on both sides of the data line, respectively.

The data line may be configured to transmit a signal to two pixel areas positioned at both sides of the data line.

Neighboring data link lines of the data link lines are formed on the same layer as the gate line and the data line, respectively, to form a two-layer structure.

The main portion of the data link lines of the center portion and the edge portion may be configured in plural on one side or both sides.

Hereinafter, a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

4 is a plan view of a thin film array substrate of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view of a structure including a data link line having a two-layer structure according to the present invention.

6A and 6B are plan views showing the process pitches of the data link lines of the edge portion and the center portion, and FIGS. 7A and 7B are plan views illustrating the process pitches of the data link lines of the center portion.

As described above, the liquid crystal display device is divided into a color filter substrate on which a color filter layer for color realization is formed, an active region in which a switching element for changing the arrangement direction of liquid crystal molecules is formed, and a pad portion region connected to an external driving circuit. It consists of a thin film array substrate and a liquid crystal layer formed between the two substrates, the following description will be limited to the thin film array substrate having the features of the present invention.

In the thin film array substrate of the liquid crystal display according to the exemplary embodiment of the present invention, as shown in FIGS. 4 and 5, and FIGS. 6A and 6B, a plurality of gate lines 112 and data lines 115 perpendicular to each other cross each other. Active regions in which a plurality of pixels are defined, a plurality of gate link lines (not shown) extending from the gate lines 112, gate pads formed at ends thereof, and a plurality of gate lines formed at the data lines 115. The pad portion region includes data link lines and data pads 125 formed at ends thereof.

In this case, the data link lines are composed of a plurality of first, second, third, and fourth data link lines 135a, 135b, 135c, and 135d.

Specifically, in the active region, a plurality of pixel regions are defined in the active region so that the plurality of gate lines 112 and the data lines 115 intersect and the data lines 115 are commonly used. Thin film transistors (TFTs) are formed in both pixel regions where 112 and data lines 112 cross each other, and pixel electrodes 117 are formed in each pixel region. In this case, the thin film transistors formed on both sides of the data line 115 are connected to gate lines 112 having different gates.

The pair of thin film transistors formed on the neighboring data lines may be configured to be symmetrical with the thin film transistors of the neighboring pixel region.

As described above, one data line 115 is configured to drive two pixel regions on both sides of the data line. In this way, the number of data drive ICs can be reduced.

In this case, the unit thin film transistor deposits an inorganic insulating material of silicon oxide (SiOx) or silicon nitride (SiNx) on the entire surface including the gate electrode 112a branched from the gate wiring 112 and the gate electrode 112a. Formed on the gate insulating layer 113, the semiconductor layer 114 of amorphous silicon (a-Si: H) formed on the gate insulating layer 113 on the gate electrode 112a, and the data wiring ( It is composed of a laminated film of source / drain electrodes 115a and 115b branched from the 115 and formed on the semiconductor layer 114, and the drain electrode 115b penetrates through the passivation layer 116 to form the pixel electrode 117. Connected with

The gate wiring 112 and the data wiring 115 may include copper (Cu), aluminum (Al), aluminum alloy (AlNd: Aluminum Neodymium), molybdenum (Mo), chromium (Cr), titanium (Ti), and tantalum. A low-resistance metal material such as (Ta) and molybdenum-tungsten (MoW) is deposited and patterned by a sputtering method, and the pixel electrode 117 is indium tin oxide (ITO) or indium zinc oxide (IZO) on the passivation layer. It is formed by depositing and patterning a transparent conductive material such as).

In the pad region, a gate pad (not shown) for applying a gate driving signal to the gate lines 112 and a data pad 125 for applying a data signal to the data lines 112 are formed. In order to interface electrical signals with external driving circuits, the gate pads and the data pads 125 are formed in groups of a plurality of gate driver ICs (not shown) and data driver ICs 140, respectively.

In this case, the gate line 112 and the gate pad are connected by a gate link line (not shown), and the data line 112 and the data pad 125 are connected by data link lines.

The data link lines are divided into a two-layer structure, as shown in FIGS. 5 and 6A and 6B.

In this case, the data link lines may be divided into a data line 115 that is close to a data line 115 that is far from the data drive IC 140. The data link lines connected to the data line 115 far away from the data drive IC 140 are disposed at the edge portion, and the data link lines connected to the data line 115 near the data line 115 are defined at the center portion. Explain.

In other words, the data link lines of the edge portion are divided into first and second data link lines 135a and 135b, and the first data link line 135a is formed when the gate wiring 112 is formed (at the same layer). Formed), and the second data link line 135b is formed (formed on the same layer) when the data line 115 is formed.

In addition, the data link lines of the center portion are divided into third and fourth data link lines 135c and 135d, and the third data link lines 135c are formed when the gate wiring 112 is formed (formed on the same layer). And the fourth data link line 135d is formed (formed on the same layer) when the data line 115 is formed.

According to the above, of the data link lines, the first and third data link lines 135a and 135c are not shown in the drawing, but are connected to the corresponding data lines through separate connection lines, and the second and fourth data link lines 135b and 135d are directly connected to the corresponding data line.

The first, second, third, and fourth data link lines 135a, 135b, 135c, and 135d having the two-layer structure are connected to one data line 115 in a one-to-one correspondence.

The data link lines close to the data link lines connected to the data line 115 that are far away from the data drive IC 140 have different lengths. In other words, the length of the data link line arranged in the edge portion becomes longer than the length of the data link line arranged in the center portion.

As described above, when the length of the data link line disposed at the edge portion is longer than the length of the data link lines connected to the center portion, the resistance of the data link line disposed at the edge portion relative to the center portion is increased, so that the data portion is disposed at the center portion and the edge portion. The speed of the current flowing through the data link line will vary.

In the present invention, the data link lines are formed in a two-layer structure to secure a process pitch, and at the same time to match the current speed according to the resistance difference between the data link lines of the edge and center portions, the data link lines located at the edge and center portions. The number of main parts of the was adjusted (by varying the line width and its area).

In general, each of the first, second, third, and fourth data link lines 135a, 135b, 135c, and 135d formed in the center portion and the edge portion has a plurality of irregularities therein on one side or both sides. As a result, the opening area was increased, and when the seal material was subsequently UV cured, UV irradiation could proceed without any problem.

6A and 6B, the first and second data link lines 135a and 135b disposed at the edge portion are the third and fourth data link lines 135c and 135d disposed at the center portion. In contrast, the difference in resistance was reduced by forming a smaller number of concave-convex irregularities. In this case, the first and second data link lines 135a and 135b of the edge portion may form concave portions only enough to secure an opening area to which a problem does not occur during UV curing in the future.

In addition, the third and fourth data link lines 135c and 135d disposed in the center portion may adjust a gap between the recess and each link line to secure an opening area. For example, the third and fourth data link lines 135c and 135d may be arranged as follows.

First, as shown in FIG. 7A, the third and fourth data link lines 135c and 135d may have a recessed portion of 3.0 μm, and a gap therebetween may be 1.5 μm. The maximum spacing between the third and fourth data link lines 135c and 135d is 4.5 占 퐉. In this configuration, the opening ratio is improved by approximately 40.4%.

As shown in FIG. 7B, the main portion of the third and fourth data link lines 135c and 135d may be 3.0 µm, and the interval therebetween may be 2.5 µm. The maximum spacing between the third and fourth data link lines 135c and 135d is 5.5 µm. In this configuration, the opening ratio is improved by about 45.9%.

As described above, when the number of irregularities (particularly, the uneven portions) is adjusted on the side of the data link line disposed at the center portion and the edge portion having different lengths, that is, the unevenness is inversely proportional to the length of the data link line. When formed, the resistance difference between the data link lines of the center portion and the edge portion can be reduced, and the opening area can be also secured.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill.

The liquid crystal display according to the present invention as described above has the following effects.

First, data link lines were formed in a two-layer structure to secure a process pitch.

Second, by adjusting the number of irregularities (especially concave portions) on the side of the data link lines arranged at the center portion and the edge portion having different lengths, the resistance difference between the center portion and the edge portion data link line is reduced, and the opening An area was also secured.

Claims (5)

An active region in which the gate lines and the data lines are intersected and the pixel area is defined; A plurality of data link lines connected to the data line outside the active area and disposed at different lengths from a center portion and an edge portion with respect to a data drive IC; A gate link line extending from the gate line and disposed in a circumference of the active region; A gate pad and a data pad disposed outside the active region to transmit signals to the gate link line and the data link line; And more concave portions in the data link lines arranged in the center portion than in the data link lines arranged in the edge portion to secure a wider opening area. The method of claim 1, And the pixel areas are defined on both sides of the data line, respectively. The method of claim 2, And the data line is configured to transmit signals to two pixel areas positioned at both sides of the data line. The method of claim 1, Adjacent data link lines of the data link lines are formed on the same layer as the gate line and the data line, respectively, to form a two-layer structure. The method of claim 1, And a plurality of main portions of the data link lines of the center portion and the edge portion are formed on one side or both sides thereof.

Images