KR20080092813A - Processor having indirect branch validation unit for secure program execution - Google Patents

Abstract

A central processing unit having a branch instruction validation unit for secure program execution is provided to prevent malfunction caused by computer virus by monitoring the computer virus instead of using any vaccine programs. A CPU(Central Processing Unit) includes a branch instruction validation unit(212) for verifying the validation of branch instruction, and a branch instruction execution unit(211) for executing the verified valid branch instruction, so that abnormal branch instruction caused by virus attack or computer intrusions may be verified in advance.

Description

CENTRAL PROCESSING UNIT WITH A BRANCH INSTRUCTION VERIFICATION

1 is a diagram showing the structure of a general CPU without a branch instruction verification unit.

2 is a diagram illustrating a structure of a central processing unit including a branch instruction validation unit according to the present invention.

FIG. 3 is a diagram showing a reference table composed of a combination of a current address value associated with a branch instruction currently loaded and a branch purpose address value for the branch instruction.

4 is a diagram illustrating a reference table of a branch instruction verifying unit implemented using an arrangement of a predetermined length as an embodiment of the present invention.

5 is a diagram illustrating the operation of a simple hash function having a very small calculation amount according to an embodiment of the present invention.

FIG. 6 illustrates another method for mixing the current address value associated with the branch instruction in accordance with one embodiment of the present invention.

FIG. 7 is a diagram illustrating an operation of a H3 type hash function using element values of a matrix according to an embodiment of the present invention.

8 is a diagram illustrating a structure of a branch instruction verifying unit implemented by connecting two arrays in series according to the present invention.

9 is a diagram illustrating a structure of a branch instruction verifying unit verifying a branch instruction through sequential calculation using a hash function of the H3 method according to the present invention.

10 is a diagram illustrating a structure of a central processing unit further including a branch predicting unit and a branch calculating unit according to the present invention.

11 is a flowchart illustrating a step-by-step method of executing a branch instruction of a central processing unit including verifying whether a branch instruction is valid.

12 is a flowchart illustrating a step-by-step method of executing a branch instruction for verifying that the branch instruction is valid only when the predicted branch purpose address and the calculated branch instruction address for a particular branch instruction do not have the same value.

13 is a flowchart illustrating a step-by-step method of executing a branch instruction including verifying whether a branch instruction is valid using a reference table.

14 is a flow diagram illustrating a step by step method of executing a branch instruction comprising verifying whether a branch instruction is valid using a hash function.

The present invention relates to a technology for preventing malfunction of information processing devices such as computers, PDAs, mobile phones, etc. due to computer viruses, and more particularly, when the central processing unit embedded in the information processing device executes a computer program command. It relates to a method and apparatus for verifying whether the command is a normal command by a computer virus or a hack or a normal command.

According to the conventional computer virus protection technology, a sample of a computer virus that has been generated is collected to extract a constant character string characteristic of the computer virus, and the computer virus is infected by using whether the string exists in a file of a specific computer or the like. It was judged whether or not.

Therefore, when a new computer virus is generated, an antivirus program corresponding to the computer virus should be developed by identifying the identity of the new computer virus, extracting a character string, and the information of the computer virus in the existing vaccine program. Before the addition, it was impossible to prepare for the new computer virus, so that damage to the new computer virus could not be prevented. In addition, as the type of computer virus increases, the type of the character string is increased proportionally, and the time required for the process of checking whether the character string is present is inevitably increased.

When a computer is attacked by a hacker for a control flow, the hacker uses a vulnerability in the computer to inject code that executes his program at a specific address. The attacked computer branches to the address where the command to start the hacker's program is executed by the code while executing the general program, and operates by the hacker's intention, unlike the user's intention, by executing the hacker's program. .

In the related art, when a vulnerability of a computer is disclosed due to a hacker attack, a program maker can only stop a hacker's attack by using a patch program that fixes the vulnerability. There was no obvious solution to other attacks.

The present invention has been made to improve the prior art as described above, and an object of the present invention is to provide a method and apparatus for preventing a malfunction caused by the computer virus, not by a vaccine program for monitoring and treating a computer virus.

Another object of the present invention is to provide a method and apparatus for preventing a computer attacked by a hacker from executing a program inserted by the hacker.

In order to achieve the above object, and to solve the problems of the prior art, the central processing unit according to one aspect of the present invention is a branch instruction verification unit for verifying that the branch instruction is valid, and when the branch instruction is verified to be valid, And a branch instruction execution unit for executing the branch instruction.

A central processing unit according to another aspect of the present invention includes a look-up table composed of a combination of address values of at least one or more branch instructions and branch destination address values for the branch instruction, the current address value associated with the particular branch instruction and the If the combination of the branch purpose address values for the branch instruction does not exist in the reference table, the branch instruction is regarded as an invalid branch instruction, and the branch instruction is not executed.

According to another aspect of the present invention, a central processing unit includes an array having a predetermined length and inputs a combination of an address value of a branch instruction stored in a program counter and a branch purpose address value for the branch instruction into at least one hash function. Generate at least one address value of the array, and determine whether the branch instruction is valid based on a value of the array stored at the at least one address, and if the branch instruction is invalid, The branch instruction is not executed.

According to still another aspect of the present invention, there is provided a method of executing a branch instruction, wherein the branch instruction verifies that the branch instruction is valid and verifies that the branch instruction is invalid in the method of executing the branch instruction. It characterized in that it comprises a step of not executing.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings and the contents described in the accompanying drawings, but the present invention is not limited or limited to the embodiments. Like reference numerals in the drawings denote like elements.

In the present invention, the central processing unit is a device that executes a predetermined command according to a predetermined algorithm, and may be interpreted as including all devices that perform similar functions such as a CPU, a processor, and a controller.

1 is a diagram showing the structure of a general CPU without a branch instruction verification unit. Hereinafter, a command execution process of a general CPU will be described with reference to FIG. 1. The central processing unit 110 executes a program configured to calculate a result desired by a user. The program created by the programmer is converted into machine code that can be executed by the central processing unit through a compilation process and stored in the external memory device 120. According to an embodiment of the present invention, the compiled program may be stored separately from the data area 121 and the code area 122 as shown in FIG. 1, and the data area 121 and the code area 122 may be separated from each other. Can be mixed and stored.

The central processing unit 110 loads the instructions stored in the code area 122 of the storage device 120. The current address value associated with the loaded instruction is stored in a program counter. The instructions are stored in the form of machine code. The central processing unit 110 executes the loaded machine code in the branch instruction execution unit 111. If the loaded instruction is a general instruction, not a branch instruction, the central processing unit 110 increases the value of the program counter in which the current address associated with the currently loaded instruction is stored so as to point to the address where the next instruction is stored. The central processing unit sequentially loads instructions stored at the next address and performs a predetermined task.

If the loaded instruction is a branch instruction requesting to execute an instruction of a specific address position, the CPU 110 stores the specific address in a program counter, loads the instruction stored at the specific address, and then loads the branch instruction. The execution unit 111 executes. Here, the address of the storage unit in which the instruction, which is the target of the branch instruction, is stored, is called the "branch destination address".

If the loaded command is a command for deciding whether or not to branch according to the value of a specific variable or a command whose value of a target address to branch is changed according to the value of a specific variable, the value of the specific variable is reviewed and the result is determined. Therefore, the value of the branch destination address in which the next instruction is stored is stored in the program counter.

The CPU 110 may store a result value executed by the branch instruction execution unit 111 in the data area 121.

A computer virus, or a hacker, uses a vulnerability of the computer to manipulate a value of a specific variable for deciding whether to branch or to manipulate a value of a branch destination address, thereby executing an instruction stored at a branch destination address by a normal program execution procedure. Instead, a computer virus or hacker inserts an instruction into a stored address.

Therefore, in the case of the general instruction that sequentially executes the instruction stored at the next address next to the stored address, it is not necessary to verify the instruction. However, the instruction that is not adjacent to the currently loaded instruction is loaded. In the case of a branch instruction to be executed, it is possible to verify whether the branch instruction is a valid instruction to prevent damage by a computer virus or a hacker.

2 is a diagram showing the structure of a central processing unit including a branch instruction verification unit according to the present invention. Hereinafter, the structure of the CPU including the branch instruction verification unit will be described with reference to FIG. 2.

Outside the central processing unit 210, there is an external storage device 220 that includes a code area 222 in which instructions are stored and a data area 221 in which data for executing a program is stored.

The central processing unit 210 loads an instruction in the code area 222 of the external storage device 220. If the loaded instruction is a branch instruction, the branch instruction verification unit 212 determines whether the branch instruction is a valid instruction. Verify.

If the branch instruction verifier 212 verifies that the branch instruction is a valid instruction, the branch instruction verifier 212 transmits a branch instruction valid signal indicating that the branch instruction is valid, to the branch instruction execution section 211. The branch instruction execution unit 211 receiving the branch instruction valid signal executes the branch instruction. If the branch instruction valid signal is not received or the branch instruction execution unit 211 which receives a signal of an invalid branch instruction does not perform the branch instruction.

According to an embodiment of the present invention, when the branch instruction verification unit 212 verifies the branch instruction as an invalid instruction, the branch instruction execution unit 211 determines that an error has occurred with respect to the branch instruction, or the user. You can report an error.

According to an embodiment of the present invention, the branch instruction valid signal indicating that the branch instruction is valid may be '1', and the branch instruction valid signal of an invalid branch instruction may indicate '0'.

FIG. 3 is a diagram showing a reference table composed of a combination of a current address value associated with a branch instruction currently loaded and a branch purpose address value for the branch instruction. Hereinafter, the verification process of the branch instruction will be described with reference to FIG. 3.

As an example, the lookup table of FIG. 3 may be stored in a memory embedded in the central processing unit.

If the central processing unit executes a branch instruction, a branch destination address is stored which stores the current address value of the external storage device in which the branch instruction is stored and the next instruction to be executed by the branch instruction.

Since the execution of a program is usually performed by repeating a specific routine or branching to some possible branch destination address depending on the value of a specific variable, a combination of the two addresses has a finite number.

For example, a specific branch instruction to be executed branches to the first address if the value of the specific variable 'A' is greater than '0' and to the second address if the value of the 'A' is less than '0'. Assume that the instruction is a branch instruction that executes an instruction stored at the second address.

The CPU may only branch to the first address or branch to the second address according to the value of the specific variable 'A' during the execution of the specific branching command. If the current address associated with the branch instruction is the same as the address value in which the specific branch instruction of the external storage device is stored, and the value of the branch destination address for the branch instruction points to the third address, the branch instruction is a normal branch instruction. And can't see. Therefore, in this case, the branch instruction verification section sends a branch instruction valid signal to the branch instruction execution section that the branch instruction is a branch instruction which is not valid.

In the reference table of FIG. 3, a first branch destination address 311, a second branch destination address 312, and a third branch destination address 313 for the branch instruction are associated with a current address value associated with the first branch instruction. Is stored.

In addition, in relation to a current address value associated with a second branch instruction, a first branch target address 321, a second branch target address 322, and a third branch target address 323 for the branch instruction are stored. .

In addition, in relation to a current address value associated with a third branch instruction, a first branch purpose address 331, a second branch purpose address 332, and a third branch purpose address 333 for the branch instruction are stored. .

If a current address value associated with the first branch instruction is stored in the program counter, the branch target address obtained as a result of the execution of the branch instruction is the first, second, and third branch target addresses 311 for the first branch instruction. , 312, 313 may verify that the branch instruction is a normal branch instruction. However, if the branch purpose address obtained as a result of the execution of the branch instruction is a fourth branch purpose address instead of the first, second, and third branch purpose addresses 311, 312, and 313, the branch instruction may be subjected to a computer virus or a hack. Can be determined to be an invalid branch instruction.

Therefore, the branch instruction verifier uses a look-up table that includes all possible combinations of the current address value in which the normal branch instruction is stored and the branch destination address in which the next instruction to be executed by the normal branch instruction is stored. If a combination of the current address value in which the branch instruction is stored and the destination address value for the branch instruction is present in the reference table, the branch instruction verifies as a valid branch instruction, and branches a valid instruction for branch instruction indicating that the branch instruction is a valid branch instruction. Send it to the execution unit. If a combination of the current address value in which a specific branch instruction is stored and the destination address value for the branch instruction does not exist in the reference table, the branch instruction is verified as an invalid branch instruction, and the specific branch instruction is invalid. A branch instruction valid signal called a non-command is transmitted to the branch instruction execution unit.

According to an embodiment of the present invention, a central processing unit of an information processing device such as a computer, a PDA, a cellular phone, and the like has a reference table composed of a combination of an address value of a branch instruction to be verified and a branch destination address value for the branch instruction. . According to one embodiment of the invention, the reference table is stored in a memory portion of the central processing unit.

The branch instruction is invalid if the combination of the address value of the branch instruction stored in the program counter and the branch destination address value for the branch instruction does not exist in the reference table to verify whether a specific branch instruction is valid. Verify by command If the branch instruction is invalid, the central processing unit may not execute the branch instruction.

According to an embodiment of the present invention, the branch instruction verifying unit may further include a current address value in which the branch instruction is stored and a value of a branch destination address for the branch instruction in order to perform the verification operation more strictly. Rather, the history of past branch instructions performed by the central processing unit can be further considered. The branch instruction verifying unit includes a reference table including a combination of a current address value in which the branch instruction is stored, a value of a branch destination address for the branch instruction, and a value of an address in which a branch instruction performed before the branch instruction is stored. And the branch instruction is normal only when a combination of an address value stored in the branch instruction, a branch purpose address value for the branch instruction, and a value of an address in which the branch instruction performed before the branch instruction is stored in the reference table. You can verify that it is a branch instruction. If it does not exist in the reference table, it can be verified as an abnormal branch instruction.

According to another embodiment of the present invention, the branch instruction verifying section is configured such that the central processing unit actually executes the past branch destination address calculated by the branch calculating section for the branch instruction before the branch instruction, and the branch instruction before the branch instruction. It is possible to verify whether the branch instruction is valid by further considering the branching destination address. The branching destination address actually branched by the central processing unit is stored in the branch history shift register inside the central processing unit. The branch instruction verifying section stored in the branch history shift register, the branching destination address actually branched in the past, and the branching instruction section of the past are stored in the past. By comparing the branch destination addresses calculated for the branch instructions with each other, the branch instructions can be verified as invalid branch instructions if they do not match. The branch instruction verifier verifies the branch instruction in consideration of whether the branch purpose address calculated for several branch instructions immediately before the branch instruction matches the branch purpose address branched as well as the branch instruction immediately before the branch instruction. Can be.

According to another embodiment of the present invention, the branch instruction verifying unit may further include: a current address value in which the branch instruction is stored, and a value of a branch destination address for the branch instruction, in order to perform the verification operation more strictly. In addition, the past command execution history performed by the CPU may be further considered. The branch instruction verifying unit includes a reference table including a combination of a current address value in which the branch instruction is stored, a value of a branch destination address for the branch instruction, and a value of an address in which the instruction executed before the branch instruction is stored. The branch instruction is a normal branch instruction only when a combination of an address value stored in the branch instruction, a branch purpose address value for the branch instruction, and a value of an address in which the instruction executed before the branch instruction is stored in the reference table. Can be verified as If it does not exist in the reference table, it can be verified as an abnormal branch instruction.

4 is a diagram illustrating a reference table of a branch instruction verifying unit implemented using an arrangement of a predetermined length as an embodiment of the present invention. Hereinafter, the branch instruction verification process will be described with reference to FIG. 4.

The computer is a general-purpose information processing apparatus, and since the central processing unit processes a large number of instructions, the reference table of the branch instruction verification unit for verifying the branch instruction occupies a very large capacity.

If the capacity of the lookup table is too large, it takes a long time to determine whether a combination of the value of the current address associated with a particular branch instruction and the branch destination address value for the branch instruction is in the lookup table, which degrades the performance of the central processing unit. do. In addition, it occupies a large area in the central processing unit, making it difficult to design the central processing unit.

According to an embodiment of the present invention, the reference table may be implemented using a bloom filter. Bloom filters are a type of data structure that can be used to check which set a given element belongs to. The bloom filter is composed of an array of preset lengths, and reads the values of the arrays of the preset lengths using a predetermined hash function to check whether a given element belongs to the set. .

The BLUM filter can check whether an infinite number of elements belong to a specific set, but an error may occur when the number of elements increases by more than a certain number, and as the number of elements increases, the possibility of occurrence of the error may increase. Increases.

The hash function is a function that receives arbitrary data and generates a hash value. If the hash values are different, the input data must have different characteristics. Even if only one bit of the input data is changed, the hash value, which is the output of the hash function, is greatly changed.

In one embodiment of the present invention, the branch instruction verifier has an array 430 of a preset length, and the branch instruction verifier has a branch instruction to be verified in at least one or more hash functions 421, 422, and 423. A combination 410 of the associated current address value and the branch destination address value for the branch instruction is input to generate at least one address value of the array of preset lengths. The branch instruction verification unit may determine whether the branch instruction is valid based on the values 431, 432, and 433 of the array of the preset length in the at least one address value.

A combination of the current address value associated with the branch instruction to be verified and the branch destination address value for the branch instruction is simply referred to as 'B' 410.

The hash functions 421, 422, and 423 receive the 'B' value and generate address values of the array having the preset length. In the embodiment of the figure, a bloom filter is shown in which three hash functions 421, 422, and 423 are used.

The branch instruction verifier determines whether the branch instruction is valid based on the array values 431, 432, and 433 stored in the address values of the array having the preset length.

According to an embodiment of the present invention, if all the values stored in the generated addresses of the preset length array are the same, the branch instruction verification unit verifies that the branch instruction is a valid branch instruction. In the embodiment shown in the figure, since the values of the arrays stored in the three addresses generated by the three hash functions are all equal to 1, the branch instruction is verified as a valid branch instruction.

According to an embodiment of the present invention, the CPU may execute a program to be executed for a predetermined time, and determine a value to be stored in the array by examining a combination of branch instructions performed by the program.

If the values of the arrays stored in the addresses of the arrays generated by the at least one hash function 421, 422, or 423 are not equal to each other, the branch instruction verification unit may verify that the branch instruction is invalid.

According to an embodiment of the present invention, a central processing unit of an information processing device such as a computer PDA, a mobile phone, etc. has an arrangement of a predetermined length. In order to verify whether a specific branch instruction is valid, a combination of an address value of the specific branch instruction stored in a program counter and a branch destination address value for the branch instruction is input to at least one hash function to arrange the preset length. Generate at least one address value of.

The CPU reads the values of the array of the preset length stored in the at least one address and compares the values.

According to an embodiment of the present invention, if all values of the array are the same, the branch instruction may be verified as valid. If the branch instructions are valid when the values of the array are all '1', it is possible to verify whether the branch instructions are valid by performing AND operation on the values of the array.

Since the hash function has a tricky property, it is not easy to implement it, and the time required for the calculation process causes the performance of the central processing unit to be degraded. This is very important for implementing branch instruction verification.

5 is a diagram illustrating the operation of a simple hash function having a very small calculation amount according to an embodiment of the present invention. Hereinafter, the operation of a simple hash function will be described with reference to FIG. 5.

The simple hash function shuffles the bit order of the current address 510 associated with the branch instruction, and performs an exclusive OR operation with the branch destination address value 520 for the branch instruction. Generates an address value 530 of an array of set length.

In the present invention, "shuffle" reverses the order of a specific array by a predetermined method. The array before the shuffled and the array after shuffled only change the order of the data stored in the array, but the data value does not change. .

In the embodiment illustrated in FIG. 5, the address values 510, 520, and 530 have a length of 4 bytes, assuming a general 32-bit CPU. In the present embodiment, the addresses are shuffled on the basis of 8-bit bytes, but it is also possible to shuffle the addresses on a bit-by-bit basis. The first, second, third, and fourth bytes 511, 512, 513, 514 of the current address value 510 associated with the branch instruction to verify are respectively the first, third, and second of the branch destination address value 520 for the branch instruction. And perform the exclusive AND operation with the fourth (521, 523, 522, 524) bytes to generate the first, third, second, and fourth (531, 533, 532, 534) bytes of the address of the array of the preset length, respectively. .

6 is a diagram illustrating another method for a simple hash function to shuffle the current address value associated with the branch instruction according to another embodiment of the present invention. Hereinafter, the operation of a simple hash function will be described with reference to FIG. 6.

The hash function shown in FIG. 6A has the first, second, third, and fourth bytes of the current address value 610 associated with the branch instruction to be verified, respectively. Second, an exclusive AND operation is performed on the third byte to generate fourth, first, second, and third bytes of the address of the array having the preset length, respectively.

The hash function shown in b of FIG. 6 includes the first, second, third, and fourth bytes of the current address value 630 associated with the branch instruction to be verified, respectively, in the second, third, and third branch destination address values 640 for the branch instruction. Fourth, an exclusive AND operation is performed on the first byte to generate second, third, fourth, and first bytes of addresses of the array having the preset length, respectively.

The hash function shown in FIG. 6C has the first, second, third, and fourth bytes of the current address value 650 associated with the branch instruction to verify, respectively, the first, fourth, and third of the branch destination address value 660 for the branch instruction. Third, an exclusive AND operation is performed on the second byte to generate first, fourth, third, and second bytes of the address of the array having the preset length.

The hash function shown in d of FIG. 6 includes the first, second, third, and fourth bytes of the current address value 670 associated with the branch instruction to be verified, respectively, the third, second, and third of the branch destination address value 680 for the branch instruction. First, an exclusive AND operation is performed on the fourth byte to generate third, second, first, and fourth bytes of the address of the array having the preset length, respectively.

In one embodiment of the present invention, the hash function used in the branch instruction verification unit is a Secure Hash Algorithm (SHA) -1 algorithm, a Message-Digest algorithm 5 (MD5) algorithm, a keyed-Hash Message Authentication Code (HMAC) algorithm. , And a hash function using at least one of the Advanced Encryption Standard (AES) standard.

SHA-1 is an algorithm defined within the secure hash standard (SHS) developed by the US NIST. SHA-1 is a revision of SHA, published in 1994, that corrects the defects remaining in SHA and is considered to be a very good hash function in terms of cryptography. This hash function produces a short message that is 160 bits long and 160 bits long. The SHA-1 is a conventionally well known function, and a detailed description thereof will be omitted.

The Advanced Encryption Standard (AES), also known as 'Rijndael', is a block cipher format designated as the US government standard. It replaces the former Data Encryption Standard (DES), and the National Institute of Standards and Technology (NIST) was published after five years of standardization. 128, 160, 190, 224, and 256 bits are available for the block size, and 128 bits are recognized as a US standard. Since the AES is a conventionally well known function, a detailed description thereof will be omitted.

The use of good hash functions such as SHA-1, MD5, HMAC, and AES reduces the likelihood of error in the use of the bloom filter.

FIG. 7 is a diagram illustrating an operation of a H3 type hash function using element values of a matrix according to an embodiment of the present invention. Hereinafter, the operation of the H3 type hash function will be described with reference to FIG. 7.

The hash function has a matrix 730 composed of a predetermined bit pattern. The hash function receives a combination 710 of a current address value associated with a branch instruction to verify and a branch destination address for the branch instruction. Perform an AND operation (751, 752, 753, 761, 762, 763) on each component of a specific column of the matrix 730 corresponding to the combination, and perform an exclusive AND operation on the plurality of values of the AND operation 754. 764) to configure a specific bit of the address 720 of the array of the preset length.

The combination 710 of the current address value associated with the branch instruction to verify and the branch destination address for the branch instruction has a length of i bits and is the address value 720 of the array of the preset length that is the output of the hash function. Has a length of j bits. Matrix 730 composed of a predetermined bit pattern has a dimension of i x j.

If the input of the i bit of the hash function is X, the input bit performs an operation with the first column of the matrix composed of the predetermined bit pattern to form the first bit of the output value of the hash function.

The first bit 711 of the input X of the i bits performs an AND operation 751 with the element 731 of the first row of the first column of the matrix 730 composed of the predetermined bit pattern.

The second bit 712 of the input X of the i bits performs an AND operation 752 with the element 732 of the second row of the first column of the matrix 730 composed of the predetermined bit pattern.

The last bit 713 of the i bits of input X performs an AND operation 753 with the elements 733 of the last row of the first column of the matrix 730 composed of the predetermined bit pattern.

The result of performing the AND operation is an exclusive-OR operation 754, and the result is the first bit 721 of the output of the j-bit hash function.

The first bit 711 of the input X of the i bits performs an AND operation 761 with the element 741 of the first row of the second column of the matrix 730 composed of the predetermined bit pattern.

A second bit 712 of the input X of the i bits performs an AND operation 742 with the element 742 of the second row of the second column of the matrix 730 composed of the predetermined bit pattern.

The last bit 713 of the input X of the i bits performs an AND operation 743 with the element 743 of the last row of the second column of the matrix 730 composed of the predetermined bit pattern.

The result of performing the AND operation is an exclusive-OR operation 764, and the result is the second bit 722 of the output of the j-bit hash function.

If the above process is performed until the values of all the bits constituting the output 720 of the j-bit hash function are obtained, an address value of the array having the predetermined length is obtained using a matrix composed of the predetermined bit pattern. Can be.

As described with reference to FIG. 7, the H3 hash function according to the present invention includes a matrix 730 having a predetermined bit pattern, and performs a predetermined logical operation with input of the matrix and the hash function. This function creates the address of a matrix of a set length.

A matrix 730 composed of a predetermined bit pattern, and a logical product (751, 752, 753, 761, 762, 763) of the matrix and the input of the hash function, an exclusive-OR operation 754 According to the method of obtaining the output of the hash function according to 764, a function of generating a different address for the same input may be implemented only by changing a value of a matrix composed of the predetermined bit pattern.

8 is a diagram illustrating a structure of a branch instruction verifying unit implemented by connecting two arrays in series according to the present invention. Hereinafter, the branch instruction verification process will be described with reference to FIG. 8.

The branch instruction verifier includes an array of a preset length consisting of two arrays 830 and 831, several hash functions 820, 821, 822, 823, 824, 825, 826, and 827, and an array of the preset length. The determination unit 840 determines whether the branch instruction to be verified is a normal branch instruction based on the value stored in the. The several hash functions 820, 821, 822, 823, 824, 825, 826, and 827 may use the simple hash function, a hash function of SHA or AES, and a hash function of H3.

In other words, the several hash functions are distinguished by groups as many as the number of arrays 830 and 831 constituting the preset length array. In the embodiment of FIG. 8, since two arrays constitute the array having the preset length, the hash function may be classified into two groups. The first group 820, 821, 822, 823 of the hash function does not generate an address for the entire array, but only a lower address for array 1, and the second group 824, 825, of the hash function. 826 and 827 generate only the lower address for array 2.

8 illustrates an embodiment in which the array of preset lengths of the branch command verifying unit is composed of two arrays, but the branch command verifying unit according to another embodiment of the present invention uses the array of preset lengths as N arrays. The branch instruction can be verified by classifying several hash functions into groups of N.

A combination 810 of the current address value associated with the branch instruction to verify and the branch destination address value for the branch instruction is input to the respective hash functions 820, 821, 822, 823, 824, 825, 826, 827. .

The hash functions 820, 821, 822, and 823 belonging to the first group generate the address values of the first array 830, and the hash functions 824, 825, 826, and 827 belonging to the second group are generated by the first group. The address values of the two arrays 831 are generated. If the values of the array of the preset length stored in the address values of the first and second arrays are all the same, the branch instruction to be verified may be verified as a valid instruction.

According to an embodiment of the present invention, the value of the preset length array stored in the address values of the first and second arrays generated by the hash functions 820, 821, 822, 823, 824, 825, 826, and 827. If all of 1's are equal to the output of the hash function, the AND operation 840 may be performed to easily determine whether the branch instruction exists in the array having the preset length.

9 is a diagram illustrating a structure of a branch instruction verifying unit verifying a branch instruction through sequential calculation using a hash function of the H3 method according to the present invention. Hereinafter, the branch instruction verification process will be described with reference to FIG. 9.

A combination 910 of the current address value associated with the branch instruction to verify and the branch destination address value for the branch instruction is input to the respective hash functions 921, 922, 923, 924.

Since each of the hash functions 921, 922, 923, and 924 is an H3 scheme, each of the hash functions 921, 922, 923, and 924 includes a Q00, Q10, Q20, and Q30 matrix 931, which consists of a predetermined bit pattern. 932, 933, 934.

Each hash function 921, 922, 923, 924 comprises a Q00, Q10, Q20, Q30 matrix 931, 932, 933, 934 consisting of the predetermined bit pattern and a current address value associated with the branch instruction to be verified and The combination 910 of branch destination address values for the branch instruction is used to generate an address of the array 950 of the preset length.

AND all the values of the array of the predetermined length at the address generated by the hash functions 921, 922, 923, and 924 to AND operation 960, and store the result in the buffer 970. Save it.

The hash function 921, 922, 923, 924 replaces the matrix of the predetermined bit pattern with Q01, Q11, Q21, Q31 (941, 942, 943, 944) and the current address associated with the branch instruction to be verified again. The address value of the array having the preset length is again generated by using a combination 910 of a value and a branch purpose address value for the branch instruction.

An AND operation 960 is performed on all values of an array of a predetermined length at an address generated by the hash functions 921, 922, 923, and 924, and the result is returned to the result stored in the buffer 970. Perform an AND operation.

If the hash function (921, 922, 923, 924) using the Q00, Q10, Q20, Q30 matrix (931, 932, 933, 934) and the Q01, Q11, Q21, Q31 matrix (941, 942, 943, 944) If the values of the array of the predetermined length at the addresses generated by the hash functions 921, 922, 923, and 924 used are all equal to 1, the result of performing the AND operation is 1. Therefore, if the result of the AND operation is 1, the branch instruction can be verified as a valid branch instruction.

Verifying that the branch instruction is valid by calculating twice in succession using four hash functions, instead of calculating it at once using eight hash functions, verifying the branch instruction within a central processing unit. The area occupied by the addition can be reduced, which is useful when it is not sensitive to the time taken to verify the branch instruction. According to an embodiment of the present invention, two hash functions may be used to repeat the calculation four times to determine whether the branch instruction is a valid branch instruction.

10 is a diagram illustrating a structure of a central processing unit further including a branch predicting unit and a branch calculating unit according to the present invention. Hereinafter, the branch instruction verification process will be described with reference to FIG. 10.

The external memory device 1020 external to the CPU 1010 is divided into a data area 1021 and a code area 1022 to store a program to be executed by the CPU 1010.

In general, the time required for data exchange between the central processing unit and the external storage device is usually much longer than the time required for data exchange inside the central processing unit. Execution result The branch predictor 1013 predicts the branch destination address to be branched.

Based on the predicted result, the branch instruction execution unit 1011 preloads the instruction stored in the branch destination address of the external storage device 1020 and executes the preloaded instruction.

The branch calculating unit 1014 accurately calculates the value of the branch object address by actually examining the value of the specific variable when the branch instruction is determined whether to branch or not by the value of the specific variable, or when the value of the branch object address is changed. .

If the value of the branch object address predicted by the branch predictor 1013 and the value of the branch object address calculated by the branch calculator 1014 are not the same, the branch instruction execution unit 1011 loads and executes the preload. The execution result of one instruction is discarded, and the instruction stored in the branch target address calculated by the branch calculating unit 1014 is reloaded and executed.

If the value of the branch destination address predicted by the branch predicting unit 1013 and the value of the branch object address calculated by the branch calculating unit 1014 are the same, the branch instruction execution unit 1011 executes the instruction previously loaded and executed. By storing the execution result of the, to improve the execution speed of the program.

The branch predictor 1013 predicts a branch destination address for the branch instruction by using a static or dynamic prediction technique. Since the branch destination address predicted by the branch predictor 1013 has not been invaded by a computer virus or a hacker, the combination of the current address value associated with the branch instruction and the branch destination address value predicted by the branch predictor 1013 is the prediction. The branch object address value thus obtained is one of valid combinations regardless of whether or not the branch object address value coincides with the branch object address calculated by the branch calculating unit 1014.

Therefore, the combination of the branch instruction to be verified and the branch destination address value predicted by the branch predicting unit 1013 is always a combination present in the reference table of the branch instruction verifying unit 1012, and the branch instruction is a valid branch instruction.

However, if the value of a specific variable that determines the value of the branch destination address for the branch instruction is infected by a computer virus or a hacker intrudes, the value of the branch destination address predicted by the branch instruction predictor 1013 and the branch calculation unit The branch destination addresses calculated at 1014 are different from each other.

Of course, if the branch predictor 1013 incorrectly predicts the branch object address, the value of the branch object address predicted by the branch predictor 1013 and the branch object address calculated by the branch calculator 1014 may not be the same. .

However, the branch destination address calculated by the branch calculation unit 1014 may have been manipulated by a computer virus or a hacker to determine a specific variable value that determines the branch destination address. The branch destination address may be changed by the branch prediction unit 1013. If the same as the predicted branch destination address, the combination of the current address associated with the branch instruction to be verified and the branch destination address value calculated by the branch calculating unit 1014 is a combination present in the reference table of the branch instruction verifying unit, and the branch instruction is valid. We can see that it is a branch instruction.

Although validating the branch instruction allows the central processing unit to operate safely, the processing time of the central processing unit is degraded due to the time required to verify the validity of the branch instruction. If the value of the branch object address predicted by the branch predictor and the value of the branch object address calculated by the branch calculator are equal to each other, it is assumed that the branch instruction is valid and the branch instruction verifier does not operate. If the branch instruction verifier verifies whether the instruction is valid, the instruction execution performance of the central processing unit can be greatly improved.

11 is a flowchart illustrating a step-by-step method of executing a branch instruction of a central processing unit including verifying whether a branch instruction is valid. Hereinafter, a branch instruction execution method of the CPU will be described with reference to FIG. 11.

In step S1110, the central processing unit loads the specific branch instruction stored in the external storage device to execute the specific branch instruction. At this time, the address value of the specific branch instruction is stored in the program counter of the central processing unit. The central processing unit verifies whether the loaded specific branch instruction is valid in step S1120, and executes the branch instruction in step S1130 when it is verified that it is a valid branch instruction.

If it is verified that the branch instruction is invalid, step 1140 determines that the program to be executed by the central processing unit is a program infected with a computer virus or hacked by a hacker and stops executing the program.

According to an embodiment of the present invention, when the branch instruction is verified as an invalid branch instruction in step S1120, it is determined that an error occurs in the branch instruction in step S1140, or an error occurrence report is reported to the user. Can be.

12 is a flowchart illustrating a step-by-step method of executing a branch instruction for verifying that the branch instruction is valid only when the predicted branch purpose address and the calculated branch instruction address for a particular branch instruction do not have the same value. Hereinafter, a branch instruction execution method will be described with reference to FIG. 12.

In step S1210, the central processing unit loads the specific branch instruction stored in the external storage device to execute the specific branch instruction. At this time, the address value of the specific branch instruction is stored in the program counter of the central processing unit.

The central processing unit predicts a branch destination address for the loaded branch instruction in step S1220, and calculates a branch destination address for the loaded branch instruction in step S1230.

Since the estimated branch destination address takes into account past branch history and the like, and the calculated branch destination address takes into account specific variable values for determining the branch destination address of the branch instruction, the calculated branch destination address is an incorrect value. The predicted branch destination address is correct. However, since the specific variable value that determines the branch destination address may be a value manipulated by a computer virus or a hacker, the calculated branch destination address is a totally wrong address that is irrelevant to the branch command to be verified. It can be done. On the other hand, since the predicted branch destination address is one of several branch destination addresses selectable by the branch instruction to be verified, there is no need to doubt the influence of a computer virus or a hacker.

In step S1240, the central processing unit determines whether the predicted branch destination address and the calculated branch destination address are the same. If the same, the branch instruction can be determined to be a valid branch instruction unaffected by a computer virus or a hacker, and executes the branch instruction in step S1250.

If the predicted branch destination address and the calculated branch destination address are not the same, it is verified in step S1260 whether the branch instruction is valid. If the branch instruction is verified to be valid, the branch instruction is executed in step S1250, and if the branch instruction is verified to be invalid, execution of a program for executing the branch instruction in step S1270 is stopped. Can be.

13 is a flowchart illustrating a step-by-step method of executing a branch instruction including verifying whether a branch instruction is valid using a reference table. Hereinafter, a branch instruction execution method will be described in detail with reference to FIG. 13.

In step S1310, the central processing unit of the information processing device such as a computer, PDA, mobile phone, etc., loads the specific branch instruction stored in the external storage device to execute the specific branch instruction. At this time, the address value of the specific branch instruction is stored in the program counter of the central processing unit.

In step S1320, the CPU calculates a branch destination address for the loaded branch instruction in consideration of the branch condition of the branch instruction.

In step S1330, the central processing unit includes a current table associated with the loaded branch instruction in a look-up table composed of a combination of a current address value associated with at least one branch instruction and a branch destination address value for the at least one branch instruction. It is determined whether a combination of the address value and the calculated destination address exists.

If a combination of the current address value and the calculated destination address value associated with the loaded branch instruction exists in the reference table, the branch instruction is verified as a valid branch instruction at step S1340, and the branch at step S1350. Run the command.

If the combination of the current address value and the calculated destination address value associated with the loaded branch instruction does not exist in the reference table, the branch instruction is verified as an invalid branch instruction in step S1360, and the step ( In step S1370, the execution of the program for executing the branch instruction is stopped.

14 is a flow diagram illustrating a step by step method of executing a branch instruction comprising verifying whether a branch instruction is valid using a hash function. Hereinafter, a branch instruction execution method will be described in detail with reference to FIG. 14.

In step S1410, the central processing unit of the information processing device such as a computer, PDA, mobile phone, etc., loads the specific branch instruction stored in the external storage device to execute the specific branch instruction. At this time, the address value of the specific branch instruction is stored in the program counter of the central processing unit.

In step S1420, the central processing unit calculates a branch destination address for the loaded branch instruction in consideration of the branch condition of the branch instruction.

In step S1430, a combination of a current address value associated with the branch instruction and a branch destination address value for the branch instruction is input to at least one hash function.

In step S1440, the at least one hash function generates at least one address value of an array of a predetermined length. The hash function may be to shuffle the address value of the branch instruction, perform an exclusive OR operation on the branch target address value with respect to the branch instruction, or use a matrix formed of a predetermined bit pattern. have.

In operation S1450, the value of the array having the preset length stored in the generated at least one address is read and the at least one value of the array is compared.

According to an embodiment of the present invention, if at least one or more values of the array of the preset length stored in the at least one or more addresses are all the same, the branch instruction may be verified as valid in step S1460. If the branch instruction is valid when at least one or more values of the array having the predetermined length are all '1', the AND operation is performed on the at least one or more values of the array. If is '1' the branch instruction can verify that it is valid.

If the branch instruction is verified as a valid branch instruction, the branch instruction is executed in step S1470.

If at least one or more values of the array of the preset length are not the same at step S1450, the branch instruction may be verified as an invalid branch instruction at step S1480. In operation S1490, execution of the program for executing the branch instruction may be stopped.

According to the present invention, a malfunction due to a computer virus computer virus can be prevented without using a vaccine program for monitoring and treating a computer virus.

According to the present invention, a computer attacked by a hacker can be prevented from executing a program inserted by the hacker, thereby protecting user data and confidentiality.

Claims (30)

In the central processing unit, A branch instruction verifier for verifying that the branch instruction is valid; And A branch instruction execution unit that executes the branch instruction when the branch instruction is verified to be valid; Central processing unit comprising a. The method of claim 1, And the branch instruction execution unit does not execute the branch instruction when the branch instruction is verified to be invalid. The method of claim 1, And the branch instruction execution unit determines that an error has occurred in the branch instruction when the branch instruction is verified to be invalid. The method of claim 1, A branch predictor for predicting a branch destination address for the branch instruction; And A branch calculation unit that calculates a branch destination address for the branch instruction. More, And the branch instruction verifying unit verifies that the branch instruction is valid when the predicted value of the branch target address and the calculated value of the branch target address do not coincide with each other. The method of claim 1, The branch instruction verification unit, And verify that the branch instruction is valid based on a combination of a current address value associated with the branch instruction and a branch destination address value for the branch instruction. The method of claim 5, The branch instruction verification unit, A lookup table consisting of a combination of a current address value associated with at least one branch instruction and at least one destination address value associated with the at least one current address value Including, A combination of a current address value associated with the branch instruction and a branch destination address value for the branch instruction verifies whether the branch instruction is valid based on the reference table. The method of claim 5, wherein the branch instruction verification unit, And considering the instruction execution history prior to the branch instruction to verify whether the branch instruction is valid. The method of claim 5, wherein the branch instruction verification unit, And considering the branch history prior to the branch instruction to verify whether the branch instruction is valid. The method of claim 8, wherein the branch instruction verification unit, And a branch purpose address calculated for the branch instruction before the branch instruction, and a branch target address branched to the branch instruction before the branch instruction. The method of claim 5, The branch instruction verification unit has an array of a preset length, Input a combination of a current address value associated with the branch instruction and a branch destination address value for the branch instruction to at least one hash function, to generate at least one address value of the array, And determine whether the branch instruction is valid based on a value of the array stored at the at least one address. The method of claim 10, wherein the branch instruction verification unit, And verify that the branch instruction is valid when all of the values of the array stored at the at least one address are the same. 11. The method of claim 10, wherein the hash function Shuffle the bit order of the current address value associated with the branch instruction in a predetermined manner, and perform an exclusive OR operation with the branch purpose address value for the branch instruction to generate an address value of the array having the preset length. Central processing unit. 11. The method of claim 10, wherein the hash function At least one of a Secure Hash Algorithm (SHA) -1 algorithm, a Message-Digest algorithm 5 (MD5) algorithm, a keyed-Hash Message Authentication Code (HMAC) algorithm, and an Advanced Encryption Standard (AES) standard. Central processing unit. The method of claim 10, wherein the hash function, Having a matrix composed of predetermined bit patterns, Perform an AND operation on each of the combinations and components of a particular column of the matrix corresponding to the combinations, And performing an exclusive OR operation on the plurality of AND-operated values to generate an address of the array having the predetermined length. The method of claim 10, The at least one hash function is divided into at least one group, A predetermined area of the array of the preset length is allocated for each of the at least one group, And the at least one hash function generates only a lower address value for the predetermined area assigned to a group to which the hash function belongs. The method of claim 14, wherein the branch instruction verification unit, Generate a first address of the array of the preset length using a hash function having the combination and the first matrix, store the first value at the first address of the array in a buffer, Generating a second address of the array of the preset length using a hash function having the combination and a second matrix, And verify whether the branch instruction is valid based on a first value of the array stored in the buffer and a second value at the second address of the array. The method of claim 16, wherein the branch instruction verification unit, And verify whether the branch instruction is valid based on the identity of the first value of the array stored in the buffer and the second value at the second address of the array. In the central processing unit, A reference table composed of a combination of at least one branch instruction address value and a branch destination address value for the branch instruction, If a combination of a current address value associated with the particular branch instruction and a branch destination address value for the branch instruction does not exist in the lookup table, the branch instruction is determined to be an invalid branch instruction, And not executing the branch instruction. In the central processing unit, Having an array of preset lengths, A combination of an address value of a branch instruction stored in a program counter and a branch destination address value for the branch instruction is input to at least one hash function to generate at least one address value of the array, Determine whether the branch instruction is valid based on a value of the array stored at the at least one address, And if the branch instruction is invalid as a result of the determination, the branch instruction is not executed. The method of claim 19, And if the values of the array stored at the at least one or more addresses are not the same, verifying that the branch instruction is invalid. 20. The method of claim 19, wherein the hash function By shuffling the bit order of the current address value associated with the branch instruction in a predetermined manner, performing an exclusive OR operation with a branch destination address value for the branch instruction to perform an address of the array of the preset length. Generating a value. The method of claim 19, wherein the hash function, Having a matrix composed of predetermined bit patterns, Perform an AND operation on each of the combinations and components of a particular column of the matrix corresponding to the combinations, And performing an exclusive OR operation on the plurality of AND-operated values to generate an address of the array having the predetermined length. In the central processing unit executes a branch instruction, Verifying that the branch instruction is valid; And If the branch instruction is verified to be invalid, not executing the branch instruction Branch instruction execution method comprising a. 24. The method of claim 23, wherein not executing the branch instruction is Determining that an error has occurred in the branch instruction Branch instruction execution method comprising a further. 24. The method of claim 23, wherein verifying that the branch instruction is valid: Predicting a branch destination address for the branch instruction; And Calculating a branch destination address for the branch instruction More, And if the predicted branch destination address and the calculated branch destination address are not the same, verifying that the branch instruction is valid. 24. The method of claim 23, wherein verifying that the branch instruction is valid: Storing and maintaining in the memory a look-up table consisting of a combination of a current address value associated with at least one branch instruction and a branch destination address value for the branch instruction; Generating a branch destination address for the branch instruction; Determining whether a combination of a current address value associated with the branch instruction and a branch destination address value for the branch instruction is present in the lookup table; And Verifying that the branch instruction is valid if the combination exists in the lookup table. Branch instruction execution method comprising a. 24. The method of claim 23, wherein verifying that the branch instruction is valid: Inputting at least one hash function a combination of a current address value associated with the branch instruction and a branch destination address value for the branch instruction; The at least one hash function generating at least one address value of an array of a predetermined length; And Comparing the values of the array stored at the at least one address to verify that the branch instruction is valid Branch instruction execution method comprising a. The method of claim 27, The at least one hash function generating at least one address value of an array of a preset length, By shuffling the bit order of the current address value associated with the branch instruction in a predetermined manner, performing an exclusive OR operation with a branch destination address value for the branch instruction to perform an address of the array of the preset length. Method of executing a branch instruction, characterized in that to generate a value. The method of claim 27, The at least one hash function generating at least one address value of an array of a preset length, Performing an AND operation on each of the combinations and components of a particular column of the matrix corresponding to the combinations; And And generating an address of the array having the predetermined length by performing an exclusive OR operation on the plurality of AND-operated values. 28. The method of claim 27, wherein verifying that the branch instruction is valid: And verifying that the branch instruction is valid when all of the values of the array stored at the at least one address are the same.

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