KR20080056781A - Gate driving circuit and liquid crystal display using thereof - Google Patents

Abstract

A gate driver and an LCD(Liquid Crystal Display) device using the same are provided to supply stable gate off signals by sharing a reset signal and a start time pulse supplied to a dual gate driver. A gate driver includes a circuit unit(132) and a wiring unit(134). The circuit unit includes plural stages, whose output terminals are connected to plural gate lines. Then, the stages output gate driving signals as gate clock pulses to be supplied to plural gate lines in response to a start time pulse. The wiring unit includes start time pulse wires, which receive the start time pulse from outside and supply the start time pulse to input terminals of odd and even first stages among the stages, and reset wires, which are connected to reset terminals of the stages. The odd stages include a first dummy stage, whose carry terminal is connected to a control terminal of the last odd stage. The even stages include a second dummy stage, whose carry terminal is connected to a control terminal of the last even stage. An output terminal of the second dummy stage supplies a reset signal to the reset wires.

Description

Gate driving circuit and liquid crystal display using the same {GATE DRIVING CIRCUIT AND LIQUID CRYSTAL DISPLAY USING THEREOF}

1 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention;

FIG. 2 is a diagram illustrating input and output signal relationships between the first and second level shifters shown in FIG. 1;

3 is an exemplary circuit diagram of the first level shifter shown in FIG. 2;

4 is a block diagram illustrating a configuration of the first and second gate driving circuits illustrated in FIG. 2;

FIG. 5 is an exemplary circuit diagram of a stage of the first gate driving circuit shown in FIG. 4.

6 is a simulation graph for explaining the operation of the gate driving circuit shown in FIG. 4, and

FIG. 7 is a simulation graph illustrating output waveforms of an n + 2 stage among the gate driving circuits shown in FIG. 4.

<Code Description of Main Parts of Drawing>

100: liquid crystal display 110: liquid crystal panel

120: data driver 130: first gate driving circuit

140: second gate driving circuit 150: first level shifter

160: second level shifter 170: timing controller

180: power supply

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device including a gate driving circuit.

In general, the liquid crystal display includes a liquid crystal panel for displaying an image, a data driver for driving the liquid crystal panel, and a gate driver. The liquid crystal panel includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels. The pixel consists of a thin film transistor and a liquid crystal capacitor. The data driver outputs a data signal to the data line, and the gate driver outputs a gate driving signal.

The gate driver is simultaneously formed on the liquid crystal panel through the same process as the thin film transistor, and the data driver is formed in a chip form and connected to the peripheral region of the liquid crystal panel. The gate driver includes a shifter register composed of a plurality of stages, each stage being connected to a corresponding gate line to output a gate driving signal.

The gate drivers are connected to each other in order to sequentially output gate driving signals to the plurality of gate lines. That is, the input terminal of the current stage is connected to the output terminal of the previous stage, and the output terminal of the next stage is connected to the control terminal of the current stage. The start signal is input to the first stage of the plurality of stages.

The gate driver is formed on the left and right sides of the liquid crystal panel so that the gate driver circuit on the left side drives the odd-numbered gate lines and the gate driver circuit on the right side drives the even-numbered gate lines in a single driving manner.

In a single driving liquid crystal display, a deviation occurs as the gate driving signal output from the left and right gate driving circuits reaches the end of the gate line due to a gate line delay. The deviation of the gate driving signal causes the charging time of the pixel to be insufficient, resulting in a horizontal line recognition phenomenon.

In order to solve the problem of insufficient pixel charging time of the single driving method, a dual driving method is proposed in which the same gate control circuit is formed on the left and right sides of the liquid crystal panel to apply the same gate driving signal to the gate line on the left and right sides. have.

However, the conventional dual driving type liquid crystal display device requires twice as much signal wiring to be connected to the gate driving circuit as compared to the single driving type, thereby securing the integrated space of the liquid crystal panel. The change in the integrated space of the liquid crystal panel means a change in the size of the liquid crystal panel, which requires a change in the equipment used in the existing liquid crystal panel manufacturing process, thereby causing a problem of increasing the manufacturing cost of the liquid crystal panel.

Accordingly, the present invention has been made to solve the conventional problems, and provides a gate off signal stably while reducing the signal wiring connected to the gate driving circuit by sharing the reset pulse and the reset signal provided to the dual gate driving circuit. Its purpose is to provide a gate driving circuit and a liquid crystal display device.

In order to achieve the above object, the gate driving circuit of the present invention includes a plurality of stages that are dependently connected to each other to output a gate clock pulse to a plurality of gate lines in response to one start pulse. The plurality of stages may include a circuit unit to which output terminals are respectively connected to a plurality of gate lines; And a start pulse wire configured to receive the start pulse from the outside and to provide the input terminals of the odd first and even first stages of the plurality of stages and the reset wires connecting the reset terminals of the plurality of stages. The odd-numbered stage of the plurality of stages includes a first dummy stage in which a carry terminal is connected to a control terminal of a last odd-numbered stage, and the even-numbered stage of the plurality of stages has a last even-numbered carry terminal. And a second dummy stage connected to the control terminal of the second stage, wherein the output terminal of the second dummy stage provides a reset signal to the reset wiring.

Here, the second dummy stage may include a pull-up transistor for providing the reset signal, and the pull-up transistor may be larger in size than the pull-up transistor of another stage of the plurality of stages.

In addition, it is preferable that the pull-up transistor of the second dummy stage is 2 to 2.5 times larger than the pull-up transistor of another stage of the plurality of stages.

The gate clock pulse may include a first gate clock pulse, a first gate clock bar pulse having an inverted phase of a phase of the first gate clock pulse, a second gate clock pulse having a delayed phase of the first gate clock pulse, and a second gate. A second gate clock bar pulse having an inverted phase of a phase of a clock pulse, wherein the odd-numbered stage outputs the first gate clock pulse or the first gate clock bar pulse as the gate driving signal, and the even-numbered The stage may output the second gate clock pulse or the second gate clock bar pulse as the gate driving signal.

In addition, it is preferable that the one start signal is input to an input terminal of the first stage of the odd stage and the first stage of the even stage.

A liquid crystal display of the present invention includes a timing controller for generating an output enable signal, a gate clock, and one start signal in response to an external input signal; A level shifter generating a gate clock pulse in response to the output enable signal and a gate clock and generating one start pulse in response to the start signal; And a plurality of stages connected dependently to each other for outputting the gate clock pulse as a gate driving signal to be provided to a plurality of gate lines in response to the one start pulse, wherein the odd numbered stages of the plurality of stages are carry The terminal includes a first dummy stage connected to a control terminal of the last odd-numbered stage, the even-numbered stage of the plurality of stages includes a second dummy stage in which the carry terminal is connected to the control terminal of the last-even-numbered stage, The output terminal of the second dummy stage includes first and second gate driving circuits for providing a reset signal to reset terminals of the plurality of stages.

The liquid crystal display of the present invention further includes a power supply unit supplying the gate on voltage and the gate off voltage to the level shifter, wherein the level shifter comprises: the gate clock pulse having the gate on voltage and the gate off voltage levels; It is preferable to output the gate clock bar pulse and the start pulse.

The level shifter may include a first level shifting unit configured to logically operate the output enable signal and the gate clock, amplify a voltage level, and output the amplified voltage as the gate clock pulse; And a second level shifting unit configured to logically operate the output enable signal and the gate clock, invert the phase, and amplify the voltage level to output the gate clock bar pulse.

The first and second gate driving circuits may be integrated in the liquid crystal panel in which the gate lines are formed, and are formed at both ends of the gate lines to dually drive the gate lines.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention. As illustrated in FIG. 1, the liquid crystal display 100 according to an exemplary embodiment of the present invention may include a liquid crystal panel 110, a data driver 120, first and second gate driving circuits 130 and 140, The first and second level shifters 150 and 160, the timing controller 170, and the power supply unit 180 are included.

The liquid crystal panel 110 includes a thin film transistor substrate 112, a color filter substrate 114, and a liquid crystal (not shown) interposed between the thin film transistor substrate 112 and the color filter substrate 114.

The thin film transistor substrate 112 includes a display area DA and first and second peripheral areas PA1 and PA2. The display area DA includes gate lines GL1 through GLn, data lines DL1 through DLm, gate lines GL1 through GLn, and data lines DL1 through GLn. The pixel defined in the intersection area of (DLm) is formed. First and second gate driving circuits 130 and 140 driving the gate lines GL1 to GLn are formed in the first peripheral area PA1. In the second peripheral area PA2, the data driver 120 driving the data lines DL1, DLm is mounted. Here, the first peripheral area PA1 is an area adjacent to both ends of the gate lines GL1, ..., GLn, and the second peripheral area PA2 is one end of the data lines DL1, ..., DLm. Is an area adjacent to

The pixel includes a thin film transistor (TFT) connected to the gate lines GL1, ..., GLn and the data lines DL1, ..., DLm, a liquid crystal capacitor (CLC) connected to the thin film transistor (TFT), and a storage capacitor. (CST). The gate and the source of the thin film transistor TFT are connected to the gate lines GL1, ..., GLn and the data lines DL1, ..., DLm, respectively, and the drains thereof are the liquid crystal capacitor CLC and the storage capacitor CST. Is connected to. The liquid crystal capacitor CLC has a pixel electrode and a common electrode as two terminals, and is formed of a liquid crystal that functions as a dielectric between the two terminals.

The color filter substrate 114 includes a black matrix for preventing light leakage, a color filter for implementing colors, and a common electrode. The liquid crystal is a material having dielectric anisotropy and is rotated by a difference between voltages applied to the common electrode and the pixel electrode to adjust light transmittance.

The first and second gate driving circuits 130 and 140 are integrally formed in the first peripheral area PA1 on one side and the other side of the liquid crystal panel 110 with the gate lines GL1,..., GLn interposed therebetween. And its output is connected to each of the gate lines GL1, ..., GLn. The first and second gate driving circuits 130 and 140 sequentially provide gate driving signals at both ends of the gate lines GL1, ..., GLn to dualize the gate lines GL1, ..., GLn. Drive it.

The data driver 120 receives a data control signal and data from the timing controller 140, selects an analog driving voltage corresponding to the data, and provides the gray level display voltage to the data lines DL1,..., DLm. . The data driver 120 is implemented as an integrated chip and is mounted in the second peripheral area PA2 of the thin film transistor substrate 112. The data driver 120 is connected to the timing controller 170 and the power supply unit 180 through the flexible circuit board 102 connected to the second peripheral area PA2.

Meanwhile, in the present exemplary embodiment, the data driver 120 is mounted on the thin film transistor substrate 112 in a chip on glass (COG) method, but is not limited thereto. The data driver 120 may be mounted in a tape carrier package (TCP) structure.

The first and second level shifters 150 and 160 receive gate control signals from the timing controller 140 and receive driving voltages from the power supply unit 180 to drive the gate driving circuits 130 and 140. A signal to be generated is provided to the first and second gate driving circuits 130 and 140.

The timing controller 140 receives data and an input control signal from an external source, generates a gate control signal and a data control signal, and provides the gate control signal and the data control signal to the first and second level shifters 150 and 160 and the data driver 120. The data is an RGB image signal, and the input control signal includes a vertical sync signal VSYNC, a horizontal sync signal HSYNC, a main clock MCLK, and a data enable signal DE.

The power supply unit 180 generates an analog driving voltage AVDD, a common voltage VCOM, and a gate driving voltage using a power supply voltage supplied from an external source. The power supply unit 180 supplies the analog driving voltage AVDD to the data driver 120, supplies the common voltage VCOM to the common electrode of the liquid crystal panel 110, and supplies the gate driving voltage to the first and second levels. It is provided to the shifters 150 and 160.

The timing controller 170, the first and second level shifters 150 and 160, and the power supply unit 180 are mounted on the control printed circuit board 104. The control printed circuit board 104 is connected to the second peripheral area PA2 of the thin film transistor substrate 112 through the flexible circuit board 102. The first and second gate driving circuits 130 and 140 formed in the liquid crystal panel 110 are directly connected to the timing controller 140 and the power supply unit 180 through the data driver 120 or the flexible circuit board 102. Can be connected.

FIG. 2 is a diagram illustrating input and output signal relationships between the first and second level shifters illustrated in FIG. 1. As shown in FIG. 2, the first and second level shifters 150 and 160 receive a gate on voltage VON and a gate off voltage VOFF from the power supply 180.

In addition, the first and second level shifts 150 and 160 may include the output enable signal OE, the first and second gate clocks CPV1 and CPV2 and the gate start signal STV, which are gate control signals from the timing controller 170. Is provided). The second gate clock CPV2 is a clock whose phase of the first gate clock CPV1 is delayed. The phase difference between the first and second gate clocks CPV1 and CPV2 is a half horizontal period in which the gate driving signals provided to the adjacent gate lines overlap each other. In addition, the gate start signal STV is a signal indicating the start of one frame.

The first and second level shifters 150 and 160 may receive a start pulse STVP having a gate on voltage VON and a gate off voltage VOFF level, and first and second gate clock pulses CKV1 in response to a gate control signal. , CKV2, and first and second gate clock bar pulses CKVB1 and CKVB2. Here, the start pulse STVP causes the gate driving circuits 130 and 140 to generate the first gate driving signal of one frame. The first and second gate clock bar pulses CKVB1 and CKVB2 are signals for increasing the speed of driving the gate line.

The first and second level shifters 150 and 160 may generate the generated start pulses STVP, the first and second gate clock pulses CKV1 and CKV2, and the first and second gate clock bar pulses CKVB1 and CKVB2. The first and second gate driving circuits 130 and 140 are provided through the data driver 120.

The first and second level shifters 150 and 160 according to the present exemplary embodiment generate one start pulse STVP in the first and second gate driving circuits 130 and 140 to generate the first gate driving circuit 130, 140). When the first and second gate driving circuits 130 and 140 receive the start pulse STVP, the first and second gate driving circuits 130 and 140 start generating the gate driving signal and providing the gate driving signal to the gate line.

3 is an exemplary circuit diagram of the first level shifter shown in FIG. 2. As illustrated in FIG. 3, the first level shifter 130 includes a first level shifting unit 132, a second level shifting unit 134, and a third level shifting unit 136.

The first level shifting unit 132 performs a logic operation on the output enable signal OE and the gate clock CPV1, amplifies a voltage level, and provides a gate clock for the first and second gate driving circuits 130 and 140. Generate a pulse CKV1. To this end, the first level shifting unit 132 includes a logic operation unit LG1, a driving inverter INV1, and a full swing inverter 133.

The logic calculator LG1 calculates by outputting the output enable signal OE and the first gate clock CPV1. The driving inverter INV1 inverts the phase of the output of the logic calculating unit LG1 and amplifies the driving level of the full swing inverter 133. The full swing inverter 133 generates a first gate clock pulse CKV1 having a gate on voltage VON and a gate off voltage VOFF in response to the output of the driving inverter INV1.

The second level shifting unit 134 performs a logic operation on the output enable signal OE and the first gate clock CPV1 and amplifies a voltage level to provide the first and second gate driving circuits 130 to the first and second gate driving circuits 130. The gate clock bar pulse CKVB1 is generated. To this end, the second level shifting unit 134 includes a logic operation unit LG2, an inverting inverter INV2, a driving inverter INV3, and a full swing inverter 135. Here, the first gate clock bar pulse CKVB1 is a clock in which the phase of the first gate clock pulse CKV1 is inverted.

The logic calculator LG2 calculates by outputting the output enable signal OE and the first gate clock CPV1. The inverting inverter INV2 inverts the phase of the output of the logic calculating section LG1 and outputs it. The driving inverter INV3 inverts the phase of the output of the inverting inverter INV2 and amplifies the driving level of the full swing inverter 135. The full swing inverter 135 generates a first gate clock bar pulse CKVB1 having a gate on voltage VON and a gate off voltage VOFF level in response to the output of the driving inverter 135.

The third level shifting unit 136 receives the output enable signal OE and the gate start signal STV to generate a start pulse STVP having a gate on voltage VON and a gate off voltage VOFF. Here, the start pulse STVP has the same period and pulse width as the gate start pulse STV, and the voltage level has a gate on voltage VON and a gate off voltage VOFF.

Meanwhile, the second level shifter 140 receives a gate on voltage VON and a gate off voltage VOFF, which are gate driving voltages, from the power supply unit 180, and outputs an output enable signal OE from the timing controller 170. The start gate STVP, the second gate clock pulse CKV2 and the second gate clock voltage VON and the gate-off voltage VOFF level are provided by the second gate clock CPV2 and the gate start signal STV. The gate clock bar pulse CKVB2 is generated and supplied to the first and second gate driving circuits 130 and 140. Since the configuration and operation of the second level shifter 140 are similar to the configuration and operation of the first level shifter 130 described above, a detailed description thereof will be omitted.

4 is a block diagram illustrating the first and second gate driving circuits of FIG. 2. As shown in FIG. 4, the first and second gate driving circuits 130 and 140 may be provided at both sides of the display area DA to dually drive the gate lines GL1,..., GLn from both sides. Are placed adjacent to each other. The first and second gate driving circuits 130 and 140 have symmetrical structures with respect to the gate lines GL1,..., GLn.

The first gate driving circuit 130 includes a wiring unit 134 for receiving and transmitting various signals from the data driver 120 and a circuit unit 132 for sequentially outputting gate driving signals in response to various signals.

The circuit unit 132 includes a shifter register including a plurality of stages STAGE1,..., And STAGE n + 2 that are dependently connected to each other. The first to nth stages STAGE1 to STAGEn are electrically connected to the first to nth gate lines GL1 to GLn to sequentially output gate driving signals. The n + 1 stage STAGE n + 1 and the n + 2 stage STAGE n + 2 are dummy stages. Where n is even.

Each of the stages STAGE1, ..., STAGE n + 2 has the first and second clock terminals CK1 and CK2, an input terminal IN, a control terminal CT, an output terminal OUT, and a reset. It includes a terminal RE, a carry terminal CR, and a ground voltage terminal VSS.

The odd-numbered stages STAGE1, STAGE3, ..., STAGE n + 1 of the stages STAGE1, ..., STAGE n + 2 are connected to the first clock terminal CK1 and the second clock terminal CK2. The first gate clock pulse CKV1 or the second gate clock bar pulse CKVB1 is provided. More specifically, the STAGE1, STAGE5, ..., STAGE n-1 stages among the odd-numbered stages are provided with the first gate clock pulse CKV1 at the first clock terminal CK1 and the second clock terminal CK2. One gate clock bar pulse CKVB1 is provided. The STAGE3, STAGE7, ..., STAG En + 1 stages among the odd-numbered stages are provided with a first gate clock bar pulse CKVB1 at the first clock terminal CK1 and a first gate clock at the second clock terminal CK2. The pulse CKV1 is provided.

The input terminal IN of the odd-numbered stages STAGE1, STAGE3, ..., STAGE n + 1 is connected to the carry terminal CR of the previous odd-numbered stage to provide a carry signal of the previous odd-numbered stage, and the control terminal. CT is connected to the output terminal OUT of the next odd-numbered stage to provide an output signal of the next odd-numbered stage. The odd first stay STAGE1 is provided with a start pulse STVP at the input terminal IN since no previous stage exists. The carry signal output from the carry terminal CR serves to drive the next odd stage.

The start pulse STVP is preferably provided to the control terminal CT of the dummy stage STAG En + 1 that provides a carry signal to the control terminal CT of the n−1 th stage STAGE n-1. The ground voltage VOFF is provided to the ground voltage terminal VSS of the odd-numbered stages STAGE1, STAGE3, ..., STAGE n + 1, and the reset terminal RE is provided to the n + 2 stage STAGE n + 2. The output signal of is provided.

The output terminal OUT of the STAGE1, STAGE5, ..., STAGE n-1 stages outputs the first gate clock pulse CKV1 as a gate driving signal, and the carry terminal CR outputs the first gate clock pulse CKV1. ) Is output as a carry signal. The output terminal OUT of the STAGE3, STAGE7, ..., STAGE n + 1 stage outputs the first gate clock bar pulse CKVB1 as a gate driving signal, and the carry terminal CR outputs the first gate clock pulse CKVB1. ) Is output as a carry signal.

The even-numbered stages STAGE2, STAGE4, ..., STAGE n + 2 of the stages STAGE1, ..., STAGE n + 2 are connected to the first clock terminal CK1 and the second clock terminal CK2. The second gate clock pulse CKV2 and the second gate clock bar pulse CKVB2 are provided. More specifically. The STAGE2, STAGE6, ..., STAGEn stages among the even-numbered stages are provided with the second gate clock pulse CKV2 at the first clock terminal CK1 and the second gate clock bar pulse CKVB2 at the second clock terminal CK2. ) Is provided. The STAGE4, STAGE8, ..., STAGE n + 2 stages of the even-numbered stages are provided with the second gate clock bar pulse CKVB2 at the first clock terminal CK1 and the second gate clock at the second clock terminal CK2. Pulse CKV2 is provided.

The input terminals IN of the even-numbered stages STAGE2, STAGE4, ..., STAGE n + 2 are connected to the carry terminal CR of the previous even-numbered stage to provide a carry signal of the previous even-numbered stage, and the control terminal. CT is connected to the output terminal OUT of the next even-numbered stage to provide an output signal of the next even-numbered stage. The even first stage STAGE1 is provided with a start pulse STVP at the input terminal IN since no previous stage exists. The carry signal output from the carry terminal CR serves to drive the next even stage.

The start pulse STVP is preferably provided to the control terminal CT of the dummy stage STAGE n + 2 that provides the carry signal to the control terminal CT of the nth stage STAGEn. The ground voltage terminal VSS is provided to the ground voltage terminal VSS of the even-numbered stages STAGE2, STAGE4, ..., STAGE n + 2, and the reset terminal RE is provided to the n + 2 stage STAGE n + 2. The output signal of is provided.

The output terminals OUT of the STAGE2, STAGE6, ..., STAGEn stages output the second gate clock pulse CKV2 as the gate driving signal, and the carry terminal CR carries the second gate clock pulse CKV2. Output as a signal. The output terminal OUT of the STAGE4, STAGE8, ..., STAGE n + 2 stages outputs the second gate clock bar pulse CKVB2 as the gate driving signal, and the carry terminal CR outputs the second gate clock bar pulse ( CKVB2) is output as a carry signal.

In other words, in the first gate driving circuit 130, the odd-numbered stages STAGE1, STAGE3,..., STAGE n + 1 are applied to the first gate clock pulse CKV1 and the first gate clock bar pulse CKVB1. In operation, the even-numbered stages STAGE2, STAGE4, ..., STAGE n + 2 operate in synchronization with the second gate clock pulse CKV2 and the second gate clock bar pulse CKVB1.

The output terminals OUT of the plurality of stages STAGE1,..., STAGE n + 1 of the first gate driving circuit 130 are connected to the gate lines GL1,..., GLn formed in the display area DA. The gate lines GL1, ..., GLn are sequentially driven by sequentially supplying gate driving signals to the gate lines GL1, ..., GLn.

The wiring portion 134 is formed adjacent to the circuit portion 132. The wiring unit 134 includes the start pulse wiring SL1, the first gate clock pulse wiring SL2, the first gate clock bar pulse wiring SL3, the second gate clock pulse wiring SL4, and the first gate clock wiring wire SL1 extending parallel to each other. The two gate clock bar pulse line SL5, a ground voltage line SL6, a first reset line SL7, and a second reset line SL5 are included.

The start pulse wiring SL1 receives the start pulse STVP from the first level shifter 150, receives an input terminal of the first stage STAGE1, an input terminal of the second stage STAGE2, and an n + 1 stage STAGE n. Input to the control terminal CT of +1) and the control terminal CT of the n + 2 stage STAGE n + 2.

The first gate clock pulse line SL2 receives the first gate clock pulse CKV1 from the first level shifter 150 to receive the first clock of the STAGE1, STAGE5, ..., STAGE n-1 stages among the odd-numbered stages. It is provided to the terminal CK1 and is provided to the second clock terminal CK2 of the STAGE3, STAGE7, ..., STAGE n + 1 stage.

The first gate clock bar pulse line SL3 receives the first gate clock bar pulse CKVB1 from the first level shifter 150 to receive the first gate of STAGE1, STAGE5, ..., STAGE n + 1 among the odd-numbered stages. It is provided to the clock terminal CK1 and is provided to the second clock terminal CK2 of the STAGE3, STAGE7, ..., STAGE n + 1 stages.

The second gate clock pulse line SL4 receives the second gate clock pulse CKV2 from the second level shifter 160 to receive the first clock terminal of the STAGE2, STAGE6, ..., STAGE n stages of the even-numbered stages. CK1) to the second clock terminal CK2 of the STAGE4, STAGE8, ..., STAGE n + 2 stages.

The second gate clock bar pulse line SL5 receives the second gate clock bar pulse CKVB2 from the second level shifter 160 to receive the first gates of STAGE4, STAGE8, ..., STAGE n + 2 of the even-numbered stages. It is provided to the clock terminal CK1 and is provided to the second clock terminal CK2 of the STAGE2, STAGE6, ..., STAGE n stage.

The ground voltage line SL6 receives the gate-off voltage VOFF from the power supply unit 180 to the ground voltage terminal VSS of the first to n + 2th stages STAGE1,..., STAGE n + 2. Supply.

The reset wiring SL7 receives the output signal of the output terminal OUT of the n + 2th stage STAGEn + 2 and the reset terminal of the first to n + 2th stages STAGE1,..., STAGE n + 2. RE). Accordingly, the gate driving circuit 130 according to the embodiment of the present invention may have odd-numbered stages STAGE1, STAGE3, ..., STAGE n + 1 and even-numbered stages STAGE2, STAGE4, ..., STAGE n +. 2) has a structure in which one reset signal is shared.

The first and second gate driving circuits 130 and 140 have symmetrical structures with respect to the gate lines GL1,..., GLn, and the second gate driving circuits 130 may be formed from the first gate driving circuit 130. Since the configuration of the 140 can be easily inferred, a detailed description of the second gate driving circuit 140 will be omitted.

FIG. 5 is an exemplary circuit diagram of the first stage shown in FIG. 4. Since the first stage illustrated in FIG. 4 has the same configuration as that of the second to n + 2 stages, the internal configuration of the first stage will be described instead of the description of each of the second to n + 2 stages. . As shown in FIG. 5, the first stage STAGE1 includes a pull-up part 132a, a pull-down part 132b, a driver 132c, a holding part 133d, a switching part 133e, and a carry part 133f. It includes.

The pull-up unit 132a pulls up the first gate clock pulse CKV1 provided through the first clock terminal CK1 to output the gate driving signal through the output terminal OUT. The pull-up unit 132a includes a first transistor NT1 having a gate connected to the first node N1, a drain connected to the first clock terminal CK1, and a source connected to the output terminal OUT. .

The pull-down unit 132b pulls down the gate driving signal pulled up in response to the carry signal from the third stage STAGE3 to the gate-off voltage VOFF provided through the ground voltage terminal VSS. The pull-down unit 132b includes a second transistor NT2 having a gate connected to the control terminal CT, a drain connected to the output terminal OUT, and a source connected to the ground voltage terminal VSS.

The driver 132c turns on the pull-up unit 132a in response to the start pulse STVP provided through the input terminal IN, and turns it off in response to a carry signal of the third stage STAGE3. To this end, the driving unit 132c includes a buffer unit, a charging unit, and a discharge unit.

The buffer part includes a third transistor NT3 having a gate and a drain connected to the input terminal IN in common and a source connected to the first node N1. The charging unit includes a first capacitor C1 having a first electrode connected to the first node N1 and a second electrode connected to the second node. The discharge part includes a fourth transistor NT4 having a gate connected to the control terminal CT, a drain connected to the first node N1, and a source connected to the ground voltage terminal VSS.

When the start pulse STVP is input to the input terminal IN, the third transistor NT3 is turned on in response to the start pulse STVP being charged in the first capacitor C1. When the first capacitor C1 is charged with a charge equal to or greater than the threshold voltage of the first transistor NT1, the first transistor NT1 is turned on to provide the first gate clock pulse CKV1 provided to the first clock terminal CK1. Output to the output terminal (OUT).

At this time, the potential of the node 1 (N1) is a bootstrap by the amount of change in the potential of the node 2 (N2) by coupling of the first capacitor C1 according to the sudden change of the potential of the node 2 (N2). do. Accordingly, the first transistor NT1 can easily output the first gate clock pulse CKV1 applied to the drain to the output terminal OUT. The first gate clock pulse CKV1 output to the output terminal OUT becomes a gate driving signal provided to the gate line. The start pulse STVP is used as a signal for preliminarily charging the first transistor NT1 to generate the first gate driving signal.

Subsequently, when the fourth transistor NT4 is turned on in response to a carry signal of the third stage STAGE3 input through the control terminal CT, the charge charged in the first capacitor C1 is transferred through the ground voltage terminal VSS. Discharged to the provided gate off voltage (VOFF) level.

The holding part 132d includes fifth and sixth transistors NT5 and NT6 for holding the gate driving signal at a gate-off voltage VOFF level. The fifth transistor NT5 has a gate connected to the third node N3, a drain connected to the second node N2, and a source connected to the ground safety terminal VSS. The sixth transistor N6 has a gate connected to the second clock terminal CK2, a drain connected to the second node, and a source connected to the ground voltage terminal VSS.

The switching unit 132e includes seventh, eighth, ninth and tenth transistors NT7, NT8, NT9, NT10 and second and third capacitors C2 and C3 to drive the holding unit 132d. To control. A gate and a drain of the seventh transistor NT7 are connected to the first clock terminal CK1 and a source thereof is connected to the third node. The eighth transistor NT8 has a drain connected to the first clock terminal CK1, a gate connected to a drain through a second capacitor C2, a source connected to a third node, and a gate connected through a third capacitor C3. Is connected to. The ninth transistor NT9 has a drain connected to the source of the seventh transistor NT7, a gate connected to the second node N2, and a source connected to the ground voltage terminal VSS. A drain of the tenth transistor NT10 is connected to the third node N3, a gate thereof is connected to the second node N2, and a source thereof is connected to the ground voltage terminal VSS.

When the gate clock pulse having the high state is output to the output terminal OUT as the gate driving signal, the potential of the second node N2 rises to the high state. When the potential of the second node N2 rises to a high state, the ninth and tenth transistors NT9 and NT10 are turned on. At this time, even when the seventh and eighth transistors NT7 and NT8 are turned on by the first gate clock pulse CKV1 braked to the first clock terminal CK1, the signals output from the seventh and eighth transistors are Discharged to the ground voltage VOFF through the ninth and tenth transistors NT9 and NT10. Therefore, while the gate driving signal of the high state is output, the potential of the third node N3 is kept low, so the fifth transistor NT5 is maintained in the turn-off state.

Thereafter, the gate driving signal is discharged through the ground voltage terminal VSS in response to the carry signal of the third stage STAGE3 input through the control terminal CT, and the potential of the second node N2 is set to a low state. Gradually descend. Accordingly, the ninth and tenth transistors NT9 and NT10 are turned off, and the potential of the third node N3 rises to a high state by a signal output from the seventh and eighth transistors NT7 and NT8. do. As the potential of the third node N3 is increased, the fifth transistor NT5 is turned on and the potential of the second node N2 is discharged to the ground voltage VOFF through the fifth transistor NT5.

In this state, when the sixth transistor NT6 is turned on by the first gate clock bar pulse CVKB1 provided to the second clock terminal CK2, the potential of the second node N2 turns off the ground voltage terminal VSSS. Discharge more reliably.

As a result, the fifth and sixth transistors NT5 and NT6 of the holding unit 132d hold the potential of the second node N2 in the ground voltage VOFF state. The switching unit 132e determines a time point at which the fifth transistor NT5 is turned on.

The carry unit 132f includes an eleventh transistor NT11 having a drain connected to the first clock terminal CK1, a gate connected to the first node N1, and a source connected to the carry terminal CR. As the potential of the first node N1 is increased, the eleventh transistor NT11 outputs the first gate clock pulse CKV1 input to the drain to the carry terminal CR.

Meanwhile, the first stage STAGE1 further includes a ripple prevention unit 132g and a reset unit 132h. The ripple prevention unit 132g prevents the gate driving signal, which is already maintained at the ground voltage VOFF, from being rippled by noise input through the input terminal IN. To this end, the ripple prevention unit 132g includes a twelfth transistor NT12 and a thirteenth transistor NT13. The twelfth transistor NT12 has a drain connected to the input terminal IN, a gate connected to the second clock terminal CK2, and a source connected to the first node N1. The thirteenth transistor NT13 has a drain connected to the first node N1, a gate connected to the first clock terminal CK1, and a source connected to the second node.

The reset part 132h includes a fourteenth transistor NT14 having a drain connected to the first node N1, a gate connected to the reset terminal RE, and a source connected to the ground voltage terminal VSS. The fourteenth transistor NT14 discharges the first node N1 to the ground voltage VOFF in response to an output signal of the n + 2th stage STAGE n + 2 input through the reset terminal RE. Since the output of the n + 2th stage STAGE n + 2 means the end of one frame, the reset unit 132h of the plurality of stages STAGE1, ..., STAGE n + 2 at the end of one frame. Discharges the first node N1.

That is, the reset unit 132h sequentially outputs the gate driving signals from the plurality of stages STAGE1 to STAGEn and then outputs the plurality of stages according to the output signals of the n + 2th stage STAGE n + 2. By turning on the fourteenth transistor NT14 of the STAGE1, ..., STAGE n + 2, the first node N1 of the plurality of stages STAGE1, ..., STAGE n + 2 is turned on to the ground voltage VOFF. Reset to). Accordingly, the plurality of stages STAGE1, ..., STAGE n + 2 of the circuit unit 132 may start operation again in an initialized state.

Meanwhile, the n + 2 stage STAGE n + 2 pulls up a transistor having a larger capacitance than the first transistor NT1 of the first to n + 1 stages STAGE1 to STAGE n + 1 described above. It is preferable to comprise). The pull-up unit 132a of the n + 2 stage STAGE n + 2 switches all the transistors NT14 constituting the reset unit 132h of the first to n + 2 stages STAGE1, ..., STAGE n + 2. This is because the driving is performed at the same time to stabilize the gate-off voltage VOFF supplied to the gate line.

The first transistor NT1 constituting the pull-up unit 132a of the n + 2 stage STAGE n + 2 is the pull-up unit 132a of the 1 to n + 1 stages STAGE1, ..., STAGE n + 1. It is preferable to have about 2 to 2.5 times the size of the transistor constituting. More preferably, the first transistor NT1 constituting the pull-up unit 132a of the n + 2 stage STAGE n + 2 is a pull-up of one to n + 1 stages STAGE1, ..., STAGE n + 1. It is 2.3 times larger than the transistor constituting the portion 132a.

6 is a simulation graph for describing an operation of a gate driving circuit of a liquid crystal display according to an exemplary embodiment of the present invention. As shown in FIG. 6, the gate driving circuit of the liquid crystal display according to the exemplary embodiment of the present invention uses the first odd stage 1ST ODD STAGE and the first even stage 1ST EVEN by one start pulse STVP. STAGE).

Here, the start pulse STVP may be the same pulse as the conventional first start pulse STVP1. Preferably, the rising time of the start pulse STVP is the same as the rising time of the conventional first start pulse STVP1, and the polling time is before the second gate clock pulse CKV2 is input to the input terminal of the first even stage. It is preferable.

More specifically, the start pulse STVP is simultaneously provided to an input terminal of the first odd stage 1ST ODD STAGE and an input terminal of the first even stage 1ST EVEN STAGE. The first odd stage 1ST ODD STAGE charges the provided start pulse STVP to the first capacitor C1 to generate a preliminary signal N1sig that turns on the gate of the first transistor NT1 in advance. The gate driving signal G1OUT is output in synchronization with the one gate clock pulse CKV1. The first even stage 1ST EVEN STAGE charges the provided start pulse STVP to the first capacitor C1 to generate a preliminary signal N2sig that turns on the gate of the first transistor NT1 in advance. The gate driving signal G2OUT is output in synchronization with the two gate clock pulse CKV2.

In this case, the first capacitor C1 of the first even stage 1ST EVEN STAGE starts charging when the start pulse STVP is charged to the first capacitor C1 of the first odd stage 1ST ODD STAGE. A preliminary signal N2sig for turning on the gate of one transistor NT1 is generated. That is, the first capacitor C1 of the first even stage 1ST EVEN STAGE includes the second gate clock pulse (including the time that the first capacitor of the first odd stage 1ST ODD STAGE charges to generate a preliminary signal). Charging is continued until CKV2) is input high. The first even stage 1ST EVEN STAGE outputs the gate driving signal G2OUT when the second gate clock pulse CKV2 is input to the high state.

That is, in the liquid crystal display according to the exemplary embodiment of the present invention, the first odd stage 1ST ODD STAGE and the first even stage 1ST EVEN STAGE may operate by sharing one start pulse STVP. This reduces the integrated space by one-half as compared with the case of the wiring configuration for providing the first and second start pulses.

7 is a simulation graph illustrating output waveforms of an n + 2 stage in a gate driving circuit of a liquid crystal display according to an exemplary embodiment of the present invention. Referring to FIG. 7, the gate driving circuit of the liquid crystal display according to the exemplary embodiment of the present invention may have an odd-numbered stage by one reset signal RST, which is an output signal of the n + 2th stage STAGE n + 2. STAGE1, STAGE3, ..., STAGE n + 1) and even-numbered stages (STAGE2, STAGE4, ..., STAGE n + 2) are reset at the same time.

The reset signal RST is generated by a pull-up part consisting of transistors about 2.5 times larger in size than the transistors constituting the pull-up parts of the 1 to n + 1 stages STAGE1, ..., STAGE n + 1. It can be seen that the signal has a greater driving capability than the gate driving circuit generated by the pull-up part of one stage STAGE1 to STAGE n + 1.

The reset signal RST is a signal indicating the end of one frame, and serves to discharge the first node N1 by turning on the fourteenth transistor T14 of the plurality of stages. The odd-numbered stages STAGE1, STAGE3, ... To reset the odd-numbered stages STAGE1, STAGE3, ..., STAGE n + 1 by providing a reset signal RST to the reset terminal RE of the stage n + 1). Even if the timing does not occur.

Accordingly, in the liquid crystal display according to the exemplary embodiment of the present invention, the odd-numbered stages STAGE1, STAGE3, ..., STAGE n + 1 and the even-numbered stages STAGE2, STAGE4, ..., STAGE n + 2 are one. It is possible to provide a gate-off voltage to the gate line stably while sharing the reset signal of. This reduces the integrated space of the wiring for providing the first and second reset signals by half.

The liquid crystal display of the present invention can stably provide the gate-off signal while reducing the signal wiring connected to the gate driving circuit by sharing the start pulse provided with the dual gate driving circuit with the reset signal. Stable operation can be guaranteed while the integrated space is reduced. In addition, the reduction of the integrated space for signal wiring enables the existing liquid crystal panel and the equipment used in the liquid crystal panel manufacturing process to be used as it is, thereby reducing the manufacturing cost of the liquid crystal panel.

In the detailed description of the present invention described above with reference to the preferred embodiment of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge of the present invention described in the claims to be described later It will be understood that various modifications and variations can be made in the present invention without departing from the spirit and scope of the art.

Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (13)

In order to output a gate clock pulse to a plurality of gate lines as a gate driving signal in response to one start pulse, the plurality of stages may be connected to each other, and the plurality of stages may include output terminals respectively connected to the plurality of gate lines. A circuit portion correspondingly connected; And A wiring unit configured to receive the start pulse from an external source and provide a start pulse wiring line to an input terminal of an odd first stage and an even first stage of the plurality of stages, and a reset line connecting the reset terminals of the plurality of stages; Including; The odd-numbered stage of the plurality of stages includes a first dummy stage having a carry terminal connected to a control terminal of a last odd-numbered stage, and the even-numbered stage of the plurality of stages has a carry terminal of a control terminal of a last even-numbered stage. A second dummy stage coupled to the output terminal of the second dummy stage to provide a reset signal to the reset wiring; Gate driving circuit comprising a. The method of claim 1, wherein the second dummy stage A pull-up transistor for providing the reset signal, wherein the pull-up transistor is larger in size than the pull-up transistor of another stage of the plurality of stages; Gate drive circuit. The method of claim 2, wherein the pull-up transistor of the second dummy stage 2 to 2.5 times larger than the pull-up transistor of the other stage of the plurality of stages Gate drive circuit. The method of claim 3, wherein The gate clock pulse may include a first gate clock pulse, a first gate clock bar pulse having an inverted phase of a phase of the first gate clock pulse, a second gate clock pulse having a delayed phase of the first gate clock pulse, and a second gate clock. A second gate clock bar pulse having an inverted phase of the phase of the pulse, The odd-numbered stage outputs the first gate clock pulse or the first gate clock bar pulse as the gate driving signal, The even stage may output the second gate clock pulse or the second gate clock bar pulse as the gate driving signal. Gate drive circuit. The method of claim 4, wherein The first stage of the odd stages and the first stage of the even stages The one start signal is input to the input terminal Gate drive circuit. A timing controller configured to generate an output enable signal, a gate clock, and one start signal in response to an external input signal; A level shifter generating a gate clock pulse in response to the output enable signal and a gate clock and generating one start pulse in response to the start signal; And A plurality of stages connected dependently to each other for outputting the gate clock pulse as a gate driving signal to be provided to a plurality of gate lines in response to the one start pulse, wherein an odd numbered stage of the plurality of stages is a carry terminal; Includes a first dummy stage connected to a control terminal of a last odd-numbered stage, the even-numbered stage of the plurality of stages includes a second dummy stage whose carry terminal is connected to a control terminal of the last-even-numbered stage, Output terminals of the second dummy stage provide first and second gate driving circuits to provide reset signals to the reset terminals of the plurality of stages. Liquid crystal display comprising a. The method of claim 6, wherein the second dummy stage And a pull-up transistor for providing the reset signal, wherein the pull-up transistor is larger in size than the pull-up transistor of another stage of the plurality of stages. Liquid crystal display. The method of claim 7, wherein the pull-up transistor of the second dummy stage 2 to 2.5 times larger than the pull-up transistor of the other stage of the plurality of stages Liquid crystal display. The method of claim 8, The gate clock pulse may include a first gate clock pulse, a first gate clock bar pulse having an inverted phase of a phase of the first gate clock pulse, a second gate clock pulse having a delayed phase of the first gate clock pulse, and a second gate clock. A second gate clock bar pulse having an inverted phase of the phase of the pulse, The odd-numbered stage outputs the first gate clock pulse or the first gate clock bar pulse as the gate driving signal, The even stage may output the second gate clock pulse or the second gate clock bar pulse as the gate driving signal. Liquid crystal display. The method of claim 9, The first stage of the odd-numbered stages and the first stage of the even-numbered stages have the one start signal input to an input terminal. Liquid crystal display. The method of claim 10, A power supply unit configured to supply the gate on voltage and the gate off voltage to the level shifter; The level shifter outputs the gate clock pulse, the gate clock bar pulse, and a start pulse having the gate on voltage and the gate off voltage levels. Liquid crystal display. The method of claim 11, wherein the level shifter, A first level shifting unit configured to logically operate the output enable signal and the gate clock, amplify a voltage level, and output the amplified voltage as the gate clock pulse; And And a second level shifting unit configured to logically operate the output enable signal and the gate clock, invert the phase, and amplify the voltage level to output the gate clock bar pulse. Liquid crystal display. The method of claim 12, wherein the first and second gate driving circuit, The gate line is integrated in the formed liquid crystal panel, and is formed across the gate line to dually drive the gate line. Liquid crystal display.

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