KR20080051793A - Dual-bit memory device and method manufacturing the same - Google Patents

Abstract

A dual bit memory device and a manufacturing method thereof are provided to reduce a standby power to be applied to store certain information by using a trap site that tunnels charge to be applied to a write word line. A bit line(20) having a desired thickness is formed in a first direction on a substrate(10) having a desired flat surface. A write word line(30) is extended in a second direction perpendicular to the bit line, and is isolated from the bit line. An electrode is electrically connected to the bit line on the write word line, and is bent towards the write word line. A read word line(40) is formed over the electrode, and is extended in the second direction in parallel with the write word line. A trap site(80) is independently formed at a portion in which the write word line crosses the read word line.

Description

Dual bit memory device and method for manufacturing same

1 is a cross-sectional view showing a memory device according to the prior art.

2 is a perspective view illustrating a dual bit memory device according to an exemplary embodiment of the present invention.

FIG. 3 is a cross-sectional view taken along line II of FIG. 2. FIG.

4 is a graph showing a relationship between a voltage applied through a bit line and a write word line and a refractive distance of a flip electrode of a dual bit memory device according to an exemplary embodiment of the present invention.

5 through 16 are process perspective views illustrating a method of manufacturing the dual bit memory device of FIG. 2.

Explanation of symbols on the main parts of the drawings

10 substrate 20 bit line

30: write word line 40: read word line

50: flip electrode 60: first sacrificial film

70: Second Sacrifice 80: Trap Site

100: trench

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device and a method of manufacturing the same, and in particular, a dual bit formed to write and read data only by switching operations of a plurality of flip electrodes symmetrically formed around a trench. A memory device and a method of manufacturing the same.

In general, memory devices used to store data may be classified into volatile memory devices and nonvolatile memory devices. In the memory device, first, a volatile memory device represented by DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory) has a characteristic of fast data input / output operation but loss of stored data when power supply is interrupted. On the other hand, nonvolatile memory semiconductor devices represented by EPROM (Erasable Programmable Read Only Memory) or EEPROM (Electrically Erasable Programmable Read Only Memory) are slow in input / output operation of data but retain stored data even when power supply is interrupted. There is this.

On the other hand, such a conventional memory device has been made by adopting a metal oxide semiconductor field effect transistor (MOSFET) based on the metal oxide semiconductor (MOS) technology. For example, a stacked gate transistor memory device having a structure stacked on a semiconductor substrate made of silicon and a trench gate transistor memory device having a structure embedded in the semiconductor substrate have been developed. However, in order to prevent the short channel effect, the MOSFET must have a channel width and length of more than a predetermined length, and the thickness of the gate insulating film formed between the gate electrode on the upper end of the channel and the semiconductor substrate is extremely thin. Due to the fundamental problem to be solved, it is difficult to implement a nanoscale ultra-fine memory device.

For this reason, researches on memory devices having structures capable of replacing MOSFETs have been actively conducted. Recently, micro electro-mechanical system (MEMS) technology and nano electro-mechanical system (NEMS) technology, which are being developed by applying semiconductor technology, are emerging. Among them, a memory device employing carbon nanotubes is a device having horizontally-arranged nanostructures in US Patent Application Publication No. 2004/0181630, and its manufacturing method (Devices having horizontally-disposed nanofabric articles and methods of making). Is disclosed.

Hereinafter, a memory device according to the related art will be described with reference to the accompanying drawings.

1 is a cross-sectional view showing a memory device according to the prior art.

As shown in FIG. 1, a conventional memory device includes a lower electrode 112 and an upper electrode 168 formed at a predetermined interval in parallel to each other, and between the lower electrode 112 and the upper electrode 168. Passed apart from each other, it is configured to include a nanotube piece 154 formed to store predetermined data while falling or contacting the lower electrode 112 or the upper electrode 168.

The lower electrode 112 is embedded in a cavity formed in the first interlayer insulating layer on the semiconductor substrate. For example, the lower electrode 112 is made of a conductive metal or a semiconductor material.

The upper electrode 168 is designed to have a constant vacant space 174 with the lower electrode 112 on the lower electrode 112. In this case, the upper electrode 168 is formed to be supported by a second interlayer insulating layer (not shown) formed on the first interlayer insulating layer 176.

The nanotube piece 154 passes through the center of the pore 174 formed between the lower electrode 112 and the upper electrode 168 and under the predetermined conditions, the lower electrode 112 or the upper electrode 168. It is formed to contact with). For example, the nanotube pieces 154 may be mounted on the nitride film formed on the first interlayer insulating layer 176 at both edges of the lower electrode 112 to be supported at a predetermined height from the lower electrode 112. Is formed. In addition, a charge opposite to the charge applied to the nanotube piece 154 is refracted and in contact with the lower electrode 112 or the upper electrode 168 to be applied. When the nanotube piece 154 is brought into contact with the lower electrode 112, the upper electrode 168 opposite to the lower electrode 112 has the same charge as that applied to the nanotube piece 154. Is applied. Thereafter, in order for the nanotube piece 154 to continuously contact the lower electrode 112, a predetermined charge must be applied to the lower electrode 112. Of course, when the nanotube piece 154 is in contact with the upper electrode 168, a charge opposite to the charge applied to the nanotube piece 154 is applied to the upper electrode 168, the nanotube A charge equal to the charge applied to the piece 154 is applied to the lower electrode 112.

Accordingly, the memory device according to the related art has a state in which the nanotube piece 154 is suspended between the lower electrode 112 and the upper electrode 168, and contacts the lower electrode 112 or the upper electrode 168. Data corresponding to one bit corresponding to each of the states may be stored.

However, the memory device according to the prior art has the following problems.

First, in the conventional memory device, the lower electrode 112 in contact with the nanotube fragment 154 to maintain the state in which the nanotube fragment 154 is in contact with the lower electrode 112 or the upper electrode 168. Alternatively, when a predetermined charge must be continuously supplied to the upper electrode 168 and the nanotube piece 154, the consumption of standby power increases and when the supply of the charge is stopped, the nanotube piece 154 Since a predetermined information corresponding to whether or not a contact can not be maintained, a nonvolatile memory device cannot be implemented.

Second, in the conventional memory device, when a predetermined current is applied while crossing the lower electrode 112 or the upper electrode 168, the nanotube piece 154, which is switched, is vertically moved to input and output only one bit of data. Because of this, there is a disadvantage that the integration of the device is reduced.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is to reduce standby power consumption for maintaining predetermined recorded information, and to ensure that certain information is not lost even without an externally supplied charge, thereby having dual A bit memory device and a method of manufacturing the same are provided.

Another object of the present invention is to provide a dual bit memory device capable of increasing or maximizing device integration by inputting and outputting two or more bits of data, and a method of manufacturing the same.

A dual bit memory device according to an aspect of the present invention for achieving the above object includes a substrate having a predetermined flat surface; A bit line formed on the substrate in a first direction and having a predetermined thickness; First and second write word lines insulated from the top of the bit lines, separated by trenches in the first direction, and formed in a second direction crossing the bit lines; Electrically connected to the bit line from both top of the first and second write word lines to respective sides, and having predetermined first and second lower voids on top of the first and second write word lines, respectively; First and second electrodes separated by the trench in the first direction and refracted in the direction of the first and second write word lines under a predetermined condition; The first and second electrodes are separated in the first direction by the trench and floated with first and second upper voids, respectively, in a second direction parallel to the first and second write word lines. First and second read word lines formed; And the first and second write word lines and the first and second separated from each other in the first direction by the trenches on the first and second write word lines below each of the first and second lower voids. The first and second write word lines may be formed independently of intersecting read word lines and may electrostatically fix the first and second electrodes refracted in the first and second write word lines. Or first and second trap sites for trapping a predetermined charge applied externally.

In addition, another aspect of the present invention, the substrate having a predetermined flat surface; A bit line formed on the substrate in a first direction and having a predetermined thickness; A write word line insulated from an upper portion of the bit line and formed in a second direction crossing the bit line; An electrode electrically connected to a bit line at an upper portion of the write word line, and formed to be refracted in a direction of the write word line under a predetermined condition while being supported with a predetermined lower void at an upper portion of the write word line; A read word line formed in a second direction parallel to the write word line, lifted with an upper gap at the top of the electrode; And the write word formed independently at a portion where the write word line and the read word line intersect on the write word line under the lower gap so as to electrostatically fix the electrode refracted in the write word line direction. A memory device comprising a trap site for trapping a predetermined charge applied from a line or external.

Further, another aspect of the present invention, forming a bit line in one direction on a substrate having a predetermined flat surface; Forming a first interlayer insulating film and a write word line in a direction crossing the bit line on the substrate on which the bit line is formed; Forming a trap site on the write word line where the write word line and the bit line intersect; Forming a first sacrificial layer on the trap site and the write word line; Forming a spacer on a sidewall of the stack comprising the first interlayer insulating film, the write word line, the trap site, and the first sacrificial film; Forming an electrode electrically connected to the bit line adjacent to the spacer and bypassing the outer peripheral surface of the spacer; Forming a second interlayer insulating layer covering an entire surface of the substrate and the bit line on which the electrode is formed and exposing the electrode on the stack; Forming a second sacrificial layer and a read word line on the electrode corresponding to the stack; Forming a third interlayer insulating layer covering the entire surface of the second sacrificial layer and the substrate on which the read word lines are formed and partially opening an upper portion of the center in the longitudinal direction of the read word lines; Forming a trench having a predetermined depth by sequentially removing the read word line, the second sacrificial layer, the electrode, the first sacrificial layer, and the write word line using the third interlayer insulating layer as an etching mask; And removing the first sacrificial layer and the second sacrificial layer through which sidewalls are exposed in the trench to form a gap between the first word line and the second word line, and supporting the electrode in the gap. A method of manufacturing a dual bit memory device is included.

Hereinafter, a dual bit memory device and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, only this embodiment to make the disclosure of the present invention complete, the scope of the invention to those skilled in the art It is provided to inform you. In the accompanying drawings, the thicknesses of the various films and regions have been emphasized for clarity, and may be present in direct contact with another layer or substrate when a layer is described as being on another layer or substrate, or between a third Layers may be present.

2 is a perspective view illustrating a dual bit memory device according to an exemplary embodiment of the present invention, and FIG. 3 is a cross-sectional view taken along line II of FIG. 2.

As illustrated in FIGS. 2 and 3, a plurality of bit lines 20 are formed in a first direction on a substrate 10 having a predetermined flat surface. In addition, a first interlayer insulating layer 22 is formed on the plurality of bit lines 20 in a second direction perpendicular to the plurality of bit lines 20. A first write word line 30A and a second write word line 30B which are separated by the trench 100 in the second direction and parallel to each other are formed on the first interlayer insulating film 22. And a first trap site 80A separated by the trench 100 in the second direction on top of each of the first write word line 30A and the second write word line 30B and parallel to each other; The second trap site 80B is formed. Here, the first trap site 80A and the second trap site 80B are only on the upper portion of the first write word line 30A and the second write word line 30B that cross the bit line 20. It is formed independently.

The first trap site 80A and the second are supported by the first lower void 90A and the second lower void 90B while being supported on top of each of the first trap site 80A and the second trap site 80B. The floating first electrode 50A and the second electrode 50B are formed at a predetermined height from the trap site 80B. Here, the first electrode 50A and the second electrode 50B each include a first curved portion and a second curved portion that extend in a horizontal direction parallel to the surface of the substrate. In addition, the first and second electrodes 50A and 50B extending in the vertical direction may be electrically connected to the bit line 20 through the first fixing part 51A and the second fixing part 51B. have. The ends of the first electrode 50A and the second electrode 50B are separated from each other by the trench 100.

Predetermined from the first electrode 50A and the second electrode 50B by the first upper void 92A and the second upper void 92B on the first electrode 50A and the second electrode 50B. The first read word line 40A and the second read word line 40B are formed to be raised at the height of. Here, the first read word line 40A and the second read word line 40B are separated from each other by the trench 100 and are separated from each other by the first trap site 80A and the second trap site 80B. It is formed in a 2nd direction from the top.

The first fixing part and the second fixing part of the first electrode 50A and the second electrode 50B may be formed by the first spacer 24A and the second spacer 24B of an insulating material. 30A) and the outer wall of the second write word line 30B and the outer wall of the first trap site 80A and the second trap site 80B. The first electrode 50A and the second electrode 50B at the upper portion of the bit line 20 to insulate the outer walls of the first electrode 50A and the second electrode 50B while being insulated from adjacent memory elements. A two-layered insulating film 26 having the same or similar height as that of is formed. A third interlayer insulating film 28 is formed on the second interlayer insulating film 26 to insulate the outer walls of the first read word line 40A and the second read word line 40B.

The unit cell 104 of the dual bit memory device according to the exemplary embodiment of the present invention may be divided into a first memory unit 102A and a second memory unit 102B around the trench 100. The first memory unit 102A and the second memory unit 102B, which neighbor each other in the first direction, electrically share one bit line 20 with each other. The first memory unit 102A and the second memory unit 102B of each of the unit cells 104 neighboring each other in the second direction electrically connect the first write word line 30A or the second write word line 30B, respectively. The first read word line 40A or the second read word line 40B may be electrically shared. The first trap site 80A and the second trap site 80B correspond to the first write word line 30A and the second write word line 30B, so that the first write word line 30A and the second write. It is formed on the word line 30B. The operation method of the dual bit memory device according to the exemplary embodiment of the present invention configured as described above will be described below.

The vertical ends of each of the first electrode 50A and the second electrode 50B are buried and supported by the second interlayer insulating film 26 and the third interlayer insulating film 28, and the horizontal ends thereof are the write word lines 30. Can be freely moved between the first lower gap 90A and the first upper gap 92A and the second lower gap 90B and the second upper gap 92B respectively formed between the first and second word lines 40. . In this way, since the vertical ends of the first electrodes 50A and the second electrodes 50B are fixed and the horizontal ends can be freely moved, the write word line 30 and the read word line ( The switching operation may be performed like the flip electrode 50 in the gap 84 formed in the 40. Accordingly, the first electrode 50A and the second electrode 50B are called cantilevered electrodes or flip electrodes 50. By controlling the position of the cantilever electrode 50 within the void, the flip electrode 50 causes contact with the trap site 80A or the read word line 40 or with the trap site 80A. It may be supported between the read word lines 40. Programs of the first memory unit 102A and the second memory unit 102B constituting the unit cell by controlling the voltage difference applied to the bit line, the write word line 30, and the read word line 40. , Deletion, writing, and reading can be performed.

In the dual bit operating method, each unit cell 104 includes a first memory unit 102A and a second memory unit 102B, each of which is simultaneously programmed. For example, a predetermined voltage is applied independently to the first write word line 30A and the second write word line 30B, and independently of the first read word line 40A and the second read word line 40B, respectively. By applying a predetermined voltage, the states of the first memory unit 102A and the second memory unit 102B can be programmed to be equal to each other to "1" or "0" at the same time, respectively, and the "1" state. And "0" can be programmed differently. Since the first memory unit 102A and the second memory unit 102B share one bit line 20 electrically, the write operation and the read operation of each state cannot be performed at the same time. Either of unit 102A and second memory unit 102B must occupy bit line 20 electrically at a given time. In the dual bit memory device, a program must be executed in the unit cell 104.

Accordingly, the dual bit memory device of the present invention is programmed to have the same state or the different state symmetrically on both sides about the trench 100, respectively, the first memory unit 102A and the second memory unit 102B. It is possible to increase or maximize the integration of the device because it is possible to input and output two bits of data with a single cell consisting of.

As described above, the trap sites 80 are stacked on the write word lines 30 and formed in the same or similar directions to each other, and have the same or similar line widths as the write word lines 30. For example, the trap sites 80 are formed such that a plurality of the trap sites 80 are separated in parallel with each other by the trench 100 formed on the first interlayer insulating film 22, similarly to the write word lines 30. In addition, the trap site 80 tunnels the charge applied through the write word line 30 into the inside of the predetermined thin film so that the trap is trapped, and always traps the trapped charge even when no charge is supplied from the outside. It is formed to be able to. For example, the trap site 80 may be formed of 'Oxide-Nitride (ONO) in which a first silicon oxide layer 82, a silicon nitride layer 84, and a second silicon oxide layer 86 formed on the write word line 30 are stacked. -Oxide) 'including a thin film having a structure. In this case, the first silicon oxide film 82 and the second silicon oxide film 86 are insulating films electrically insulating the silicon nitride film 84 between the write word line 30 and the flip electrode 50. In particular, the first silicon oxide film 82 is a tunnel insulating film formed to selectively tunnel electric charges according to the direction and magnitude of an electric field applied between the silicon nitride film 84 and the write word line 30.

For example, the silicon nitride film 84 may be electrically separated by the first silicon oxide film 82 and the second silicon oxide film 86, and may be charged through the first silicon oxide film 82 under a specific voltage or more. May be referred to as a floating electrode formed to flow in and out.

Accordingly, the dual bit memory device according to the embodiment of the present invention tunnels and charges the charge applied through the write word line 30, and confines the trapped charge even when the charge applied from the write word line 30 is removed. Since it is possible to equip the trap site 80 (bound) to electrically maintain the refractive direction of the flip electrode 50 formed on the trap site 80 corresponding to the write word line 30. Non-volatile memory designs are possible.

4 is a graph illustrating a relationship between a voltage applied through a bit line 20 and a write word line 30 and a refractive distance of a flip electrode 50 of a dual bit memory device according to an exemplary embodiment of the present invention. When a positive voltage of " V _pull-in " is applied between the line 20 and the write word line 30, the flip electrode 50 and the trap site 80 are brought closer to " 0 ". When the corresponding information is written and a voltage of "V _pull-out " having a negative value is applied between the bit line 20 and the write word line 30, the flip electrode 50 and the trap site 80 are applied. ) Are separated from each other and information corresponding to "1" may be recorded.

Here, the horizontal axis represents the magnitude of the voltage, and the vertical axis represents the distance Taggap that the flip electrode 50 is moved from the surface of the trap site 80 to the read word line 40. Accordingly, a positive voltage "V _pull-in " is applied to the flip electrode 50 and the write word line 30 connected to the bit line 20, or a "V _pull- " having a negative value. _When a voltage of " _out " is applied, the flip electrode 50 contacts or is spaced apart from the trap site 80 on the write word line 30 to correspond to one bit having a value of "0" or "1". Digital information may be recorded.

In this case, the voltage of the "V _pull-in " and the voltage of the "V _pull-out " may be determined by the following equation (2).

(Formula 2)

V = V _{B / L} -V _WWL

Here, "V" represents a voltage of "V _pull-in " or "V _pull-out ", "V _{B / L} " is a voltage applied to the bit line 20, and "V _WWL " Is the voltage applied to the write word line 30. At this time, the voltage of the "V _pull-in " has a positive value, the voltage of the "V _pull-out " has a negative value. For example, when the voltage of the "V _pull-in " and the absolute value of the voltage of "V _pull-out " are the same or similar to each other, when the information corresponding to the value of "0" is to be recorded, 1/2 "V _pull a voltage of _-in " is applied to the bit line 20 and a voltage of 1/2 " V _pull-out " is applied to the write word line 30 to contact the flip electrode 50 and the trap site 80. You can.

In addition, when information corresponding to "1" is to be recorded, the voltage of 1/2 "V _pull-out " is applied to the bit line 20 and the voltage of 1/2 "V _pull-in " is applied. The flip electrode 50 may be spaced apart from the trap site 80. Although not shown, the bit line 20, the write word line 30, and the read word line 40 to which the voltage of “V _pull-in ” or the voltage of “V _pull-out ” are not applied are grounded. It can be set to have.

A method of manufacturing a memory device according to the second exemplary embodiment of the present invention configured as described above is as follows.

5 to 16 are process perspective views illustrating a method of manufacturing the dual bit memory device of FIG. 2.

As shown in FIG. 5, first, a bit line 20 having a predetermined thickness is formed on the substrate 10 in a horizontal state. Here, the bit lines 20 are formed on the substrate 10 in parallel in one direction. For example, the bit line 20 may be a conductive metal film such as gold, silver, copper, aluminum, tungsten, tungsten silicide, titanium, titanium nitride, tantalum, or tantalum silicide formed by physical vapor deposition or chemical vapor deposition. It comprises a polysilicon film doped with an impurity. Although not shown, the bit line 20 may be formed on the entire surface of the substrate 10, or the photoresist pattern or the first hard mask may be shielded to have a predetermined line width on the polysilicon film. The film may be anisotropically etched by a dry etching method using the film as an etching mask film. For example, the reaction gas used in the dry etching method of the conductive metal film or the polysilicon film includes a strong acid gas in which sulfuric acid and nitric acid are mixed. In addition, the bit line 20 is formed to have a thickness of about 500 GPa and a line width of about 30 GPa to about 500 GPa.

As shown in FIG. 6, a first interlayer insulating film 22 having a predetermined line width and a write word line 30 are formed in the direction in which the bit lines 20 intersect. For example, the first interlayer insulating film 22 includes a silicon oxide film or a silicon nitride film formed to have a thickness of about 200 kPa to about 850 kPa by chemical vapor deposition. In this case, the first interlayer insulating film 22 and the write word line 30 may be formed to have a predetermined line width during subsequent first sacrificial film patterning. In addition, the first interlayer insulating layer 22 may function as an etch stop layer in a process of forming the trench 100 that subsequently separates the write word line 30 in the longitudinal direction. In addition, the write word line 30 is formed of gold, silver, copper, aluminum, tungsten, tungsten silicide, titanium, titanium nitride, And conductive metal films such as tantalum and tantalum silicide.

As shown in FIG. 7, a trap site 80 is formed on the write word line 30 which is replaced with the bit line 20. Here, the trap site 80 is a first silicon oxide film 82, a silicon nitride film 84, laminated with a thickness of about 30 kPa to about 200 kPa, respectively, by rapid heat treatment, atomic layer deposition, or chemical vapor deposition. The second silicon oxide film 86 is formed to have an 'ONO' structure. In addition, the trap site 80 of the write word line 30 to constrain (constrain) the electrode formed on the upper portion of the trap site 80 with an electrostatic force so as to intersect the write word line 30 later. The nodes must be formed in such a way that they are separated. Thus, the trap site 80 is formed independently on top of the write word line 30 where the write word line 30 and the bit line 20 intersect.

As shown in FIG. 8, a first sacrificial layer is formed on the trap site 80 and the write word line 30. For example, the first sacrificial film 60 may include a polysilicon film formed to have a thickness of about 50 kPa to about 150 kPa by atomic layer deposition or chemical vapor deposition. The first sacrificial layer 60, the trap site 80, the write word line 30, and the first interlayer insulating layer 22 may be formed to have a line width of about 30 μs to about 1000 μs. Although not shown, the first interlayer insulating layer 22 and the write word line 30 may be patterned to a predetermined line width when the first sacrificial layer is formed. That is, a first interlayer insulating film 22 and a conductive thin film are formed on the bit line 20, the polysilicon film is formed after the trap site 80 is patterned, and the polysilicon film has a predetermined line width. The first sacrificial layer may be patterned to form the first sacrificial layer, and the first interlayer insulating layer 22 and the write word line 30 may be formed in a stack having a predetermined line width together with the first sacrificial layer.

As shown in FIG. 9, spacers 24 are disposed on sidewalls of the stack including the first interlayer insulating layer 22, the write word line 30, the trap site 80, and the first sacrificial layer 60. Form. Here, the spacer 24 is formed on the substrate 10 to have a predetermined step, the first interlayer insulating layer 22, the write word line 30, the trap site 80, and the first sacrificial layer ( A flip electrode 50 formed subsequently on the sidewall of the stack of 60 may be insulated from the write word line 30. For example, the spacer 24 is formed of a silicon nitride film or a polysilicon film formed by a chemical vapor deposition method. In this case, the spacer 24 is anisotropically etched the silicon nitride film by a dry etching method having a silicon nitride film or a polysilicon film having a uniform thickness on the entire surface of the substrate 10 including the stack and excellent in vertical etching characteristics. Thereby self-aligning on the sidewalls of the stack. Here, when the spacer 24 is made of the silicon nitride film, the flip electrode 50 may be maintained at a predetermined distance from the sidewalls of the write word line 30 and the trap site 80. On the other hand, when the spacer 24 is formed of a polysilicon film, the spacer 24 may be subsequently removed together with the first sacrificial layer 60 to form voids. In this case, when the spacer 24 is made of the polysilicon film, the first sacrificial film (after the formation of the first interlayer insulating film 22, the write word line 30, and the trap site 80) may be formed. It may be formed by the same process as 60). For example, the spacer 24 forms the first interlayer insulating layer 22, the write word line 30, and the trap site 80 that intersect the bit line 20 on the bit line 20. A polysilicon film is formed on the entire surface of the substrate 10 on which the first interlayer insulating film 22, the write word line 30, and the trap site 80 are formed, and the first interlayer insulating film 22 is formed. And the first interlayer insulating layer 22 and the write word connected to the first sacrificial layer 60 formed of the write word line 30 and the polysilicon layer formed on the trap site 80. The polysilicon layer may be patterned to surround the line 30 and sidewalls of the trap site 80.

Although not shown, the first hard mask layer formed on the bit line 20 when the bit line 20 is formed may be removed by the reaction gas used in the dry etching method when the spacer 24 is formed. Thus, the bit line 20 may be exposed when the spacer 24 is formed.

As shown in FIG. 10, the spacer includes the first sacrificial layer 60, the write word line 30, and the first interlayer insulating layer 22. A flip electrode 50 is formed which is electrically connected to the bit line 20 adjacent to 24. Here, the flip electrode 50 bypasses the top of the stack with the center at the center corresponding to the bit line 20 formed at the bottom of the stack, so that the bit lines 20 are formed at both sides of the stack. It is formed to be electrically connected to. In this case, the flip electrode 50 has a line width that is the same as or similar to that of the bit line 20, and is formed to be stacked on the bit line 20 around the spacers 24 on both sides of the stack. For example, the flip electrode 50 may be formed on the front surface of the substrate 10 on which the stack and the spacers 24 are formed. A photoresist pattern or a second hard mask layer is formed on the line 20 to shield the conductive metal layer or the carbon nanotube. The conductive metal layer is a dry etching method using the photoresist pattern or the second hard mask layer as an etching mask. The film, or carbon nanotubes, is formed by anisotropic etching. In this case, the conductive metal film is formed by a physical vapor deposition method or a chemical vapor deposition method, the carbon nanotubes are formed by an electrical discharge method. In addition, the second hard mask layer may be removed when the flip electrode 50 is patterned, or may remain on the flip electrode 50.

As shown in FIG. 11, a second interlayer insulating layer 26 having a predetermined thickness is formed on the front surface of the substrate 10 on which the flip electrode 50 is formed, and the flip electrode 50 on the stack is exposed. The second interlayer insulating layer 26 is removed and planarized to be possible. Here, the second interlayer insulating layer 26 crosses the stack 10 of the write word line 30, the trap site 80, and the first sacrificial layer 60 having a predetermined step from the substrate 10. And the second sacrificial layer 70 and the read word line 40 are formed on the flip electrode 50 to be formed in the direction parallel to the stack. In addition, the second interlayer insulating layer 26 may be formed by separating the patterning process of the flip electrode 50 and the upper read word line 40. This is because the flip electrode 50 and the read word line 40 are made of a conductive metal film having excellent conductivity, and a select etch ratio of most etching solutions or reaction gases used for patterning the conductive metal film is low. to be. Accordingly, the second interlayer insulating layer 26 is essentially used in a process of separating and forming two stacked lines or patterns made of a conductive metal film. For example, the second interlayer insulating film 26 is formed of a silicon oxide film formed by a plasma chemical vapor deposition method. In this case, the second interlayer insulating layer 26 is formed to have a height greater than or equal to the flip electrode 50 on the entire surface of the substrate 10 on which the flip electrode 50 and the second hard mask layer are formed. In addition, the second interlayer insulating layer 26 may be removed and planarized by chemical mechanical polishing to expose the flip electrode 50 on the first sacrificial layer 60.

Accordingly, in the method of manufacturing the dual bit memory device according to the embodiment of the present invention, the second interlayer insulating layer 26 is formed on the entire surface where the flip electrode 50 is formed, and the write word line 30 and the first sacrificial layer 60 are formed. The second interlayer insulating layer 26 may be planarized to expose the flip electrode 50 formed on the upper surface of the substrate 100 so that the subsequent second sacrificial layer 70 and the read word line 40 may be patterned.

As shown in FIG. 12, the first sacrificial layer 60, the trap site 80, and the write word line are disposed on the flip electrode 50 exposed by the second interlayer insulating layer 26. The second sacrificial film 70 and the read word line 40 are formed in a direction parallel to the reference numeral 30. Here, the second sacrificial layer 70 and the read word line 40 may be formed around the flip electrode 50, the first sacrificial layer 60, the trap site 80, and the write word line 30. Is formed symmetrically. For example, the second sacrificial layer 70 is made of a polysilicon material formed by an atomic layer deposition method or a chemical vapor deposition method similarly to the first sacrificial layer 60, and is formed to have a thickness of about 50 GPa to about 150 GPa. do. In addition, the read word line 40 is formed to have a thickness of about 200 mW and a line width of about 30 mW to about 1000 mW. In this case, the second sacrificial layer 70 and the read word line 40 may be formed as follows. First, a polysilicon film, a conductive metal film, and a third hard mask film 42 having a predetermined thickness are laminated on the second interlayer insulating film 26 by a chemical vapor deposition method. Next, a photoresist pattern is formed to shield the first sacrificial layer 60 and the third hard mask layer 42 on the write word line 30, and the photoresist pattern is used as an etching mask. After removing the third hard mask layer 42 by an etching method or a wet etching method, the photoresist pattern is removed by an ashing process. Lastly, the polysilicon film and the conductive metal film are anisotropically etched by a dry etching method or a wet etching method using the third hard mask layer 42 as an etching mask, and the second sacrificial layer 70 and the read word line. 40 may be formed.

As shown in FIG. 13, the third hard mask layer 42 formed on the read word line 40 is reduced and patterned to a predetermined line width. Here, the patterned third hard mask layer 42 subsequently defines the line width of the trench 100. For example, the third hard mask layer 42 may be anisotropically formed by a dry etching method or a wet etching method using an etching mask on a photoresist pattern formed to shield a center in the longitudinal direction of the read word line 40 formed in one direction. May be etched to reduce the line width. In addition, the third hard mask layer 42 may be formed to be isotropically etched by a dry etching method or a wet etching method which has better etching characteristics in the lateral direction than in the planar direction to reduce the line width. In this case, the reaction gas or the etching solution used in the isotropic dry etching method or the wet etching method may selectively etch the side surface of the third hard mask layer 42 while flowing in a direction parallel to the substrate 10. .

As shown in FIG. 14, a third interlayer insulating film 28 having a predetermined thickness is formed on the third hard mask film 42 having a reduced line width, and the third hard mask film 42 is exposed. The interlayer insulating film 28 is planarized. The third interlayer insulating layer 28 may be formed to have a thickness greater than or equal to the second sacrificial layer 70 and the read word line 40. Therefore, when the second sacrificial layer 70 is subsequently removed, the third interlayer insulating layer 28 supports the side surface of the read word line 40 to support the read word line 40 from the flip electrode 50. Can be raised to support. For example, the third interlayer insulating film 28 includes a silicon oxide film formed by a plasma chemical vapor deposition method. In addition, the third interlayer insulating film 28 may be planarized by a chemical mechanical polishing method. In this case, when the third interlayer insulating layer 28 is planarized by using the read word line 40 as an etch stop layer, the read word line 40 made of a conductive metal film may be damaged. The hard mask film 42 should be used as an etch stop film.

 As illustrated in FIG. 15, the third hard mask layer 42, the read word line 40, and the second sacrificial layer may be formed using a dry etching method using a third interlayer insulating layer 28 as an etching mask. 70, the flip electrode 50, the first sacrificial layer 60, the trap site 80, and the write word line 30 are sequentially anisotropically etched to form the first interlayer insulating layer 22. ) Forms a trench 100 that is exposed at the bottom. The trench 100 may include the read word line 40, the second sacrificial layer 70, the flip electrode 50, the first sacrificial layer 60, and the write word line 30. It is formed to be symmetrically separated into a plurality. The trench 100 is a dry etching method using a reaction gas having a high selectivity of polysilicon and a conductive metal film corresponding to the third interlayer insulating film 28 and the first interlayer insulating film 22 formed of a silicon oxide film. It can be formed by. For example, the reactive gas used in the dry etching method may be a fluorinated carbon-based gas such as a CxFy-based gas or a CaHbFc-based gas. The fluorinated carbonaceous gas includes a gas such as CF4, CHF3, C2F6, C4F8, CH2F2, CH3F, CH4, C2H2, C4F6, or a mixture thereof. When the width of the trench 100 is reduced, interference between the neighboring write word line 30, the read word line 40, and the flip electrode 50 may occur. In addition, an etching solution or a reaction gas for etching the first sacrificial layer 60 and the second sacrificial layer 70 may not normally flow through the trench 100. On the other hand, when the width of the trench 100 is wider, the degree of integration of the unit device may be reduced, but the etching solution or reaction gas for etching the first sacrificial layer 60 and the second sacrificial layer 70 is excellent. Can be flowed. Accordingly, the trench 100 symmetrically separates the write word line 30, the flip electrode 50, and the read word line 40, and between the write word line 30 and the flip electrode 50. An etchant or reaction gas for removing the first sacrificial layer 60 and the second sacrificial layer 70 between the flip electrode 50 and the read word line 40 may have a line width through which a normal flow may be performed. Is formed. For example, the trench 100 is formed to have a line width of about 30 kPa to about 800 kPa.

Although not shown, when the process of reducing the line width of the third hard mask layer 42 is omitted, a third interlayer insulating layer formed in the center of the longitudinal direction of the read word line 40 and the write word line 30 ( 28, the third hard mask layer 42, the read word line 40, the second sacrificial layer 70, and the flip electrode may be formed by a dry etching method using a photoresist pattern exposing the photoresist pattern as an etching mask. 50, the first sacrificial layer 60, the trap site 80, and the write word line 30 may be sequentially anisotropically etched to form the trench 100.

As illustrated in FIG. 16, the write word line 30 and the read word line are removed by removing the first sacrificial layer 60 and the second sacrificial layer 70 exposed by the trench 100. The gaps 40 form a predetermined gap in which the flip electrode 50 is supported. For example, the first sacrificial layer 60 and the second sacrificial layer 70 are isotropically etched and removed from the side exposed from the sidewalls of the trenches 100 and 82 by a wet etching method or a dry etching method. Can be. The etching solution used in the wet etching method of the first thin film 60 and the second sacrificial layer 70 made of polysilicon is made of deionized water in a strong concentration such as nitric acid, hydrofluoric acid, and acetic acid. It consists of a mixed solution mixed. The etching solution or reaction gas used in the wet etching method or the dry etching method removes the first sacrificial layer 60 and the second sacrificial layer 70 exposed from the sidewall of the trench 100 in a horizontal direction. The gap may be formed between the read word line 40 and the write word line 30. When the spacer 24 is formed of a polysilicon material, the spacer 24 may also be etched by the etching solution or the reaction gas to form voids. At this time, when the distance of the gap formed by removing the spacer 24 is significantly smaller than the gap distance between the write word line 30 and the flip electrode 50, the flip electrode 50 is the write word. Rather than being in electrical contact at the top of the line 30, it is in electrical contact at the side of the write word line 30, resulting in poor writing and reading of information. Therefore, when the spacer 24 is removed, the distance between the top of the write word line 30 and the flip electrode 50 is equal to the distance between the side of the write word line 30 and the flip electrode 50. It is largely formed.

Although not shown, a fourth interlayer insulating layer covering the upper end of the trench 100 is formed to seal the inside of the trench 100. In this case, the voids in the trench 100 may be filled with nitrogen or argon in the atmosphere and a non-reactive gas, and may be set to have a vacuum state to increase the refractive rate of the flip electrode 50. In addition, another bit line 20, a write word line 30, a flip electrode 50, and a read word line 40 are sequentially formed on an upper portion of the substrate 10 on which the fourth interlayer insulating layer is formed. Thus, a memory device having a multilayer structure can be manufactured.

Accordingly, in the method of manufacturing a dual bit memory device according to an exemplary embodiment of the present invention, a plurality of write words are formed by using trenches 100 formed in an intersecting direction on top of the bit lines 20 formed in one direction on the substrate 10. Since the line 30, the flip electrode 50, and the read word line 40 can be formed symmetrically, the integration degree of the device can be improved.

In addition, the description of the above embodiment is merely given by way of example with reference to the drawings in order to provide a more thorough understanding of the present invention, it should not be construed as limiting the present invention. In addition, for those skilled in the art, various changes and modifications may be made without departing from the basic principles of the present invention.

As described above, according to the present invention, there is provided a trap site for tunneling charge applied to a write word line so as to trap, and for maintaining a curved state of a flip electrode using the trapped charge to store predetermined information. Since it is possible to reduce the consumption of standby power to be applied in order to prevent the loss of predetermined information without the charge supplied through the write word line, it is possible to implement a nonvolatile memory device.

In addition, a single cell consisting of a first memory unit and a second memory unit programmed to have the same or different states symmetrically on both sides with respect to the trench can input and output two bits of data. Therefore, there is an effect that can increase or maximize the degree of integration of the device.

Claims (17)

A substrate having a predetermined flat surface; A bit line formed on the substrate in a first direction and having a predetermined thickness; A write word line insulated from an upper portion of the bit line and formed in a second direction crossing the bit line; An electrode electrically connected to a bit line at an upper portion of the write word line, and formed to be refracted in a direction of the write word line under a predetermined condition while being supported with a predetermined lower void at an upper portion of the write word line; A read word line formed in a second direction parallel to the write word line, lifted with an upper gap at the top of the electrode; And The write word line is formed independently of a portion where the write word line and the read word line intersect on the write word line below the lower gap so as to electrostatically fix the electrode refracted in the write word line direction. Or a trap site for trapping a predetermined charge applied from the outside. The method of claim 1, The trap site may include a stack of a first silicon oxide film, a silicon nitride film, and a second silicon oxide film. The method of claim 1, A first interlayer insulating film formed between the bit line and the write word line, a second interlayer insulating film insulating the outer side of the electrode, and fixing the electrode to support the lower void in the upper portion of the trap site; And a third interlayer insulating layer formed on the second interlayer insulating layer, the third interlayer insulating layer supporting the read word line above the upper gap of the electrode. The method of claim 2 or 3, And a spacer insulating said electrode from sidewalls of said first interlayer insulating film, said write word line, said trap site, and said lower void. A substrate having a predetermined flat surface; A bit line formed on the substrate in a first direction and having a predetermined thickness; First and second write word lines insulated from the top of the bit lines, separated by trenches in the first direction, and formed in a second direction crossing the bit lines; Electrically connected to the bit line from both top of the first and second write word lines to respective sides, and having predetermined first and second lower voids on top of the first and second write word lines, respectively; First and second electrodes separated by the trench in the first direction and refracted in the direction of the first and second write word lines under a predetermined condition; The first and second electrodes are separated in the first direction by the trench and floated with first and second upper voids, respectively, in a second direction parallel to the first and second write word lines. First and second read word lines formed; And The first and second write word lines and the first and second readouts being separated from each other in the first direction by the trenches on the first and second write word lines below each of the first and second lower voids. The first and second write word lines may be formed independently at portions where word lines cross each other, and may be used to electrostatically fix the first and second electrodes refracted in the first and second write word lines. And a first and second trap site for trapping a predetermined charge applied from the outside. The method of claim 5, wherein And the first and second trap sites each include a first silicon oxide film, a silicon nitride film, and a second silicon oxide film stacked thereon. The method of claim 5, wherein A first interlayer insulating film formed between the bit line and the first and second write word lines, and an outer side of the first and second electrodes, and the first and second lower voids. A second interlayer insulating film which fixes the first and second electrodes so that the electrode is supported, and an upper portion of the second interlayer insulating film, the upper part of the first and second upper voids above the first and second electrodes And a third interlayer insulating film supporting the first and second read word lines. The method according to claim 6 or 7, A spacer for insulating the first and second electrodes from the first interlayer insulating film, the first and second write word lines, the first and second trap sites, and the outer walls of the first and second lower voids. Dual bit memory element characterized by containing. The method of claim 5, wherein The stack is formed between the first and second write word lines and the first and second read word lines to form the first and second lower voids and the second and second upper voids, and then And a first sacrificial layer and a second sacrificial layer, wherein the sidewalls exposed by the trench are removed by an etching solution or a reaction gas. The method of claim 13, And the first and second sacrificial layers include a polysilicon layer. Forming a bit line in one direction on a substrate having a predetermined flat surface; Forming a first interlayer insulating film and a write word line in a direction crossing the bit line on the substrate on which the bit line is formed; Forming a trap site on the write word line where the write word line and the bit line intersect; Forming a first sacrificial layer on the trap site and the write word line; Forming a spacer on a sidewall of the stack comprising the first interlayer insulating film, the write word line, the trap site, and the first sacrificial film; Forming an electrode electrically connected to the bit line adjacent to the spacer and bypassing the outer peripheral surface of the spacer; Forming a second interlayer insulating layer covering an entire surface of the substrate and the bit line on which the electrode is formed and exposing the electrode on the stack; Forming a second sacrificial layer and a read word line on the electrode corresponding to the stack; Forming a third interlayer insulating layer covering the entire surface of the second sacrificial layer and the substrate on which the read word lines are formed and partially opening an upper portion of the center in the longitudinal direction of the read word lines; Forming a trench having a predetermined depth by sequentially removing the read word line, the second sacrificial layer, the electrode, the first sacrificial layer, and the write word line using the third interlayer insulating layer as an etching mask; And Removing the first sacrificial layer and the second sacrificial layer through which sidewalls are exposed in the trench to form a gap between the first word line and the second word line, and supporting the electrode in the gap. A method of manufacturing a dual bit memory device, characterized in that. The method of claim 11, wherein Forming the first interlayer insulating film, the write word line, and the trap site on the substrate, selectively patterning the trap site on the write word line above the bit line, and on the trap site and the write word line. Forming a stack of the first sacrificial layer, the trap site, and the write word line having a predetermined line width in a direction crossing the bit line; Method of manufacturing a dual bit memory device. The method of claim 11, wherein The second sacrificial film and the read word line form a polysilicon film and a conductive metal film having a predetermined thickness on an entire surface of the semiconductor substrate on which the flip electrode and the second interlayer insulating film are formed, and the first sacrificial film and the Forming a hard mask film that shields the conductive metal film corresponding to the write word line, and performing anisotropically etching the polysilicon film and the conductive metal film by a dry etching method or a wet etching method using the hard mask film as an etching mask. A method of manufacturing a dual bit memory device, characterized in that. The method of claim 13, And forming the hard mask layer to have a line width smaller than that of the read word line. The method of claim 14, The third interlayer insulating film is formed by forming a silicon oxide film to bury the hard mask film on the entire surface of the substrate, and removing the silicon oxide film so as to have a flat surface to which the hard mask film is exposed. Manufacturing method. The method of claim 15, The trench may include the hard mask layer, the second word line, the second sacrificial layer, the flip electrode, and the first sacrificial layer using the etch mask layer as the third interlayer insulating layer and the etch stop layer as the first interlayer insulating layer. And forming the first word line sequentially anisotropically etched. The method of claim 11, wherein And the first and second sacrificial layers are wet-etched using a mixed solution in which deionized water is mixed with a strong acid such as nitric acid, hydrofluoric acid, and acetic acid at a predetermined concentration as an etching solution. Manufacturing method.

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