KR20080036680A - Method and device for controlling synchronizing signal - Google Patents

Abstract

A method and an apparatus for controlling a synchronization signal are provided to add appended data to image data when the image data processed in an image processing unit is outputted, thereby preventing the damage of the image data which is to be inputted to a post-processing processor. An image signal processor(310) receives original data from an image sensor(110) and converts the original data into image data in correspondence to a predetermined format. A memory(320) stores the image data. An output controller(330) adds appended data to the image data and delays and outputs the output section of a clock signal corresponding to pixel data to which the appended data is added.

Description

Method and device for controlling synchronizing signal

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram schematically showing a configuration of a general imaging device.

2 is a diagram illustrating a typical Bayer mosaic filter pattern.

3 is a block diagram schematically illustrating an internal configuration of an image processing unit according to an exemplary embodiment of the present invention.

4 illustrates a waveform of a horizontal input output from an image signal processor in accordance with the prior art.

FIG. 5 illustrates waveforms of a horizontal input output from an image signal processor in accordance with one preferred embodiment of the present invention. FIG.

6 is a flowchart illustrating a method of controlling a synchronization signal by an image processor according to an exemplary embodiment of the present invention.

7 is a block diagram schematically illustrating an internal configuration of an image processing unit according to another exemplary embodiment of the present invention.

8 is a flowchart illustrating a method of controlling a synchronization signal by an image processing unit according to another embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

310: image signal processor

320: memory

330: output controller

The present invention relates to pixel data output, and more particularly, to a method and apparatus for controlling an output synchronization signal for accurate processing of pixel data.

In recent years, small and thin image pickup devices are mounted in small and thin portable terminals such as mobile phones and PDAs (Personal Digital Assistants), whereby the portable terminals can function as image pickup devices. The user can transmit not only voice information but also image information to a remote location using the portable terminal. The imaging device is provided not only in a mobile phone or a PDA but also in a portable terminal such as an MP3 player so that various devices can hold external images as electronic data.

Generally, solid-state imaging devices, such as a charge coupled device (CCD) type image sensor and a complementary metal-0xide semiconductor (CMOS) type image sensor, are used for such an imaging device.

FIG. 1 is a diagram schematically illustrating a configuration of a general imaging device, and FIG. 2 is a diagram illustrating a general Bayer mosaic filter pattern.

As illustrated in FIG. 1, an image pickup device that converts an external image into electrical data and displays the same on the display unit 150 includes an image sensor 110, an image signal processor 120 (ISP), and a backend chip ( 130, a back-end chip, a baseband chip 140, and a display unit 150. In addition, the imaging apparatus may further include a memory for storing the converted electrical data, an AD converter for converting an analog signal into a digital signal, and the like.

The image sensor 110 generally includes a Bayer pattern, and outputs raw data corresponding to the amount of light input through the lens for each unit pixel. In order to detect the color of the image exposed to the image sensor 110, a pixel of the image sensor 110 to each color filter absorbing the light wavelength of all colors except the color of the color filter. It is covered.

That is, a general method of obtaining color information from the image sensor 110 is to arrange a color filter array (CFA) on the pixels of the image sensor 110. The most common form of color filter array is the Bayer Mosaic filter shown in FIG. The Bayer mosaic filter has a checkerboard like structure and consists of alternating rows of red (R), green (G) and blue (B), green (G) filters. The red and green filters are offset from each other so that the two green filters do not share the edge between adjacent rows and columns. In order to obtain complete color information of each pixel, interpolation based on color intensity of surrounding pixels is required.

The image signal processor 120 converts an electrical signal (raw data) input from the image sensor 110 into a YUV value, and inputs the converted YUV value to the back end chip 130. The YUV method focuses on the fact that the human eye is more sensitive to brightness than color, and the color is divided into Y component, which is luminance, and U and V, which are chroma. Since the Y component is sensitive to error, we code more bits than the color components U and V. A typical Y: U: V ratio is 4: 2: 2.

The image signal processor 120 sequentially stores the converted YUV values in the FIFO so that the back end chip 130 may receive the corresponding information.

The back end chip 130 converts the input YUV value into JPEG or BMP by using a predetermined encoding method and stores the converted YUV value in a memory (not shown), or decodes the encoded image stored in the memory and displays it on the display unit 150. The back end chip 130 may also perform functions such as enlargement, reduction, and rotation of an image. Of course, as shown in FIG. 1, the baseband chip 140 may receive decoded data from the backend chip 130 and display the decoded data on the display unit 150.

The baseband chip 140 performs a function of controlling the overall operation of the imaging device. For example, when an imaging command is input from a user through a key input unit (not shown), the baseband chip 140 transmits an image generation command to the backend chip 130 to the external image to which the backend chip 130 is input. It is also possible to generate corresponding encoded data.

The display unit 150 displays decoded data provided by the control of the back end chip 130 or the baseband chip 140.

The image data signal and the synchronization signal (ie, the clock signal) output through the image signal processor 120 in the image capturing apparatus are related to whether the effective pixel is determined. That is, an image to be inputted and outputted during a valid period of a synchronization signal (clock signal) between the image signal processor 120 and the post-processing processor (for example, the back end chip 130) that processes the image data input from the image signal processor 120. The number and order of data are predetermined. Therefore, when the relationship between the image data output from the image signal processor 120 and the synchronization signal is broken, the post-processing processor processes a completely different signal.

In general, as the synchronization signal (ie, the clock signal) is delayed by one cycle due to the distance between the image signal processor 120 and the post-processing processor (for example, the back end chip 130, etc.) in the imaging device. A slowing problem occurred. As a result, the post-processing processor may not properly receive the image data output through the image signal processor 120.

Accordingly, an object of the present invention for solving the above-described problem is an output synchronization signal control method capable of suppressing corruption of image data input by a post-processing processor by adding extra data in outputting image data processed by an image processing unit. And to provide an apparatus.

Another object of the present invention is to extend the output section of the clock signal corresponding to the free data added to the image processing unit by controlling the output synchronization signal that can enable the post-processing processor to acquire the image data stably without modification of the post-processing processor It is to provide a method and apparatus.

Other objects of the present invention will be easily understood through the description of the following examples.

In order to achieve the above object, according to an aspect of the present invention, an image processor capable of delaying the output period of the clock signal corresponding to the pixel data to which the extra data is added and outputted by adding the extra data to the image data; Chips are provided.

According to an exemplary embodiment of the present invention, an image signal processor for receiving raw data from an image sensor and converting the raw data into image data corresponding to a predetermined format; A memory for storing the image data; And an output controller that adds margin data to the image data and delays an output section of a clock signal corresponding to the pixel data to which the margin data is added.

The output controller may cause the clock signal corresponding to the pixel data to be delayed and output in correspondence to the number of the extra data.

The spare data may be data superimposed preliminarily by the best pixel data of the image data read from the memory on a line-by-line basis, and superimposed on the last pixel data by the following.

The output controller extracts the image data stored in the memory in units of lines, adds k (random natural numbers) of the lines of leading data by m (random natural numbers), and adds n (random natural numbers) of the lines. ) Final data can be added after p by an arbitrary number of natural numbers.

According to another preferred embodiment of the present invention, the image signal processor for receiving the raw data from the image sensor and converts the image data to a corresponding format; A memory for storing the image data; An output controller that reads the image data, adds spare data to write to the memory, and outputs an output command of the image data to which the spare data is added; And a data output unit configured to read and output image data to which the margin data is added in response to the output command from the memory, wherein the output controller delays an output period of a clock signal corresponding to the pixel data to which the margin data is added. The image processor chip may be provided to be output.

According to another preferred embodiment of the present invention, the image signal processor for receiving the raw data from the image sensor and converts it into image data in a predetermined format; A memory for storing the image data; An output controller for outputting the image data read command; And a data output unit configured to read the image data from the memory in response to the read command, output the best pixel data as spare data, and output image data and sequentially output the last pixel data as spare data. The output controller may be provided with an image processor chip which delays an output period of a clock signal corresponding to pixel data to which the margin data is added.

The data output unit extracts image data stored in the memory in units of lines, adds k (random natural numbers) of the best pixel data of the line by m (random natural numbers), and adds n (arbitrary) of the lines. Last pixel data may be added after p by an arbitrary natural number.

The spare data information to be added is information on the number of spare data to be added, and the output controller may delay and output an output period of the clock signal in response to the spare data information to be added.

According to another aspect of the present invention, a method of controlling a synchronization signal in an image processor chip is provided.

According to an embodiment of the present invention, a method of controlling a synchronization signal in an image processor chip, the method comprising: receiving raw data from an image sensor and converting the image data into a corresponding format; Adding spare data to the image data; And delaying the output period of the clock signal corresponding to the pixel data to which the margin data is added may be provided.

In the adding of the spare data to the video data, k (arbitrary natural numbers) of the video data are added in advance by m (arbitrary natural numbers) and n (random natural numbers) of the video data. Last pixel data can be added after p by an arbitrary natural number.

The delaying and outputting of the output period of the clock signal corresponding to the pixel data to which the spare data is added may include delaying and outputting the output period of the clock signal corresponding to the image data according to the number of the added pixel data. Can be.

According to another preferred embodiment of the present invention, a method for controlling a synchronization signal in an image processor chip, the method comprising: receiving raw data from an image sensor and converting the raw data into image data corresponding to a predetermined format; Adding spare data to the video data and recording the same in a memory; Delaying and outputting an output period of a clock signal corresponding to the pixel data to which the margin data is added; Transmitting an output command indicating an output of the image data to which the redundant data is added; And reading and outputting image data to which the margin data is added in response to the output command from the memory, wherein the clock signal corresponds to an output section of the image data among the image data to which the margin data is added. A synchronization signal control method may be provided which is delayed to be output.

The outputting of the clock signal corresponding to the pixel data to which the spare data is added may be delayed and output. The output period of the clock signal may be delayed and output according to the spare data information to be added.

The step of reading and outputting image data to which the spare data is added in response to the output command from the memory includes extracting image data stored in the memory in units of lines and selecting k (random natural numbers) of the lines. The data can be added after m (random natural number), and the n (arbitrary natural number) last pixel data of the line can be added after p (random natural number) and output.

According to still another aspect of the present invention, there is provided an image pickup apparatus capable of delaying and outputting an output section of a clock signal corresponding to pixel data to which extra data is added and outputting image data.

According to a preferred embodiment of the present invention, the image sensor for outputting the raw data corresponding to the external image; An image signal processor for receiving the raw data and converting the raw data into image data in a predetermined format; A memory for storing the converted image data; And an output controller which adds margin data to the image data and delays an output section of a clock signal corresponding to the pixel data to which the margin data is added.

The output controller may cause the clock signal corresponding to the pixel data to be delayed and output in correspondence to the number of the extra data.

The output controller extracts image data stored in the memory in units of lines, adds k (random natural numbers) of the best pixel data of the line by m (random natural numbers), and adds n Last pixel data can be added after and output by p (random natural number).

According to another preferred embodiment of the invention, the image sensor for outputting the raw data corresponding to the external image; An image signal processor for receiving the raw data and converting the raw data into image data in a predetermined format; A memory for storing the converted image data; An output controller that reads the image data, adds spare data to write to the memory, and outputs an output command of the image data to which the spare data is added; And a data output unit configured to read and output image data to which the margin data is added in response to the output command from the memory, wherein the output controller delays an output period of a clock signal corresponding to the pixel data to which the margin data is added. And an image pickup device can be provided.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. Hereinafter, the same reference numerals are used for the same components in the drawings, and duplicate descriptions of the same components are omitted. In addition, in describing the present invention, when it is determined that the detailed description of the related known technology may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

3 is a block diagram schematically illustrating an internal configuration of an image processing unit according to an exemplary embodiment of the present invention. FIG. 4 is a diagram illustrating a waveform of a horizontal input output from an image signal processor according to the prior art. 5 is a diagram illustrating a waveform of a horizontal direction input to an image signal processor according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the image processor 310 according to the present invention includes an image signal processor 120, a memory 320, and an output controller 330. Here, the image processor 310 may be formed of one chip.

The image signal processor 120 processes raw data input from the image sensor 110 and stores the processed image data in the memory 320. For example, the image signal processor 120 may convert the raw data input from the image sensor 110 into YUV data and output the converted YUV data. Hereinafter, for convenience of description, the data generated by image processing the raw data input from the image sensor 110 by a predetermined method will be referred to as "image data". do.

For example, when the image signal processor 120 further includes an encoding unit (eg, a JPEG encoder), the image signal processor 120 may store JPEG encoded data in the memory 320.

The memory 320 stores image data processed by the image signal processor 120. The memory 320 may consist of n line memories of any natural number, for example, any number of lines from 1 to 1 frame.

For example, assuming that two line memories are included, image data of odd lines of a specific frame may be sequentially stored in the first line memory, and image data of even lines may be sequentially stored in the second line memory. Can be. Then, the image data output from the image signal processor 120 may be overwritten in the previously stored line memory and stored. Here, the pre-stored data may be output to the post-processing processor (not shown) by the control of the output controller 330 before being overwritten by the newly input image data.

The output controller 330 reads image data recorded in the memory 320 in units of lines or pixels, and adds extra data (hereinafter, referred to as "output image data" for convenience). (Not shown, for example, back-end chip).

For example, when the output controller 330 outputs image data corresponding to each line to the post-processing processor, the first pixel data corresponding to the value set in the register (not shown) is preliminarily added to the redundant data. It will be called. Here, the register may be included in the output controller 330. Of course, it may be included in the image processor 310 according to the implementation method. In addition, the data that follows and overlaps the last pixel data corresponding to the value set later may also be referred to as spare data. Of course, depending on the design method, in outputting the image data to the post-processing processor, it is obvious that a plurality of pixel data may be added before and after the image data as spare data, respectively. As described above, in the present specification, redundant or redundant data will be collectively referred to as spare data.

In addition, the output controller 330 may delay the output period of the clock signal of the image data to which the spare data is added and output the post-processor. The output controller 330 may include one or more registers (not shown, i.e., registers that record the number of spare data to be added before the first pixel data and the last pixel data) to be updated to correspond to the number of spare data to be added to the image data. And a register which records the number of spare data to be added later. Therefore, the output controller 330 may delay and output the output period of the clock signal of the video data to which the spare data is added using the value set in the corresponding register.

4 and 5, O_PCLK represents a clock signal, O_HREF represents a valid horizontal line signal, and DATA represents an output state of raw data output from the image sensor 110. Image data for one pixel is input in one cycle (i.e., one cycle) of O_PCLK, and one of the frames while O_HREF is high (may be low depending on implementation, of course). Image data of the number of pixels corresponding to a line may be output by the control of the output controller 330 through the image signal processor 120. In the following description, it is assumed that new image data is to be input by the clock signal O_PCLK. Of course, depending on the implementation method may be implemented to be detected by the falling edge (falling edge).

For example, referring to FIG. 5, in outputting the image data corresponding to each line to the post-processing processor, the output controller 330 adds the first data as many as k (random natural numbers) in advance, and ends the most. Data may be added after the m (arbitrary natural number) and output to the post-processing processor. Here, k and m may be the same or different values that are preset or specified by the user. Therefore, the output controller 330 may read the values (eg, k, m) set in the corresponding register and add the spare data to the image data. For example, assuming that the values corresponding to k and m set in the register are 1, and the image data is, for example, A, B, C, D, E, F, the output controller 330 ) Adds the first pixel data one time before, and adds the last pixel data one time and consequently adds A, A, B, C, D, E, F, and F as illustrated in FIG. The same output image data may be sequentially output to the post-processing processor. In the present specification, the description has been made on the assumption that the types of extra data added are 1, respectively, but may be 2 or more (for example, A, B, A, B, C, D, E, F, E, F, etc.). Naturally, the processor may add different data. In this case, the redundant description thereof will be omitted.

In addition, the output controller 330 may delay and output an output period of a clock signal corresponding to the added spare data. That is, as illustrated in FIG. 5, the output controller 330 delays the output section of the clock signal corresponding to the first pixel data (see 510) and delays the output section of the clock signal corresponding to the last pixel data. Can be output (see 520).

For example, suppose that pixel data is input every one period of the clock signal (i.e., every time the rising edge is input), and assume that the value set in the register is 1, for example, corresponding to the spare data to be added. . The output controller 330 may delay the output period of the clock signal of the pixel data to which the spare data is added by one cycle. As a result, the output period of the clock signal corresponding to the pixel data to which the spare data is added may be obtained as if the delay is performed. If it is assumed that two pieces of spare data are added, the output controller 330 may delay the output period of the clock signal of the pixel data to which the spare data is added by two cycles.

Referring to 510 and 520 of FIG. 5, it can be seen that the output section of the pixel data to which respective spare data is added is delayed. Through this, even after the clock signal is delayed by one cycle due to the distance between the image signal processor 120 and the post-processing processor in the imaging device, the post-processing processor can stably receive the image data without breaking the image data. There is an advantage.

A brief description will be given of the conventional method with reference to FIG. In the case of FIG. 4, when the path length of the imaging device becomes longer, the post-processing processor changes from low to high of O_HREF for extracting the first output image data (high according to the implementation method. may be missed). In such a case, the post-processing processor receives the output image data one cycle (one cycle) with delay. As a result, the order of the output image data and the number of valid data are different, resulting in a problem that the post-processing processor receives broken data.

Therefore, as shown in FIG. 5, the output controller 330 adds and outputs the first data and the last data of each line corresponding to the value set in the register, respectively, and the clock corresponding to the pixel data to which the spare data is added. By delaying the output section of the signal, it is possible to stably receive the data from the post-processing processor without breaking the data.

6 is a flowchart illustrating a method of controlling a synchronization signal by an image processor according to an exemplary embodiment of the present invention.

Referring to FIG. 6, in operation 610, the image signal processor 120 receives raw image data from the image sensor 110 and converts the raw image data into image data according to a predetermined format. The image signal processor 120 stores the converted image data in the memory 320 (step 615).

In operation 620, the output controller 330 reads image data from the memory 320 and adds extra data to output the read data. For example, the output controller 330 may read image data recorded in the memory 320 in units of lines. The output controller 330 may add m (arbitrary natural numbers) of redundant data to the best k (arbitrary natural numbers) pixel data of the read image data. The output controller 330 may add p (arbitrary natural number) of margin data to the last n (arbitrary natural number) pixel data of the read image data. Here, the information on the number of spare data to be added may be set in a register, and the output controller 330 may add the spare data corresponding to the value set in each register.

For example, assuming that the best two pixel data and the last two pixel data are added in duplicate each time (for convenience, the image data is assumed to be A, B, C, D, E, F). The controller 330 may add the best two pixel data (ie, A and B) once in duplicate, and add the last two pixel data (ie, E and F) once in duplicate and output the same. . As a result, the output controller 330 may output the output image data of the A, B, A, B, C, D, E, F, E, F form.

In operation 625, the output controller 330 delays the output period of the clock signal corresponding to the added spare data and outputs the delayed period.

That is, the output controller 330 delays the output section of the clock signal corresponding to the previously added margin data (that is, A and B) to the output section of the clock signal of the pixel data to which the margin data is added, and subsequently adds it. The output section of the clock signal corresponding to the reserved data (that is, E and F) may be delayed until the output section of the clock signal of the pixel data to which the margin data is added.

Through this, the post-processing processor that receives the image data to which the spare data is added may stably receive the data.

7 is a block diagram briefly illustrating an internal configuration of an image processing unit according to another exemplary embodiment of the present invention.

Referring to FIG. 7, the image processor 710 according to the present invention includes an image signal processor 120, a memory 320, a data output unit 720, and an output controller 730. Hereinafter, redundant descriptions of the components already described in FIG. 3 will be omitted. That is, since the description of the image signal processor 120 and the memory 320 is the same as described with reference to FIG. 3, the description thereof will be omitted.

The output controller 730 may transfer the spare data information (for example, the number of spare data to be added) that is preset in the register or specified by the user, to the data output unit 720. Here, the output controller 730 may transfer the spare data information to be added to the first data and the last data of the image data to be output to the data output unit 720. In addition, the output controller 730 may delay the output section of the clock signal corresponding to the spare data information to be added and output the delayed output section to the post processor 720.

For example, since the output controller 730 knows information about the frame that the image signal processor 120 writes to the memory 320, the frame information stored in the memory 320 (for example, the size information of the frame). ) If it is determined that all of the frames are recorded, the frame read command may be output to the data output unit 720.

The data output unit 720 reads the image data recorded in the memory 320 under the control of the output controller 730 in units of lines or pixels, and adds the spare data information to be added from the output controller 730. Correspondingly, the spare data is added and output to the post-processing processor. Here, the data output time point to which the extra data is added may be controlled by the output controller 730.

For example, suppose that there are m (random natural numbers) of free data information to be added before the first data of the image data and n (random natural numbers) of free data information to be added after the last data. In addition, the data output unit 720 may add the first data of the image data read out from the memory 320 in advance by m pieces of free data, and the largest data may add n pieces of spare data by adding them later. have. Of course, the output controller 730 may control the state of the output time of the image data to which the extra data is added by the data output unit 720.

As another example, the output controller 730 may read image data from the memory 320, add spare data as much as a value set in a register, and rewrite the corresponding output image data in the memory 320. The output controller 730 may delay and output the output section of the clock signal corresponding to the data to which the corresponding spare data is added in correspondence with the added spare data. In addition, a command instructing the output of the output image data rewritten in the memory 320 may be transmitted to the data output unit 720. Accordingly, the data output unit 720 may read output image data recorded in the memory 320 and output the read image data to the post-processing processor.

8 is a flowchart illustrating a method of controlling a synchronization signal by an image processor according to another exemplary embodiment of the present invention.

Referring to FIG. 8, in operation 810, the image signal processor 120 receives raw image data from the image sensor 110, converts the raw image data into image data according to a predetermined format, and records the image data in the memory 320.

In operation 815, the output controller 730 reads image data from the memory 320, adds spare data, and writes the data back to the memory 320. In this case, the spare data may be data in which pixel data is overlapped.

For example, assume that pixel data to which redundant data is to be added is A, B, C, D, E, F. And suppose that the spare data information to be added is one. Then, the output controller 730 adds the best pixel data (ie, A) once and adds the last pixel data (ie, F) once and writes it back to the memory 320.

In operation 820, the output controller 730 transmits the image data re-written in the memory 320 (that is, image data with extra data added, for convenience, referred to as “output image data”) to the data output unit 720. .

In operation 825, the data output unit 720 reads output image data from the memory 320 in response to an output command and outputs the output image data to the post-processing processor.

In operation 830, the output controller 730 delays the output period of the clock signal corresponding to the pixel data to which the spare data is added and outputs the delayed period to the post-processing processor. For example, the output controller 730 may delay and output an output section of the clock signal in correspondence to the number of additional spare data. If the output period of the clock signal corresponding to each pixel data is one period (that is, one cycle), and the number of added spare data is 1, the output controller 730 may output the pixel data to which the spare data is added. The output period of the clock signal can be delayed by one period. If the number of extra data added is 2, the output controller 730 may delay the output period of the clock signal of the pixel data to which the extra data is added by 2 cycles.

For example, as illustrated in FIG. 7, the data output unit 720 reads out the image data recorded in the memory 320 under the control of the output controller 730 in units of lines or pixels, thereby outputting the output controller ( The spare data may be added and output to the post-processing processor corresponding to the spare data information to be added from 730. Here, the data output time point to which the extra data is added may be controlled by the output controller 730.

For another example, the data output unit 720 first outputs the best pixel data as margin data under the control of the output controller 730, and then outputs the image data, and uses the last pixel data of the image data as the margin data. You can also output

As described above, by providing the output synchronization signal control method and apparatus according to the present invention, by adding the extra data in outputting the image data processed by the image processing unit, it is possible to suppress the damage of the image data to be input from the post-processing processor. It has an effect.

In addition, the present invention has an effect that the post-processing processor can stably obtain image data without deformation of the post-processing processor by extending the output period of the clock signal corresponding to the extra data added to the image processing unit.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the present invention as set forth in the claims below It will be appreciated that modifications and variations can be made.

Claims (18)

An image signal processor for receiving raw data from an image sensor and converting the raw data into image data according to a predetermined format; A memory for storing the image data; And And an output controller configured to add margin data to the image data and delay and output an output section of a clock signal corresponding to pixel data to which the margin data is added. The method of claim 1, And the output controller causes the clock signal corresponding to the pixel data to be delayed and outputted according to the number of the extra data. The method of claim 1, And the redundant data is data superimposed preliminarily by the best pixel data of the image data read from the memory on a line-by-line basis, and superimposed on the last pixel data by the following. The method of claim 1, The output controller extracts the image data stored in the memory in units of lines, adds k (random natural numbers) of the lines of leading data by m (random natural numbers), and adds n (random natural numbers) of the lines. ) Last data added by p (random natural numbers). In the method for controlling the synchronization signal in the image processor chip, Receiving raw data from an image sensor and converting the raw data into image data according to a predetermined format; Adding spare data to the image data; And And delaying an output period of a clock signal corresponding to the pixel data to which the margin data is added. The method of claim 5, The adding of the spare data to the video data may include: K (random natural numbers) of the video data are added in advance of m (random natural numbers) by m (random natural numbers), and n (random natural numbers) of the last pixel data of the video data are p (random natural numbers) The method of controlling a synchronization signal according to claim 12, wherein the method is added later. The method of claim 5, Delaying the output period of the clock signal corresponding to the pixel data to which the margin data is added, And outputting a delayed output section of a clock signal corresponding to the image data in accordance with the number of the pixel data. An image signal processor for receiving raw data from an image sensor and converting the raw data into image data according to a predetermined format; A memory for storing the image data; An output controller that reads the image data, adds spare data to write to the memory, and outputs an output command of the image data to which the spare data is added; And And a data output unit configured to read and output image data to which the spare data is added in correspondence with the output command, from the memory. And the output controller delays an output section of a clock signal corresponding to pixel data to which spare data is added. An image signal processor for receiving raw data from an image sensor and converting the raw data into image data according to a predetermined format; A memory for storing the image data; An output controller for outputting the image data read command; And And a data output unit configured to read the image data from the memory in response to the read command, output the best pixel data as spare data, output image data, and sequentially output the last pixel data as spare data. And the output controller delays an output section of a clock signal corresponding to the pixel data to which the margin data is added and outputs the delayed output section. The method according to claim 8 or 9, The data output unit extracts image data stored in the memory in units of lines, adds k (random natural numbers) of best-fit pixel data of the line by m (random natural numbers), and adds n ( And adding (p) an arbitrary number of last pixel data after p (random number of natural numbers). The method according to claim 8 or 9, The spare data information to be added is information on the number of spare data to be added, and the output controller delays an output section of the clock signal to output the delayed data corresponding to the spare data information to be added. In the method for controlling the synchronization signal in the image processor chip, Receiving raw data from an image sensor and converting the raw data into image data corresponding to a predetermined format; Adding spare data to the video data and recording the same in a memory; Delaying and outputting an output period of a clock signal corresponding to the pixel data to which the margin data is added; Transmitting an output command indicating an output of the image data to which the redundant data is added; And And reading out and outputting image data to which the spare data is added in correspondence to the output command, from the memory. And the clock signal is delayed to be output in accordance with an output period of the image data among the image data to which the margin data is added. The method of claim 12, Delaying the output period of the clock signal corresponding to the pixel data to which the margin data is added, And outputting the delayed output section of the clock signal in correspondence with the additional data information to be added. The method of claim 12, The method of reading and outputting image data to which the spare data is added in correspondence with the output command, may include: Image data stored in the memory is extracted in units of lines, and k (random natural numbers) of the best lines of the line are added after m (random natural numbers), and n (random natural numbers) of the lines are added. A method of controlling a synchronization signal, characterized in that the last pixel data is added after the p (random natural number) and added. An image sensor for outputting raw data corresponding to an external image; An image signal processor for receiving the raw data and converting the raw data into image data in a predetermined format; A memory for storing the converted image data; And And an output controller which adds margin data to the image data and delays an output section of a clock signal corresponding to the pixel data to which the margin data is added. The method of claim 15, And the output controller causes the clock signal corresponding to the pixel data to be delayed and outputted according to the number of the extra data. The method of claim 15, The output controller extracts the image data stored in the memory in units of lines, adds k (random natural numbers) of the best pixel data of the line by m (random natural numbers), and adds n ( And (p) an arbitrary number of natural pixels) last pixel data after each additional p (random number of natural numbers) for output. An image sensor for outputting raw data corresponding to an external image; An image signal processor for receiving the raw data and converting the raw data into image data in a predetermined format; A memory for storing the converted image data; An output controller that reads the image data, adds spare data to write to the memory, and outputs an output command of the image data to which the spare data is added; And And a data output unit configured to read and output image data to which the spare data is added in correspondence with the output command, from the memory. And the output controller delays an output section of a clock signal corresponding to pixel data to which spare data is added and outputs the delayed output section.

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