KR20070119473A - Apparatus and method for transmitting/receiving signal in a communication system - Google Patents

Abstract

An apparatus and a method for transmitting/receiving a signal in a communication system are provided to support various coding rates with one parity check matrix to reduce the implementation complexity of an encoder and a decoder. A method for transmitting/receiving a signal in a communication system includes the step of generating an ultimate block LDPC(Low Density Parity Check) code from an information vector by using a main parity check matrix corresponding to a coding rate or a sub parity check matrix generated based on the main parity check matrix. The first coding rate which is supported by the sub parity check matrix is lower than the second coding rate which is supported by the main parity check matrix. The sub parity check matrix includes the main parity check matrix.

Description

A device and method for transmitting and receiving signals in a communication system {APPARATUS AND METHOD FOR TRANSMITTING / RECEIVING SIGNAL IN A COMMUNICATION SYSTEM}

1 illustrates a parity check matrix of a block LDPC code according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a child parity check matrix when a code rate of a mother codeword vector is 2/3 and a code rate of a child codeword vector is 1/3. FIG.

3A to 3L illustrate a matrix corresponding to each subblock of FIG. 2.

4 is a diagram illustrating a child parity check matrix when a code rate of a mother codeword vector is 1/2 and a code rate of a child codeword vector is 1/4 according to an embodiment of the present invention.

5A to 5L illustrate a matrix corresponding to each subblock of FIG. 4.

FIG. 6 schematically illustrates a structure of an apparatus for transmitting a signal by supporting various coding rates in a communication system using a block LDPC code according to an embodiment of the present invention.

FIG. 7 schematically illustrates a structure of an apparatus for receiving a signal transmitted by supporting various coding rates in a communication system using a block LDPC code according to an embodiment of the present invention.

8 is a block diagram illustrating an internal structure of the encoder 611 of FIG. 6.

9 is a block diagram illustrating an internal structure of the decoder 715 of FIG. 7.

FIG. 10 is a flowchart illustrating an operation of the encoder 611 of FIG. 6.

FIG. 11 is a diagram showing the binomial matrix, the matrix E, the matrix T, and the inverse of the matrix T of the matrix B of FIG.

12 illustrates a parity check matrix having a form similar to that of a full lower triangular matrix.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and method for transmitting and receiving signals in a communication system, and in particular, to transmit and receive signals in a communication system using a block low density parity check (LDPC) code. It relates to an apparatus and a method.

The next generation communication system has been developed in the form of a packet service communication system, and the packet service communication system transmits bursted packet data to a plurality of mobile stations (MSs). The system has been designed to be suitable for high-speed mass data transmission and reception. In particular, in next-generation communication systems, a hybrid automatic repeat request (HARQ) scheme and an adaptive modulation and coding (AMC) scheme are used to support high-speed large data transmission and reception. Various schemes, such as the "AMC" scheme, have been proposed. In order to use the schemes such as the HARQ scheme and the AMC scheme, various coding rates must be supported.

In addition, in the next-generation communication system, it is known that the performance gain is excellent in high-speed data transmission together with a turbo code, and it is possible to effectively correct errors caused by noise generated in a transmission channel to increase the reliability of data transmission. The use of a block LDPC code with However, the block LDPC code has a disadvantage in terms of coding rate. That is, the block LDPC code is disadvantageous in that it is not free in terms of coding rate because the generated codeword has a relatively high coding rate. Most of the block LDPC codes currently proposed have a code rate of 1/2, and only a part has a code rate of 1/3. Thus, in the case of the block LDPC code, there is a limitation in terms of the coding rate, which makes it unsuitable for high speed data transmission.

Of course, in order to achieve a relatively low coding rate, the order distribution showing the optimal performance may be obtained by using a density evolution method, but the block LDPC code having the order distribution indicating the optimal performance may be obtained. This is difficult due to various constraints such as cycle structure and hardware implementation on a bipartite (hereinafter referred to as 'bipartite') graph.

As described above, in the case of a block LDPC code, there is a limitation in terms of coding rate. Therefore, in a communication system using the block LDPC code, a method for transmitting and receiving signals by supporting various code rates from low to high code rates is provided. There is a need for it.

Accordingly, an object of the present invention is to provide an apparatus and method for transmitting and receiving signals in a communication system using a block LDPC code.

Another object of the present invention is to provide an apparatus and method for transmitting and receiving signals by supporting various coding rates in a communication system using a block LDPC code.

The apparatus of the present invention for achieving the above objects; In an apparatus for transmitting a signal in a communication system, a final block low density parity check (LDPC) using an information vector using a parent parity check matrix or a child parity check matrix generated based on the parent parity check matrix corresponding to a coding rate. Low Density Parity Check) includes an encoder that generates codewords.

Another apparatus of the present invention for achieving the above objects; A signal receiving apparatus of a communication system, the signal receiving apparatus inputting using a parent parity check matrix or a child parity check matrix generated based on a parent parity check matrix corresponding to a coding rate used by a signal transmitting apparatus corresponding to the signal receiving device It includes a decoder for reconstructing the information vector from the signal.

The method of the present invention for achieving the above objects; A method for transmitting a signal in a signal transmission apparatus of a communication system, the method comprising: a final block low density parity using an information vector corresponding to a coding rate using a parent parity check matrix or a child parity check matrix generated based on the parent parity check matrix LDPC: Low Density Parity Check (LDPC).

Another method of the present invention for achieving the above objects is; A method for receiving a signal in a signal receiving apparatus of a communication system, the method comprising: a child parity generated based on a mother parity check matrix or the mother parity check matrix corresponding to a coding rate used by a signal transmitting apparatus corresponding to the signal receiving apparatus Restoring an information vector from an input signal using the test matrix.

Hereinafter, with reference to the accompanying drawings in accordance with the present invention will be described in detail. It should be noted that in the following description, only parts necessary for understanding the operation according to the present invention will be described, and descriptions of other parts will be omitted so as not to distract from the gist of the present invention.

First, in the next generation communication system, various methods such as hybrid automatic repeat request (HARQ) and adaptive modulation and encoding (AMC) are supported to support high-speed large data transmission and reception. Various methods such as Adaptive Modulation and Coding (hereinafter, referred to as 'AMC') have been proposed, and various coding rates must be supported in order to use the HARQ method and the AMC method. However, as described in the related art, a block low density parity check (LDPC) code, which is actively considered for use in a next-generation communication system, is referred to as an encoding rate in view of its characteristics. There is a limitation in. Accordingly, the present invention proposes a signal transmission and reception apparatus and method for supporting various coding rates in a communication system using a block LDPC code.

1 is a diagram illustrating a parity check matrix of a block LDPC code according to an embodiment of the present invention.

Referring to FIG. 1, the parity check matrix includes a parent parity check matrix used to generate a parent codeword vector, that is, a parent block LDPC codeword, and a coding rate less than a coding rate of the parent codeword vector. It has a form including a child codeword vector having a rate, that is, a child parity check matrix used to generate a child block LDPC codeword. Here, the parent parity check matrix includes an information part (s), a first parity part (p ₁ ) and a second parity part (p ₂ ), and the child parity check matrix is an information part (s). ), A first parity part p ₁ , a second parity part p ₂ , and a third parity part p ₃ . Here, the information part (s) represents a part of a parity check matrix of the block LDPC code mapped to the information vector when generating an information vector as a codeword vector, and the first parity part (p _1). And the second parity part p ₂ and the third parity part p ₃ are parity vectors, i.e., the block LDPC mapped to the first parity vector and the second parity vector and the third parity vector. Represents a part of a parity check matrix of a sign. The information vector may include at least one information bit, and each of the first parity vector, the second parity vector, and the third parity vector may include at least one parity bit.

크기를 가진다. 또한, 상기 순열 행렬을 구성하는 N_s개의 행(row)들 각각의 웨이트(weight)가 1이고, 상기 순열 행렬을 구성하는 N_s개의 열(column)들 각각의 웨이트 역시 1인 행렬을 나타낸다. 여기서, 상기 블록 LDPC 부호의 패리티 검사 행렬의 설계와 상기 블록 LDPC 부호의 부호화를 용이하게 하기 위해서 상기 블록 LDPC 부호의 패리티 검사 행렬이 다수개의 서브 블록(sub-block)들을 포함하는 형태를 가진다고 가정할 수 있다. 또한, 상기 서브 블록은 적어도 1개의 블록을 포함한다. The parity check matrix of the block LDPC code includes a plurality of blocks, and a permutation matrix or a zero matrix corresponds to each of the plurality of blocks. Here, the permutation matrix and the zero matrix are

Has a size. In addition, the N _s rows (row) of each of the weights (weight) constituting the permutation matrix, and a 1 indicates the N _s columns (column) of each of the weight constituting the permutation matrix also 1 matrix. Here, it is assumed that the parity check matrix of the block LDPC code includes a plurality of sub-blocks in order to facilitate the design of the parity check matrix of the block LDPC code and the encoding of the block LDPC code. Can be. In addition, the sub block includes at least one block.

First, the parent parity check matrix will be described.

First, the parent parity check matrix includes six sub-blocks, and the six sub-blocks include sub-block A 111, sub-block C 113, sub-block B 121, and sub-block D ( 123, the sub block T 131, and the sub block E 133. The sub block A 111 and the sub block C 113 correspond to the information part s, and a matrix A and a matrix C correspond to each of the sub block A 111 and the sub block C 113. The sub block B 121 and the sub block D 123 correspond to the first parity part p ₁ , and each of the sub block B 121 and the sub block D 123 has a matrix B and a matrix D. Corresponding. The sub block T 131 and the sub block E 133 correspond to the second parity part p ₂ , and each of the sub block T 131 and the sub block E 133 has a matrix T and a matrix E. Corresponding.

Secondly, the magnetic parity check matrix will be described below.

First, the child parity check matrix includes twelve subblocks, and the twelve subblocks include six subblocks included in the parent parity check matrix, a subblock F 115, and a subblock O 125. ), A sub block 0 135, a sub block 0 141, a sub block 0 143, and a sub block I 145. The sub block A 111, the sub block C 113, and the sub block F 115 correspond to the information part s, and the matrix F corresponds to the sub block F 115. The sub block B 121, the sub block D 123, and the sub block 0 125 correspond to the first parity part p ₁ , and the matrix 0 corresponds to the sub block 0 125. Here, the matrix 0 represents a matrix in which all elements are zero. The sub block T 131, the sub block E 133, and the sub block 0 135 correspond to the second parity part p ₂ , and the matrix 0 corresponds to the sub block 0 135. The sub block 0 141, the sub block 0 143, and the sub block I 145 correspond to the third parity part p ₃ , and the sub block 0 141 and the sub block 0 143 correspond to the third parity part p ₃ . Matrix 0 corresponds to, and matrix I corresponds to sub-block I 145. Here, the matrix I represents an identity matrix.

As described above, the child parity check matrix includes all sub blocks included in the parent parity check matrix and additional sub blocks. Accordingly, the child parity check matrix has an extended form of the parent parity check matrix.

Accordingly, a parent codeword vector may be generated using the mother parity check matrix, and a child codeword vector having a coding rate less than the coding rate of the mother codeword vector may be generated using the child parity check matrix. It can be seen that.

On the contrary, there may be a case where a child codeword vector having a code rate exceeding the code rate of the parent codeword vector must be generated. In this case, at least one parity bit may be punctured from the parity vector included in the mother codeword vector to generate a child codeword vector having a coding rate exceeding the coding rate of the mother codeword vector.

As a result, a mother codeword vector having only the child parity check matrix, a child codeword vector having a coding rate less than the coding rate of the mother codeword vector, and a coding rate exceeding the coding rate of the mother codeword vector It is possible to generate all child codeword vectors.

Meanwhile, as described above, since each of the subblocks includes at least one block, the sub parity check matrix includes a plurality of blocks. 2 and 3A to 3L, a parity check matrix will be described when the code rate of the mother codeword vector is 2/3 and the code rate of the child codeword vector is 1/3. do.

2 is a diagram illustrating a child parity check matrix when a code rate of a mother codeword vector is 2/3 and a code rate of a child codeword vector is 1/3.

Before describing FIG. 2, the parity check matrix of the block LDPC code includes a plurality of blocks as described above. Since it is assumed that the coding rate of the mother codeword vector is 2/3, the mother parity check matrix corresponding to the coding rate 2/3 includes an information part (s) including 32 block columns and 16 block rows, and 1 The first parity part p ₁ includes the number of block columns and the 16 block rows, and the second parity part p ₂ includes the number of 15 block columns and the 16 block rows. That is, the information part (s) of the parent parity check matrix includes a matrix A 211 and a matrix C 213, and the first parity part p ₁ includes the matrix B 221 and the matrix D 223. The second parity part p ₂ includes a matrix T 231 and a matrix E 233.

In addition, since it is assumed that the coding rate of the child codeword vector is 1/3, the self parity check matrix corresponding to the coding rate 1/3 includes an information part (s) including 32 block columns and 64 block rows. , A first parity part p ₁ comprising one block column and 64 block rows, a second parity part p ₂ comprising 15 block columns and 64 block rows, 48 block columns and 64 The third parity part p ₃ including three block rows is included. That is, the information part s of the child parity check matrix includes the matrix A 211, the matrix C 213, and the matrix F 215, and the first parity part p ₁ is the matrix B 221. ), Matrix D 223 and matrix 0 225, and the second parity part p ₂ includes matrix T 231, matrix E 233, and matrix 0 235. The third parity part p ₃ includes a matrix 241, a matrix 243, and a matrix I 245.

The matrix A 211, the matrix C 213, the matrix F 215, the matrix B 221, the matrix D 223, and the matrix 0 225 will be described with reference to FIGS. 3A through 3L. ), The structures of the matrix T 231, the matrix E 233, the matrix 235, the matrix 0 241, the matrix 0 243, and the matrix I 245 will be described. .

3A to 3L illustrate a matrix corresponding to each subblock of FIG. 2.

Before describing FIG. 3A to FIG. 3L, numbers described in blocks in the matrix illustrated in FIGS. 3A to 3L represent exponents of permutation matrices corresponding to the corresponding blocks. Here, the exponent is assuming that the permutation matrix is expressed as P ^a containing an exponent. If a = 0, this means that the permutation matrix, that is, P ⁰ is an identity matrix. As it increases, the permutation matrix has a structure shifted to the right from the identity matrix structure. In addition, when no number is written in the block in the matrix shown in FIGS. 3A to 3L, the block corresponds to 0 matrix.

The matrix A 211 is shown in FIG. 3A, and the matrix A 211 includes 32 block columns and 15 block rows, and a permutation matrix or a zero matrix corresponds to the corresponding blocks. do.

The matrix C 213 is shown in FIG. 3B, and the matrix C 213 includes 32 block columns and one block row, and a permutation matrix or a zero matrix corresponds to the corresponding blocks. do.

The matrix F 215 is shown in FIG. 3C, where the matrix F 215 includes 32 block columns and 48 block rows, and the permutation matrix or the zero matrix corresponds to the corresponding blocks. do.

The matrix B 221 is illustrated in FIG. 3D, and the matrix B 221 includes one block column and 16 block rows, and a permutation matrix or a zero matrix corresponds to the corresponding blocks. .

The matrix D 223 is illustrated in FIG. 3E, and the matrix D 223 includes one block column and one block row, and the permutation matrix corresponds to the corresponding block.

The matrix 0 225 is shown in FIG. 3F, and the matrix 0 225 includes one block column and 48 block rows. The matrix 0 225 corresponds to the zero matrix as shown in the corresponding block.

The matrix T 231 is illustrated in FIG. 3G, and the matrix T 231 includes 15 block columns and 15 block rows, and a permutation matrix or a 0 matrix corresponds to the corresponding block as illustrated in the corresponding block. .

The matrix E 233 is shown in FIG. 3H, and the matrix E 233 includes 15 block columns and one block row, and a permutation matrix or a zero matrix corresponds to the corresponding block as shown in the corresponding block. .

The matrix 0 235 is illustrated in FIG. 3I, and the matrix 0 235 includes 15 block columns and 48 block rows. The matrix 0 235 corresponds to the corresponding block as shown in the corresponding block.

The matrix 0 241 is illustrated in FIG. 3J, and the matrix 0 241 includes 48 block columns and 15 block rows. The matrix 0 241 corresponds to the zero matrix as shown in the corresponding block.

The matrix 0 243 is illustrated in FIG. 3K, and the matrix 0 243 includes 48 block columns and one block row, and the zero matrix corresponds to the corresponding block.

The matrix I 245 is illustrated in FIG. 3L, which includes 48 block columns and 48 block rows, and corresponds to a permutation matrix or a 0 matrix as shown in the corresponding block. .

Next, with reference to Figs. 4 and 5A to 5L, a description will be given of the subparity check matrix when the code rate of the mother codeword vector is 1/2 and the code rate of the child codeword vector is 1/4. Shall be.

4 is a diagram illustrating a child parity check matrix when a code rate of a mother codeword vector is 1/2 and a code rate of a child codeword vector is 1/4. Referring to FIG.

Before describing FIG. 4, the parity check matrix of the block LDPC code includes a plurality of blocks as described above. Since it is assumed that the coding rate of the mother codeword vector is 1/2, the mother parity check matrix corresponding to the coding rate 1/2 includes an information part (s) including 24 block columns and 24 block rows, and 1 The first parity part p ₁ includes the number of block columns and the 24 block rows, and the second parity part p ₂ includes the number of 23 block columns and the 24 block rows. That is, the information part s of the parent parity check matrix includes a matrix A 411 and a matrix C 413, and the first parity part p ₁ includes the matrix B 421 and the matrix D 423. The second parity part p ₂ includes a matrix T 431 and a matrix E 433.

In addition, since the code rate of the child codeword vector is assumed to be 1/4, the self parity check matrix corresponding to the code rate 1/4 includes an information part (s) including 24 block columns and 724 block rows. , A first parity part p ₁ comprising one block column and 72 block rows, a second parity part p ₂ comprising 23 block columns and 72 block rows, 48 block columns and 72 And a third parity part p ₃ comprising three block rows. That is, the information part s of the child parity check matrix includes the matrix A 411, the matrix C 413, and the matrix F 415, and the first parity part p ₁ is the matrix B 421. ), Matrix D 423 and matrix 0 425, wherein the second parity part p ₂ comprises matrix T 431, matrix E 433, and matrix 0 435. The third parity part p ₃ includes a matrix 441, a matrix 443, and a matrix I 445.

The matrix A 411, the matrix C 413, the matrix F 415, the matrix B 421, the matrix D 423, and the matrix 0 425 with reference to FIGS. 5A through 5L. ), The structures of the matrix T 431, the matrix E 433, the matrix 435, the matrix 0 441, the matrix 0 443, and the matrix I 445 will be described. .

5A to 5L illustrate a matrix corresponding to each subblock of FIG. 4.

Before describing FIG. 5A to FIG. 5L, numbers described in blocks in the matrix illustrated in FIGS. 5A to 5L represent exponents of permutation matrices corresponding to the blocks. In addition, when no number is written in the block in the matrix illustrated in FIGS. 5A to 5L, the block corresponds to the zero matrix.

The matrix A 411 is shown in FIG. 5A, and the matrix A 411 includes 24 block columns and 23 block rows, and the permutation matrix or the zero matrix corresponds to the corresponding blocks. do.

The matrix C 413 is shown in FIG. 5B, and the matrix C 413 includes 24 block columns and 1 block row, and the permutation matrix or the 0 matrix corresponds to the corresponding blocks. do.

The matrix F 415 is shown in FIG. 5C, and the matrix F 415 includes 24 block columns and 48 block rows, and a permutation matrix or a 0 matrix corresponds to the corresponding blocks. do.

The matrix B 421 is illustrated in FIG. 5D, and the matrix B 421 includes one block column and 23 block rows, and a permutation matrix or a zero matrix corresponds to the corresponding blocks as shown in the corresponding blocks. .

The matrix D 423 is illustrated in FIG. 5E, and the matrix D 423 includes one block column and one block row, and the permutation matrix corresponds to the corresponding block.

The matrix 0 425 is shown in FIG. 5F, and the matrix 0 425 includes one block column and 48 block rows, and the zero matrix corresponds to the corresponding block.

The matrix T 431 is illustrated in FIG. 5G, and the matrix T 431 includes 23 block columns and 23 block rows, and a permutation matrix or a 0 matrix corresponds to the corresponding block as illustrated in the corresponding block. .

The matrix E 433 is illustrated in FIG. 5H, and the matrix E 433 includes 23 block columns and 1 block row, and a permutation matrix or a 0 matrix corresponds to the corresponding block as shown in the corresponding block. .

The matrix 0 435 is shown in FIG. 5I, and the matrix 0 435 includes 23 block columns and 48 block rows. The matrix 0 435 corresponds to the zero matrix as shown in the corresponding block.

The matrix 0 441 is illustrated in FIG. 5J, and the matrix 0 441 includes 48 block columns and 23 block rows, and a zero matrix corresponds to the corresponding block.

The matrix 0 443 is illustrated in FIG. 5K, and the matrix 0 443 includes 48 block columns and one block row, and a zero matrix corresponds to the corresponding block.

The matrix I 445 is shown in FIG. 5L, and the matrix I 445 includes 48 block columns and 48 block rows, and a permutation matrix or a 0 matrix corresponds to the corresponding block as shown in the corresponding block. .

Next, a structure of an apparatus for transmitting a signal by supporting various coding rates in a communication system using a block LDPC code according to an embodiment of the present invention will be described with reference to FIG. 6.

6 is a diagram schematically illustrating a structure of an apparatus for transmitting a signal by supporting various coding rates in a communication system using a block LDPC code according to an embodiment of the present invention.

Referring to FIG. 6, the signal transmission apparatus includes an encoder 611, a modulator 613, and a transmitter 615.

First, when an information vector to be transmitted is generated by the signal transmission device, the information vector is transmitted to the encoder 611. The encoder 611 encodes the information vector using a predetermined coding scheme, generates the final codeword vector, and outputs the final codeword vector to the modulator 613. Here, the coding scheme is an LDPC coding scheme supporting various coding rates as described above, and since the internal structure of the encoder 611 will be described in detail with reference to FIG. 8, a detailed description thereof will be omitted. .

The modulator 613 modulates the codeword vector using a predetermined modulation scheme to generate a modulated vector and output the modulated vector to the transmitter 615. The transmitter 615 inputs a modulation vector output from the modulator 613 to process a transmission signal and then transmits the signal to a signal receiving apparatus through an antenna.

Next, a structure of an apparatus for receiving a signal transmitted by supporting various coding rates in a communication system using a block LDPC code according to an embodiment of the present invention will be described with reference to FIG. 7.

FIG. 7 schematically illustrates a structure of an apparatus for receiving a signal transmitted by supporting various coding rates in a communication system using a block LDPC code according to an embodiment of the present invention.

Referring to FIG. 7, the signal receiving apparatus includes a receiver 711, a demodulator 713, and a decoder 715. The signal transmitted by the signal transmitting apparatus corresponding to the signal receiving apparatus is received through the antenna of the signal receiving apparatus, and the signal received through the antenna is transmitted to the receiver 711. The receiver 711 processes a signal received through the antenna and outputs the received signal to the demodulator 653. The demodulator 653 inputs the signal output from the receiver 651, demodulates the demodulation method corresponding to the modulation scheme applied by the modulator of the signal transmission apparatus, that is, the modulator 613, and then outputs the demodulation scheme to the decoder 715. do. The decoder 715 inputs the signal output from the demodulator 713, decodes the decoder according to an encoding method applied by the encoder of the signal transmission apparatus, that is, the encoder 611, and finally decodes the decoded signal. Output as reconstructed information vector. Here, the decoding method is a decoding method corresponding to the coding method, and since the internal structure of the decoder 715 will be described in detail with reference to FIG. 9, a detailed description thereof will be omitted.

Next, the internal structure of the encoder 611 of FIG. 6 will be described with reference to FIG. 8.

8 is a block diagram illustrating an internal structure of the encoder 611 of FIG. 6.

Referring to FIG. 8, the encoder 611 includes a puncturer 811, a matrix A multiplier 813, a matrix C multiplier 815, a switch 817, and a matrix ET- ¹ multiplier ( 819), an exclusive OR operator 821, a matrix B multiplier 823, an exclusive OR operator 825, a matrix ET- ¹ multiplier 827, a matrix F multiplier 831, and an assembly unit 833. And a controller (not shown).

First, the operation of the controller will be described.

The controller stores a child parity check matrix in which a parent parity check matrix is extended to an internal memory (not shown) included in the controller itself. The controller generates a final codeword vector using a parent parity check matrix, or generates a final codeword vector using a child parity check matrix, corresponding to a coding rate supported by the signal transmission apparatus, or the parent parity. Control to generate the final codeword vector by puncturing the codeword vector generated using the check matrix. That is, the controller controls the operation of the encoder 611 according to the coding rate supported by the signal transmission apparatus, and the operation of the encoder 611 according to the control operation of the controller will be described in detail below. Same as

First, when an information vector to be encoded is input, the controller determines a coding rate supported by the signal transmission apparatus and controls the operation of the encoder 611 according to the determined coding rate. First, the operation of the encoder 611 when the determined coding rate is the same as the coding rate supported by the parent parity check matrix (hereinafter, referred to as a parent code rate) will be described. . Here, that the determined code rate is equal to the mother code rate indicates that the encoder 611 generates a final codeword vector using the parent parity check matrix.

First, the input information vector is transferred to an assembly unit 833, a matrix A multiplier 813, a matrix C multiplier 815, and a switch 817. The matrix A multiplier 813 multiplies the information vector by the matrix A and outputs the result to the matrix ET ⁻¹ multiplier 819 and the exclusive-OR operator 825. The matrix ET ^-1 multiplier 819 multiplies the signal output from the matrix A multiplier 813 and the matrix ET ^-1 and then outputs the result to the exclusive OR operator 821. The matrix C multiplier 815 multiplies the information vector and the matrix C and outputs the multiplied logical OR operator 821. The exclusive OR operator 821 performs an exclusive OR on the signal output from the matrix ET- ¹ multiplier 819 and the signal output from the matrix C multiplier 815, and then performs the matrix B multiplier 823 and the puncturer ( 811). Here, the signal output from the exclusive-OR operator 821 becomes a first parity vector.

The matrix B multiplier 823 multiplies the signal output from the exclusive OR operator 821 and the matrix B and then outputs the result to the exclusive OR operator 825. The exclusive OR operator 825 performs an exclusive OR on the signal output from the matrix A multiplier 813 and the signal output from the matrix B multiplier 823, and then outputs the result to the matrix ET ⁻¹ multiplier 827. The matrix ET ^-1 multiplier 827 multiplies the signal output from the exclusive-OR operator 825 and the matrix ET ^-1 and outputs the multiplier to the perforator 811. Here, the signal output from the matrix ET- ¹ multiplier 827 becomes a second parity vector.

The switch 817 performs a switching operation under the control of the controller, and the controller only needs to generate a third parity vector, that is, generate a final codeword vector using a child parity check matrix. Only when there is a switch 817 is switched on (controlling) so that the information vector is input to the matrix F multiplier (831). However, since the coding rate supported by the signal transmission apparatus is a parent coding rate, the controller switches off the switch 817.

The puncturer 811 also performs a puncturing operation under the control of the controller. Since the code rate supported by the signal transmission apparatus is a mother code rate, the controller does not perform the puncturing operation by the puncturer 811. The parity vector and the second parity vector are controlled to be output to the granulator 833 as they are. The assembler 822 assembles the information vector, the first parity vector, and the second parity vector under the control of the controller, generates the final codeword vector, and outputs the final codeword vector.

Secondly, the operation of the encoder 611 when the determined coding rate is equal to the coding rate supported by the self parity check matrix (hereinafter, referred to as a 'child coding rate') will be described below. Here, that the determined code rate is equal to the child code rate indicates that the encoder 611 generates the final codeword vector using the self parity check matrix.

The operation of the encoder 611 in the case of generating the final codeword vector using the child parity check matrix is compared with the operation of the encoder 611 in the case of generating the final codeword vector using the parent parity check matrix. It differs only in that the final codeword vector is generated by additionally generating a 3 parity vector. That is, since the child coding rate is supported, the controller switches on the switch 817 to control the information vector to be transmitted to the matrix F multiplier 831. Then, the matrix F multiplier 831 multiplies the information vector transferred from the switch 817 by the matrix F and outputs the matrix F to the assembler 811. In this case, the signal output from the matrix F multiplier 831 becomes the third parity vector. The assembler 822 assembles the information vector, the first parity vector, and the second parity vector under the control of the controller, generates the final codeword vector, and outputs the final codeword vector.

Third, the operation of the encoder 611 in the case where the determined coding rate exceeds the mother coding rate (hereinafter, referred to as "overcoding rate") will be described. Here, the code rate determined to be the excess code rate means that the encoder 611 generates a codeword vector using the parent parity check matrix, and then punctures the generated codeword vector to generate a final codeword vector. Indicates that In this case, the operation of the encoder 611 is compared to the operation of the encoder 611 in the case of generating the final codeword vector using the parent parity check matrix. The only difference is that the corresponding parity bits are punctured to produce the final codeword vector. That is, since the excess code rate is supported, the controller controls the puncturer 811 to puncture corresponding parity bits corresponding to the excess code rate among the first parity vector and the second parity vector. Accordingly, the puncturer 811 punctures the parity bit corresponding to the excess coding rate among the first and second parity vectors under the control of the controller and outputs the parity bit to the assembly unit 833. The granulator 833 assembles the information vector and the signal output from the puncturer 833, generates a final codeword vector, and outputs the final codeword vector.

In FIG. 8, the controller generates each vector, that is, the information vector, the first parity vector, the second parity vector, and the third parity vector in parallel, corresponding to the coding rate, and then assembles the final codeword vector. Although a case of controlling to generate C 1 is described as an example, the controller may control to generate a final codeword vector by sequentially generating only a corresponding vector of each vector according to a coding rate. In FIG. 8, the controller determines an encoding rate to be used by the signal transmission apparatus when an information vector is input. However, the controller controls to perform the encoding operation described with reference to FIG. 8 according to a predetermined encoding rate. Of course you can.

On the other hand, all the codes of the LDPC code sequence can be decoded by a sum-product algorithm on a bipartite (hereinafter referred to as 'bipartite') graph. The decoding method of the LDPC code can be largely classified into a bidirectional transfer method and a flow transfer method. When the decoding operation is performed by the bidirectional transfer method, a node processor exists per check node, and the complexity of the decoder becomes complicated in proportion to the number of the check nodes, but since all nodes are updated at the same time, the decoding is performed. The speed is very fast.

In contrast, the flow transfer method has a node processor, which updates information by passing through nodes on all bipartite graphs. Therefore, the complexity of the decoder is simplified, but as the size of the parity check matrix increases, that is, as the number of nodes increases, the decoding speed becomes slow. However, when the parity check matrix is generated in units of blocks like the block LDPC code supporting the variable coding rate proposed by the present invention, the node processor uses the number of nodes constituting the parity check matrix during decoding. The decoder complexity is reduced rather than the delivery method, and it is possible to implement a decoder having a faster decoding speed than the flow delivery method.

Next, the internal structure of the decoder 715 of FIG. 7 will be described with reference to FIG. 9.

9 is a block diagram illustrating an internal structure of the decoder 715 of FIG. 7.

Referring to FIG. 9, the decoder 715 includes a codeword selector 911, a variable node decoder 913, a switch 915, an exclusive-OR operator 917, and a de-interleaver. 919, an interleaver 921, a controller 923, a memory 925, an exclusive-OR operator 927, an inspection node decoder 929, and a hard determiner 931. It includes.

First, a demodulator, that is, a signal output from the demodulator 713 of FIG. 7 is transmitted to the codeword selector 911, and the codeword selector 911 inputs a signal output from the demodulator 713 to transmit a signal. The codeword is selected according to the coding rate used in the apparatus. When the excess code rate is used in the signal transmission apparatus, the codeword selector 911 inserts 0 into a bit corresponding to the punctured parity bit and outputs the result to the variable node decoder 913. In addition, the codeword selector 911 stores a preparatory subparity check matrix between the signal transmission device and the signal reception device, and punctures parity bits corresponding to the excess coding rate used by the signal transmission device. Information is stored in advance. Here, the codeword selector 911 stores not only the number of parity bits punctured according to the corresponding coding rate but also its position information in advance.

The variable node decoder 913 inputs the signal outputted from the codeword selector 911 to calculate probability values, updates the calculated probability values, and then updates the calculated probability values to the switch 915 and the exclusive-OR operator 917. Output Here, the variable node decoder 913 connects the variable nodes corresponding to the parity check matrix preset in the decoder 715, and updates the number of input values and output values of 1 connected to the variable nodes. The operation is performed. Here, since the decoder 715 uses a parent parity check matrix or a child parity check matrix, the variable node decoder 913 connects variable nodes corresponding to the parent parity check matrix or the child parity check matrix. The number of 1s connected to each of the variable nodes is equal to the weight of each of the columns constituting the parity check matrix. Therefore, the internal operation of the variable node decoder 913 is different according to the weight of each column constituting the parity check matrix.

The exclusive OR operator 917 inputs a signal output from the variable node decoder 913 and an output signal of the interleaver 921 during a previous iterative decoding process, and in the variable node decoder 913 The output signal of the interleaver 921 in the previous iterative decoding process is subtracted from the output signal and then output to the deinterleaver 919. Here, when the decoding process is the first decoding process, the output signal of the interleaver 921 should be regarded as 0, of course.

The deinterleaver 919 inputs the signal output from the exclusive OR operator 917 and de-interleaves the deinterleaving method according to a predetermined deinterleaving scheme, and then the exclusive OR operator 927 and the check node. Output to decoder 929. Here, the internal structure of the deinterleaver 927 has a structure corresponding to the parity check matrix, and the reason is that the deinterleaver 927 corresponds to the position of elements having a value of 1 in the parity check matrix. This is because the output value with respect to the input value of the interleaver 921 is different.

The exclusive OR operator 927 inputs an output signal of the check node decoder 929 and an output signal of the deinterleaver 919 in a previous iterative decoding process, and outputs the check node decoder in the previous iterative decoding process. The output signal of the deinterleaver 919 is subtracted from the output signal of 929 and then output to the interleaver 921. The check node decoder 929 connects check nodes according to a parity check matrix preset in the decoder 715, and an update operation having an input value and an output value equal to 1 connected to the check nodes is performed. Is performed. Here, since the decoder 715 uses a parent parity check matrix or a child parity check matrix, the check node decoder 929 connects variable nodes corresponding to the parent parity check matrix or the child parity check matrix. The number of 1s connected to each of the check nodes is equal to the weight of each of the rows constituting the parity check matrix. Accordingly, the internal operation of the check node decoder 929 is different according to the weight of each of the rows constituting the parity check matrix.

Here, the interleaver 921 interleaves the signal output from the exclusive OR operator 927 in a preset manner according to the control of the controller 923, and then the exclusive OR operator 917 and the variable node. Output to decoder 913. Herein, the controller 923 reads information related to the interleaving scheme stored in the memory 925 to control the interleaving scheme of the interleaver 921. In addition, when the decoding process is the first decoding process, the output signal of the deinterleaver 919 should be regarded as 0.

By repeatedly performing the above processes, a reliable decoding is performed without error, and after performing the repeated decoding corresponding to a preset number of preset repetitions, the switch 915 performs an exclusive OR with the variable node decoder 913. After switching off between the operators 917, the signal output from the variable node decoder 913 by switching on between the variable node decoder 913 and the hard determiner 931 is converted into the hard determiner 931. To print). The hard determiner 931 inputs the signal output from the variable node decoder 913 to make a hard decision, and then outputs the hard decision result, and the output value of the hard determiner 931 becomes a finally decoded value. will be.

In addition, in FIG. 9, the codeword selector determines a code rate used by the signal transmission apparatus when a signal output from the demodulator 713 is inputted. However, FIG. 9 corresponds to a predetermined code rate. Of course, it can be controlled to perform the decoding operation described in.

Next, an operation process of the encoder 611 of FIG. 6 will be described with reference to FIG. 10.

10 is a flowchart illustrating an operation of the encoder 611 of FIG. 6.

Referring to FIG. 10, the encoder 611 receives an information vector in step 1011 and proceeds to step 1013. In step 1013, the encoder 611 determines a coding rate to be used in the signal transmission apparatus and proceeds to step 1015. In step 1015, the encoder 611 checks whether the determined coding rate is the same as the parent coding rate. If the determined code rate is the same as the parent code rate, the encoder 611 proceeds to step 1017. In step 1017, the encoder 611 generates a first parity vector and a second parity vector corresponding to the parent parity check matrix, and proceeds to step 1019. In step 1019, the encoder 611 combines the information vector, the generated first and second parity vectors, and generates a final codeword vector.

On the other hand, if the determined code rate is not the same as the parent code rate in step 1015, the encoder 611 proceeds to step 1021. In step 1021, the encoder 611 checks whether the determined coding rate is equal to the child coding rate. If the determined code rate is equal to the child code rate, the encoder 611 proceeds to step 1023. In step 1023, the encoder 611 generates a first parity vector, a second parity vector, and a third parity vector corresponding to the self parity check matrix, and proceeds to step 1025. In step 1025, the encoder 611 generates the final codeword vector by assembling the information vector, the generated first parity vector, the second parity vector, and the third parity vector.

On the other hand, if the code rate determined in step 1021 is not the same as the child code rate, that is, if the determined code rate exceeds the mother code rate, the encoder 611 proceeds to step 1027. In step 1027, the encoder 611 generates a first parity vector and a second parity vector corresponding to the parent parity check matrix, and proceeds to step 1029. In step 1029, the encoder 611 punctures a corresponding parity bit among the first parity vector and the second parity vector, and then proceeds to step 1031. In step 1031, the encoder 611 assembles the information vector, the punctured first parity vector and the second parity vector, generates a final codeword vector, and ends.

Meanwhile, among the sub blocks included in the parity check matrix of the block LDPC code according to the embodiment described above with reference to FIG. 1, each of the sub blocks B 121, the sub blocks E 133, and the sub blocks T 131, respectively. The matrix B corresponding to, and the matrix E and the matrix T are generated to have a structure as shown in FIG. 11 to minimize the coding complexity of the block LDPC code.

FIG. 11 is a diagram illustrating a transpose matrix, a matrix E, a matrix T, and an inverse matrix of the matrix T of the matrix B of FIG. 1.

FIG. 11 shows a matrix B ^T , which is a binomial matrix of the matrix B, a matrix E, a matrix T, and a matrix T ^{−1 which} is an inverse of the matrix T. FIG. The matrix T has a form similar to a full lower triangular matrix. That is, the matrix T allows an identity matrix to be mapped to blocks positioned on a diagonal, and permutation matrices are mapped to blocks having a dual diagonal structure with the diagonal. Herein, a matrix mapped to a block will be referred to as a 'block matrix', and for convenience of explanation, a block and a block matrix will be used interchangeably.

Meanwhile, a process of generating the matrix B ^T , the matrix E, the matrix T, and the matrix T- ^{1 to} have a structure as shown in FIG. 11 will be described below.

First, it is assumed that the parent parity check matrix has a structure as shown in FIG.

12 is a diagram illustrating a parity check matrix having a form similar to that of a full lower triangular matrix.

혹은 a_ij = ∞를 가진다. 상기 정보 파트가 포함하는 순열 행렬 P의 위 첨자 a_ij가 0일 경우, 즉 P⁰는 항등 행렬

를 나타내며, 상기 순열 행렬 P의 위첨자 a_ij가 ∞일 때, 즉 순열 행렬 P^∞는 영 행렬 나타낸다. 또한, p와 q는 상기 패리티 검사 행렬에서 상기 정보 파트에 해당하는 블록들의 행과 열의 개수를 나타낸다. 또한, 상기 패리티 파트가 포함하는 순열 행렬 P의 위첨자 a_i, x, y 역시 순열 행렬 P의 지수를 나타내며, 다만 설명의 편의상 정보 파트와의 구분을 위해 상이하게 설정하였을 뿐이다. 즉, 상기 도 12에서

내지

역시 순열 행렬들이며, 상기 패리티 파트의 대각(diagonal) 부분에 위치하는 부분 행렬들에 순차적으로 인덱스(index)를 부여한 것이다. 또한, 상기 도 12에서 P^x와 P^y 역시 순열 행렬들이며, 설명의 편의상 임의의 인덱스를 부여한 것이다. In the parity check matrix illustrated in FIG. 12, the parity part is out of the shape of the full lower triangular matrix as compared to the parity check matrix having the full lower triangular matrix. In FIG. 12, the superscript a _ij of the permutation matrix P included in the information part is

Or a _ij = ∞. If the superscript a _ij of the permutation matrix P included in the information part is 0, that is, P ⁰ is an identity matrix

When the superscript a _ij of the permutation matrix P is ∞, that is, the permutation matrix P ^∞ represents a zero matrix. In addition, p and q represent the number of rows and columns of blocks corresponding to the information part in the parity check matrix. In addition, the superscripts a _i , x, and y of the permutation matrix P included in the parity part also represent exponents of the permutation matrix P, but are merely set differently from the information part for convenience of description. That is, in FIG. 12

To

Also, they are permutation matrices, and indexes are sequentially assigned to partial matrices positioned in a diagonal portion of the parity part. In addition, in FIG. 12, P ^x and P ^{y are} also permutation matrices, which are given an arbitrary index for convenience of description.

는 정보 벡터(

)와, 제1패러티 벡터(

)와, 제2패러티 벡터(

)로 분할하여 생각할 수 있고, 이 경우 상기 모 패러티 검사 행렬과 상기 부호어 벡터

의 곱은 하기 수학식 1 및 수학식 2와 같이 나타낼 수 있다.Then, considering the case where the mother parity check matrix includes an information part (s), a first parity part (p ₁ ), and a second parity part (p ₂ ), a codeword vector

Is an information vector (

) And the first parity vector (

) And the second parity vector (

In this case, and in this case, the parent parity check matrix and the codeword vector

The product of can be expressed as Equation 1 and Equation 2 below.

)와 연관된 부분, 즉

는 하기 수학식 3을 사용하여 구할 수 있다.In Equation 1, T represents a transpose operation, and in Equation 2, the first parity vector (

), That is,

Can be obtained using Equation 3 below.

)를 구하기 위해 사용되는 상기 행렬 φ을 항등 행렬 I가 되도록 설정한다. 이렇게 상기 행렬 φ을 항등 행렬 I가 되도록 설정함으로써 상기 블록 LDPC 부호의 부호화 복잡도가 최소화된다. 그러면 여기서 상기 도 11을 참조하여 상기 행렬 φ을 항등 행렬 I가 되도록 설정하는 동작에 대해서 설명하기로 한다. In Equation 3, since the coding complexity of the block LDPC code is generated in proportion to the square of the magnitude of the matrix φ, in the embodiment of the present invention, the first parity vector (

Is set to be the identity matrix I. By setting the matrix φ to be the identity matrix I, the coding complexity of the block LDPC code is minimized. Next, an operation of setting the matrix φ to be the identity matrix I will be described with reference to FIG. 11.

는 항등 행렬 I로 고정하기로 한다. 상기 도 11에서 설명한 행렬 T^-1이 포함하는 블록들에서

부분은 행렬

에서 행렬

까지의 곱인

를 나타낸다. First, permutation matrix

Is fixed to the identity matrix I. In the blocks included in the matrix T- ¹ described with reference to FIG. 11.

Part of the matrix

Matrix

Multiply by

Indicates.

In addition, the matrix E 11 is zero, so the matrix corresponding to all of the blocks except one block, multiplication of the matrix E and the matrix T ^-1 is the end of the last row of the matrix T ^-1 and the matrix E of The multiplication form of the block may be expressed as in Equation 4 below.

In addition, multiplying the matrix B by the multiplication of the matrix E and the matrix T ^-1 may be expressed by Equation 5 below.

As shown in Equation 5, when the multiplication of the matrix E and the matrix T ^-1 is multiplied by the matrix B, all other blocks except for two blocks among the blocks included in the matrix B have zero matrixes. Correspondingly, since a multiplication operation needs to be performed on only two blocks of the matrix B, a simple operation is obtained.

이 되도록 설정하고,

가 되도록 설정하면,

의 관계가 성립하므로 상기 행렬 φ은 항등 행렬 I가 된다. 그리고 하기 수학식 6은 상기 행렬 φ이 항등 행렬 I가 되는 조건들을 간략하게 나타낸 것이다. here,

Set to

If set to

Since the relation is true, the matrix φ becomes the identity matrix I. Equation 6 briefly illustrates the conditions under which the matrix φ becomes the identity matrix I.

If the matrix φ is set to be the identity matrix I as described in Equation 4 to Equation 6, the complexity of the encoding process of the block LDPC code can be minimized.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

The present invention as described above has the advantage that it is possible to transmit and receive signals by supporting various coding rates in a communication system using a block LDPC code. In addition, the present invention has the advantage that it is possible to support a variety of code rates with only one parity check matrix, thereby minimizing the complexity of implementing the encoder and the decoder.

Claims (40)

In the method for transmitting a signal in a signal transmission apparatus of a communication system, Generating a final block low density parity check (LDPC) codeword using an information vector corresponding to a coding rate using a mother parity check matrix or a child parity check matrix generated based on the mother parity check matrix. Signal transmission method comprising. The method of claim 1, And a first encoding rate that is a coding rate supported by the child parity check matrix is less than a second encoding rate that is a coding rate supported by the parent parity check matrix. The method of claim 1, The child parity check matrix has a form including the parent parity check matrix. The method of claim 3, The child parity check matrix includes a first part corresponding to the parent parity check matrix and a second part other than the first part, wherein the first part includes an information part mapped to the information vector, and a first parity vector. And a second parity part mapped to a second parity vector, wherein the second part includes an additional information part mapped to the information vector and an additional agent mapped to the first parity vector. And a first parity part, an additional second parity part mapped to the second parity vector, and a third parity vector mapped to a third parity vector. The method of claim 4, wherein The information part includes a first matrix and a second matrix, the first parity part includes a third matrix and a fourth matrix, the second parity part includes the fifth matrix and a sixth matrix, The additional information part includes a seventh matrix, the additional first parity part includes an eighth matrix, the additional second parity part includes a ninth matrix, and the third parity part includes a tenth matrix. And an eleventh matrix and a twelfth matrix. The method of claim 5, Generating a final block LDPC codeword using the child parity check matrix; Generating a first signal by multiplying the information vector by the first matrix; Generating a second signal by multiplying the information vector by the second matrix; Multiplying the first signal by a matrix product of the inverse of the third matrix and the fourth matrix to generate a third signal; Generating an first parity vector as a fourth signal by performing an exclusive OR operation on the second signal and the third signal; Multiplying the fourth signal by the fifth matrix to generate a fifth signal, and generating an sixth signal by performing an exclusive OR on the first signal and the fifth signal; Generating a second parity vector as a seventh signal by multiplying the inverse of the sixth signal by the fourth matrix; Generating a third parity vector as an eighth signal by multiplying the information vector by the seventh matrix; And assembling the information vector, the first parity vector, the second parity vector, and the third parity vector to generate the final block LDPC codeword. The method of claim 1, Generating the final block LDPC codeword; Generating a block LDPC codeword by encoding the information vector corresponding to the mother parity check matrix when the coding rate is a second encoding rate exceeding a first encoding rate that is a coding rate supported by the mother parity check matrix; , Puncturing the block LDPC codeword corresponding to the second code rate to generate the final LDPC codeword. The method of claim 7, wherein The mother parity check matrix includes an information part mapped to the information vector, a first parity part mapped to a first parity vector, and a second parity part mapped to a second parity vector. The method of claim 8, The information part includes a first matrix and a second matrix, the first parity part includes a third matrix and a fourth matrix, and the second parity part includes the fifth matrix and the sixth matrix. A signal transmission method characterized by the above-mentioned. The method of claim 9, Generating the final block LDPC codeword corresponding to the second code rate; Generating a first signal by multiplying the information vector by the first matrix; Generating a second signal by multiplying the information vector by the second matrix; Multiplying the first signal by a matrix product of the inverse of the third matrix and the fourth matrix to generate a third signal; Generating an first parity vector as a fourth signal by performing an exclusive OR operation on the second signal and the third signal; Multiplying the fourth signal by the fifth matrix to generate a fifth signal, and generating an sixth signal by performing an exclusive OR on the first signal and the fifth signal; Generating a second parity vector as a seventh signal by multiplying the inverse of the sixth signal by the fourth matrix; Puncturing a predetermined parity bit among the first parity vector and the second parity vector; And assembling the information vector, the punctured first parity vector and the second parity vector to generate the final block LDPC codeword. The method of claim 1, Generating a modulation vector by modulating the final block LDPC codeword vector using a predetermined modulation scheme; And transmitting the modulation vector. An apparatus for transmitting a signal in a communication system, An encoder for generating an information vector as a final block low density parity check (LDPC) codeword using a parent parity check matrix or a child parity check matrix generated based on the parent parity check matrix according to a coding rate. Signal transmission device comprising. The method of claim 12, And a first encoding rate that is a coding rate supported by the child parity check matrix is less than a second coding rate that is a coding rate supported by the parent parity check matrix. The method of claim 12, The child parity check matrix has a form including the parent parity check matrix. The method of claim 14, The child parity check matrix includes a first part corresponding to the parent parity check matrix and a second part other than the first part, wherein the first part includes an information part mapped to the information vector, and a first parity vector. And a second parity part mapped to a second parity vector, wherein the second part includes an additional information part mapped to the information vector and an additional agent mapped to the first parity vector. And a first parity part, an additional second parity part mapped to the second parity vector, and a third parity vector mapped to a third parity vector. The method of claim 15, The information part includes a first matrix and a second matrix, the first parity part includes a third matrix and a fourth matrix, the second parity part includes the fifth matrix and a sixth matrix, The additional information part includes a seventh matrix, the additional first parity part includes an eighth matrix, the additional second parity part includes a ninth matrix, and the third parity part includes a tenth matrix. And an eleventh matrix and a twelfth matrix. The method of claim 16, The encoder; Multiplying the information vector by the first matrix to generate a first signal, Multiplying the information vector by the second matrix to generate a second signal; Multiplying the first signal by a matrix product of the inverse of the third matrix and the fourth matrix to generate a third signal, An exclusive OR operation of the second signal and the third signal is performed to generate a first parity vector as a fourth signal, Generating a fifth signal by multiplying the fourth signal by the fifth matrix, and generating an sixth signal by performing an exclusive OR on the first signal and the fifth signal, Generating a second parity vector as a seventh signal by multiplying the sixth signal by an inverse of the fourth matrix, Multiplying the information vector by the seventh matrix to generate a third parity vector as an eighth signal, And the information vector, the first parity vector, the second parity vector, and the third parity vector are assembled to generate the final block LDPC codeword. The method of claim 12, The encoder; When the coding rate is a second coding rate that exceeds a first coding rate that is a coding rate supported by the parent parity check matrix, the information vector is encoded according to the parent parity check matrix to generate a block LDPC codeword. And puncturing the block LDPC codeword corresponding to the second code rate to generate the final LDPC codeword. The method of claim 18, The mother parity check matrix includes an information part mapped to the information vector, a first parity part mapped to a first parity vector, and a second parity part mapped to a second parity vector. The method of claim 19, The information part includes a first matrix and a second matrix, the first parity part includes a third matrix and a fourth matrix, and the second parity part includes the fifth matrix and the sixth matrix. A signal transmission device characterized in that. The method of claim 20, The encoder; Multiplying the information vector by the first matrix to generate a first signal, Multiplying the information vector by the second matrix to generate a second signal; Multiplying the first signal by a matrix product of the inverse of the third matrix and the fourth matrix to generate a third signal, An exclusive OR operation of the second signal and the third signal is performed to generate a first parity vector as a fourth signal, Generating a fifth signal by multiplying the fourth signal by the fifth matrix, and generating an sixth signal by performing an exclusive OR on the first signal and the fifth signal, Generating a second parity vector as a seventh signal by multiplying the sixth signal by an inverse of the fourth matrix, Puncturing a predetermined parity bit among the first parity vector and the second parity vector; And generating the final block LDPC codeword by assembling the information vector, the punctured first parity vector, and the second parity vector. The method of claim 12, The signal transmission device; A modulator for modulating the last block LDPC codeword vector using a preset modulation scheme to generate a modulation vector; And a transmitter for transmitting the modulation vector. In the method for receiving a signal in a signal receiving apparatus of a communication system, Restoring an information vector from an input signal using a parent parity check matrix or a child parity check matrix generated based on the parent parity check matrix, corresponding to the coding rate used by the signal transmitter corresponding to the signal receiving apparatus. Signal receiving method comprising. The method of claim 23, wherein And a first coding rate that is a coding rate supported by the child parity check matrix is less than a second coding rate that is a coding rate supported by the parent parity check matrix. The method of claim 23, wherein Restoring an information vector from the input signal; And if the coding rate used by the signal transmission apparatus is a coding rate supported by a self parity check matrix, restoring the information vector by reconstructing the input signal corresponding to the self parity check matrix. The method of claim 24, The child parity check matrix has a form including the parent parity check matrix. The method of claim 26, The child parity check matrix includes a first part corresponding to the parent parity check matrix and a second part other than the first part, wherein the first part includes an information part mapped to the information vector, and a first parity vector. And a second parity part mapped to a second parity vector, wherein the second part includes an additional information part mapped to the information vector and an additional agent mapped to the first parity vector. And a first parity part, an additional second parity part mapped to the second parity vector, and a third parity vector mapped to a third parity vector. The method of claim 27, The information part includes a first matrix and a second matrix, the first parity part includes a third matrix and a fourth matrix, the second parity part includes the fifth matrix and a sixth matrix, The additional information part includes a seventh matrix, the additional first parity part includes an eighth matrix, the additional second parity part includes a ninth matrix, and the third parity part includes a tenth matrix. And an eleventh matrix and a twelfth matrix. The method of claim 23, wherein Restoring an information vector from the input signal; Inserting 0 into the input signal at a predetermined position when the encoding rate used by the signal transmission apparatus is a second encoding rate exceeding a first encoding rate supported by the mother parity check matrix; Restoring the information vector by restoring the zero-inserted signal corresponding to the mother parity check matrix. In the signal receiving apparatus of the communication system, A decoder for restoring an information vector from an input signal using a parent parity check matrix or a child parity check matrix generated based on the parent parity check matrix, corresponding to a coding rate used by the signal transmitter corresponding to the signal receiving device. Signal receiving device comprising a. The method of claim 30, And a first encoding rate that is a coding rate supported by the child parity check matrix is less than a second encoding rate that is a coding rate supported by the parent parity check matrix. The method of claim 30, The decoder; And when the coding rate used by the signal transmission apparatus is a coding rate supported by a self parity check matrix, recovering the information vector by reconstructing the input signal corresponding to the self parity check matrix. 33. The method of claim 32, And the child parity check matrix has a form including the parent parity check matrix. The method of claim 33, wherein The child parity check matrix includes a first part corresponding to the parent parity check matrix and a second part other than the first part, wherein the first part includes an information part mapped to the information vector, and a first parity vector. And a second parity part mapped to a second parity vector, wherein the second part includes an additional information part mapped to the information vector and an additional agent mapped to the first parity vector. And a first parity part, an additional second parity part mapped to the second parity vector, and a third parity vector mapped to a third parity vector. The method of claim 34, wherein The information part includes a first matrix and a second matrix, the first parity part includes a third matrix and a fourth matrix, the second parity part includes the fifth matrix and a sixth matrix, The additional information part includes a seventh matrix, the additional first parity part includes an eighth matrix, the additional second parity part includes a ninth matrix, and the third parity part includes a tenth matrix. And an eleventh matrix and a twelfth matrix. The method of claim 30, The decoder; If the code rate used by the signal transmission apparatus is a second code rate exceeding the first code rate supported by the parent parity check matrix, zero is inserted into the input signal at a predetermined position, and the zero-inserted signal is input. And reconstructing the information vector by reconstructing corresponding to the mother parity check matrix. The method of claim 5, Each of the third matrix, the fifth matrix, and the sixth matrix includes a plurality of blocks, Permutation matrices are mapped to two blocks among blocks included in the binary matrix of the third matrix, Permutation matrices are mapped to blocks positioned diagonally among the blocks included in the fifth matrix, and permutation matrices are mapped to blocks forming a double diagonal structure with the diagonal. The permutation matrix is mapped to one of the blocks included in the sixth matrix. The method of claim 16, Each of the third matrix, the fifth matrix, and the sixth matrix includes a plurality of blocks, Permutation matrices are mapped to two blocks among blocks included in the binary matrix of the third matrix, Permutation matrices are mapped to blocks positioned diagonally among the blocks included in the fifth matrix, and permutation matrices are mapped to blocks forming a double diagonal structure with the diagonal. The permutation matrix is mapped to one of the blocks included in the sixth matrix. The method of claim 28, Each of the third matrix, the fifth matrix, and the sixth matrix includes a plurality of blocks, Permutation matrices are mapped to two blocks among blocks included in the binary matrix of the third matrix, Permutation matrices are mapped to blocks positioned diagonally among the blocks included in the fifth matrix, and permutation matrices are mapped to blocks forming a double diagonal structure with the diagonal. The permutation matrix is mapped to one of the blocks included in the sixth matrix. 36. The method of claim 35 wherein Each of the third matrix, the fifth matrix, and the sixth matrix includes a plurality of blocks, Permutation matrices are mapped to two blocks among blocks included in the binary matrix of the third matrix, Permutation matrices are mapped to blocks positioned diagonally among the blocks included in the fifth matrix, and permutation matrices are mapped to blocks forming a double diagonal structure with the diagonal. The permutation matrix is mapped to one of the blocks included in the sixth matrix.

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