KR20070104076A - Driving circuit for image display device and method for driving the same - Google Patents

Abstract

An apparatus and a method for driving an image display device are provided to prevent display error due to mismatching between an image output timing and an input timing of synchronous signals by displaying a black image. An apparatus for driving an image display device includes a display panel, a driver and a controller. The controller includes a detecting unit(241), a synchronous signal generator(242), a control signal generator(243), an image processing unit(244) and a determiner(245). The detecting unit generates a first operation signal when at least one synchronous signals are not received. The synchronous signal generator generates a first data enable signal in response to the first operation signal. The control signal generator generates gate and data control signals in response to the first data enable signal. The image processing unit outputs predetermined image data in response to the first data enable signal. The determiner outputs a second operation signal to the detecting unit when the at least one synchronous signals are not synchronized with the control signals from the control signal generator.

Description

Driving device for image display device and driving method thereof {Driving circuit for image display device and method for driving the same}

1 is a timing diagram showing waveforms of synchronization signals and data input to a driving apparatus of a conventional liquid crystal display.

2 is a configuration diagram showing a driving device of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a detailed configuration diagram showing a control unit according to the first embodiment of the present invention.

FIG. 4 is a timing diagram illustrating waveforms of input and output signals of the controller illustrated in FIG. 3.

5 is a detailed block diagram showing a control unit according to a second embodiment of the present invention.

FIG. 6 is a timing diagram illustrating waveforms of input and output signals of the controller illustrated in FIG. 5.

* Explanation of symbols on the main parts of the drawings

240 control unit 241 detection unit

242: synchronization signal generator 243: control signal generator

244: image processing unit 245: determination unit

DCLK: main clock DE1: first data enable signal

Vsync: Vertical Sync Signal Hsync: Horizontal Sync Signal

GCS: gate control signal DCS: data control signal

The present invention relates to a driving device of an image display device and a driving method thereof capable of preventing a screen abnormality caused by an unstable synchronization signal.

Recently, various image display apparatuses that can reduce weight and volume, which are disadvantages of cathode ray tubes, have emerged. Such image display apparatuses include a liquid crystal display, a field emission display, a plasma display panel, a light emitting display, and the like.

 Here, the liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal cells according to the video signal. An active matrix type liquid crystal display device in which switching elements are formed for each liquid crystal cell is suitable for displaying moving images. As a switching element used in an active matrix liquid crystal display device, a thin film transistor (hereinafter, referred to as TFT) is mainly used.

Such a liquid crystal display may be classified into a liquid crystal panel displaying an image signal and a driving device applying a driving signal to the liquid crystal panel.

Although not shown in the drawings, the liquid crystal panel is a display device in which a liquid crystal is injected between two substrates bonded to each other with a predetermined space, and one of the two substrates includes a plurality of gate lines and a plurality of data lines for driving the liquid crystal. A plurality of pixel electrodes formed in each pixel region defined by each gate line and data line, and a plurality of thin film transistors that apply a signal of a data line to each pixel electrode according to a signal of each gate line. do. The color filter layer, the common electrode, and the black matrix layer are formed on the remaining substrates. Therefore, when the turn-on signal is sequentially applied to each gate line, an image is displayed because a data signal is applied to the pixel electrode of the corresponding line at each time.

In addition, the driving apparatus of the liquid crystal display device includes a gate driver for driving a gate line, a data driver for driving a data line, and supplying image data input from the outside to the data driver and controlling the data driver and simultaneously controlling the gate driver. It has a control unit for controlling.

However, the driving device of the conventional liquid crystal display device configured as described above cannot generate the gate control signal and the data control signal when the synchronization signals input from the outside are not input. Therefore, when the gate control signal and the data control signal are not generated, the image data cannot be displayed on the liquid crystal panel, and thus an operation of turning off / on the power applied to the liquid crystal panel is performed.

1 is a timing diagram illustrating waveforms of synchronization signals and data input to a driving apparatus of a conventional liquid crystal display.

As shown in FIG. 1, the synchronization signals are classified into a data enable signal DE, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal divided into a main clock DCLK (not shown). (DE) defines a valid section and a blank section in which RGB image data is transmitted every 1 frame (1F). In addition, a data valid section and a blank section of the data enable signal DE may be distinguished in each horizontal section.

The “A” section represents a section in which the synchronization signals DCLK, DE, Hsync, and Vsync are not input. In the “A” section, the gate control signal and the data control signal are not generated. It is a section to turn on.

In detail, when the resolution of the image displayed on the liquid crystal panel is changed or the driving frequency is changed, or when the size of the region where the video is displayed is changed, the synchronization signals DCLK, DE, Hsync, and Vsync are modulated and input. In this case, the synchronization signals DCLK, DE, Hsync, and Vsync are not instantaneously input. At this time, the operation of turning off / on the power of the liquid crystal panel and generating a gate control signal and a data control signal according to the modulated synchronization signal to display image data on the liquid crystal panel. Therefore, the inconvenience of turning off / on the power of the liquid crystal panel and the timing of the power off / on and the timing of generation of the gate control signal and the data control signal are not synchronized. A problem occurs.

The present invention is to solve the above problems, and when the at least one synchronization signal and the at least one control signal is not synchronized to generate a stable data enable signal, a stable control signal using a stable data enable signal It is an object of the present invention to provide a driving device of an image display device capable of generating and outputting predetermined image data and a driving method thereof.

The driving apparatus of the liquid crystal display according to the embodiment of the present invention for achieving the above object is at least one of a display panel for displaying an image, a driver for driving the display panel, and a plurality of synchronization signals input from the outside. The driving unit is configured to generate at least one control signal for controlling the driving unit by using one synchronization signal, and to display an image set on the display panel according to whether the at least one synchronization signal and at least one control signal are synchronized. It characterized in that it comprises a control unit for controlling.

According to an aspect of the present invention, there is provided a method of driving a liquid crystal display device, the method including generating and outputting control signals using at least one synchronization signal from among synchronization signals from the outside. Determining whether the synchronization signal is synchronized with the at least one control signal, generating an internal synchronization signal according to the synchronization, generating and outputting control signals using the internal synchronization signal, and the internal And outputting predetermined image data in response to the synchronization signal.

Hereinafter, a driving apparatus and a driving method of a liquid crystal display according to an exemplary embodiment of the present invention having the above characteristics will be described in detail with reference to the accompanying drawings.

2 is a configuration diagram illustrating a driving device of a liquid crystal display according to an exemplary embodiment of the present invention.

The driving device of the liquid crystal display shown in FIG. 2 includes a liquid crystal panel 110 having n gate lines GL1 to GLn and m data lines DL1 to DLm arranged in a direction perpendicular to each other, and a gate line. Gate driver 120 for driving the GL1 to GLn, data driver 130 for driving the data lines DL1 to DLm, and synchronization signals DCLK, DE1, Hsync, Vsync) detects a case where at least one signal is not input or is not synchronized to generate a stable data enable signal, and generates a data control signal DCS and a gate control signal GCS according to the generated data enable signal. The controller 140 controls the gate driver 120 and the data driver 130.

The liquid crystal panel 110 is connected to the thin film transistor TFT formed in each pixel region defined by n gate lines GL1 to GLn and m data lines DL1 to DLm, and is connected to the thin film transistor TFT. A pixel electrode for driving a molecule is provided. The thin film transistor TFT supplies a data signal from the data lines DL1 to DLm to the pixel electrode in response to a scan pulse from the gate lines GL1 to GLn. The pixel electrode forms the common electrode and the liquid crystal capacitor Clc with the liquid crystal interposed therebetween, and forms the previous gate lines GL1 to GLn and the storage capacitor Cst. The liquid crystal capacitor Clc and the storage capacitor Cst maintain a data signal applied to the pixel electrode until the next data signal is charged.

The gate driver 120 sequentially generates a scan pulse, that is, a gate high pulse, in response to the gate start pulse GSP and the gate shift clock GSC among the gate control signals GCS from the controller 140. It includes. In response to this scan pulse, the thin film transistor TFT is turned on.

The data driver 130 converts the image data of the digital signal into the image data of the analog signal according to the data control signal DCS supplied from the controller 140. In addition, analog image data for one horizontal line is supplied to the data lines DL1 to DLm every horizontal period in which scan pulses are supplied to the gate lines GL1 to GLn. That is, the data driver 130 selects a gamma voltage having a predetermined level according to the gray value of the image data Data, and supplies the selected gamma voltage to the data lines DL1 to DLm.

The controller 140 arranges the image data RGB from the outside to be suitable for driving the liquid crystal panel 110 and supplies the image data RGB to the data driver 130. In addition, the gate driver 120 and the data driver 130 are controlled by generating the gate control signal GCS and the data control signal DCS using the synchronization signals DCLK, DE1, Hsync, and Vsync. The gate control signal GCS and the data control signal DCS may be generated using only the first data enable signal DE1.

Meanwhile, the controller 140 generates a second data enable signal when at least one of the synchronization signals DCLK, DE1, Hsync, and Vsync is not input or not synchronized. The data control signal DCS and the gate control signal GCS are generated using the second data enable signal to control the driving timing of the data driver 130 and the gate driver 120. In addition, the data of the preset black gradation are output using the second data enable signal.

3 is a detailed block diagram showing a control unit according to the first embodiment of the present invention.

As shown in FIG. 3, the control unit 140 according to the first embodiment of the present invention has the first operation signal CSet1 when the synchronization signals DCLK, DE1, Hsync, and Vsync input from the outside are not input. A detection unit 141 for outputting a signal, a synchronization signal generation unit 142 for generating and outputting a second data enable signal DE2 according to the first operation signal CSet1, and a second data enable signal DE2. Control signal generation unit 143 for generating and outputting the gate control signal GCS and the data control signal DCS, and receiving the second data enable signal DE2 to output only black grayscale data. It includes a processing unit 144.

The detector 141 supplies the first data enable signal DE1 among the sync signals DCLK, DE1, Hsync and Vsync to the image processor 144 when the sync signals DCLK, DE1, Hsync and Vsync are input. At the same time, the first data enable signal DE1, the horizontal sync signal Hsync, and the vertical sync signal Vsync are supplied to the control signal generator 143. However, if at least one of the synchronization signals DCLK, DE1, Hsync, and Vsync is not input, the detector 141 stops the output of the synchronization signals DCLK, DE1, Hsync, and Vsync, and the first operation signal. (CSet1) is generated and supplied to the synchronization signal generation unit 142.

The synchronization signal generator 142 generates a second data enable signal DE2 when the first operation signal CSet1 is input from the detector 141 to simultaneously transmit the second data enable signal DE2 to the image processor 144 and the control signal generator 143. Supply. In this case, the second data enable signal DE2 is a signal having a predetermined pulse width and is generated at a predetermined period. The second data enable signal DE2 is preferably generated to match the first data enable signal DE1 as much as possible.

The control signal generator 143 generates the gate control signal GCS and the data control signal DCS by using the synchronization signals DCLK, DE1, Hsync, and Vsync supplied from the detector 141 to generate the gate driver 120. ) And the data driver 130. However, when the second data enable signal DE2 is input from the sync signal generator 142 without the sync signals DCLK, DE1, Hsync and Vsync supplied, only the second data enable signal DE2 is used. The gate control signal GCS and the data control signal DCS are generated to control the gate driver 120 and the data driver 130. Here, since the second data enable signal DE2 is input with a pulse width of a predetermined period, the gate control signal GCS and the data control signal DCS have a constant pulse width of the second data enable signal DE2. It is preferable that the black image is generated to be displayed on the liquid crystal panel 110 as a whole.

The image processor 144 arranges the image data RGB input from the outside to be suitable for driving the liquid crystal panel 110 and supplies the image data RGB to the data driver 130. However, when the second data enable signal DE2 is input from the synchronization signal generator 142, only the black gray image data is supplied to the data driver 130 to be synchronized with the second data enable signal DE2.

4 is a timing diagram illustrating waveforms of input and output signals of the controller illustrated in FIG. 3.

The controller 140 illustrated in FIG. 4 is divided into a first data enable signal DE1, a vertical sync signal Vsync, a horizontal sync signal Hsync, and a main clock DCLK not shown in the drawing. The gate start pulse GSP is a signal for enabling the gate driver 120 among the gate control signals GCS, and the data start pulse DSP is a signal for enabling the data driver 130 among the data control signals DCS. to be. Here, the first data enable signal DE1 defines an effective section and a blank section in which RGB image data is transmitted every 1 frame (1F). In addition, a data valid section and a blank section of the data enable signal DE may be distinguished in each horizontal section.

The “A” section represents a section in which the synchronization signals DCLK, DE1, Hsync, and Vsync are not input. When the “A” section starts, the second data enable signal DE2 is generated to generate black gray data ( black is displayed on the liquid crystal panel 110. That is, as the detection unit 141 generates the first operation signal CSet1 and supplies it to the synchronization signal generator 142, the synchronization signal generator 142 generates the second data enable signal DE2 to generate an image processor. Since the data is simultaneously supplied to the control unit 144 and the control signal generator 143, the black data of the black tone output from the image processor 144 is output to the liquid crystal panel 110.

The driving method of the liquid crystal display according to the first embodiment of the present invention will be described in detail with reference to FIGS. 3 to 4 as follows.

First, when a case in which at least one of the synchronization signals DCLK, DE1, Hsync, and Vsync that are input from the outside does not occur, the detector 141 generates the first operation signal CSet1 to generate the synchronization signal generator. 142 is supplied. When the first operation signal CSet1 is input, the synchronization signal generator 142 generates a second data enable signal DE2 and supplies it to the image processor 144 and to the control signal generator 143. The control signal generator 143 generates the gate control signal GCS and the data control signal DCS by using the second data enable signal DE2, and supplies them to the gate driver 120 and the data driver 130, respectively. do. In this case, the image processor 144 supplies the black data of the gray data to the data driver 130 in response to the second data enable signal DE2. Therefore, the black image is displayed on the liquid crystal panel 110.

After that, when the synchronization signals DCLK, DE1, Hsync, and Vsync are normally input to the detection unit 141, the first operation signal CSet1 is no longer output, and the input synchronization signals DCLK, DE1, Hsync, and Vsync are no longer output. ) Is supplied to the control signal generator 143 and the first data enable signal DE1 among the synchronization signals DCLK, DE1, Hsync and Vsync is supplied to the image processor 144. Since the first operation signal CSet1 is not applied, the sync signal generator 142 does not generate the second data enable signal DE2 any more. In addition, the control signal generator 143 generates the gate control signal GCS and the data control signal DCS by using the input synchronization signals DCLK, DE1, Hsync, and Vsync. Supply to the data driver 130, respectively. In this case, the image processor 144 arranges the image data RGB input from the outside in response to the first data enable signal DE1 to be suitable for driving the liquid crystal panel 110 and supplies the image data to the data driver 130. Image data RGB is displayed on the liquid crystal panel 110.

Accordingly, the driving apparatus and driving method thereof of the liquid crystal display according to the first exemplary embodiment of the present invention may include the liquid crystal panel 110 when at least one of the synchronization signals DCLK, DE1, Hsync, and Vsync is not input. You can display a black image on the screen. Therefore, the inconvenience of turning off / on the power source can be solved conventionally. In addition, when the power is turned off / on, the timing at which the power is turned off / on, the timing at which the image is output, and the timing at which the synchronization signals DCLK, DE1, Hsync, and Vsync are not matched may cause the displayed image to be broken or blurred. I can solve it.

5 is a detailed block diagram illustrating a control unit according to a second embodiment of the present invention.

The control unit 240 shown in FIG. 5 is a detector 241 that generates a first operation signal CSet1 when at least one of the synchronization signals DCLK, DE1, Hsync, and Vsync input from the outside is not input. And a synchronization signal generator 242 for generating and outputting a second data enable signal DE2 when the first operation signal CSet1 is input, and a second data enable input from the synchronization signal generator 242. A control signal generator 243 for generating and outputting a gate control signal GCS and a data control signal DCS using the signal DE2, and a second data enable signal input from the synchronization signal generator 242. The image processor 244 outputs black gray data according to DE2, and inputs all of the synchronization signals DCLK, DE1, Hsync, and Vsync, the gate control signal GCS, and the data control signal DCS. Receive the synchronization signals DCLK, DE1, Hsync and Vsync, the gate control signal GCS and the data control signal DCS. It determines whether the synchronization, and if the at least one signal is not synchronized includes a determination unit 245 for outputting the second operation signal (CSet2).

When the synchronization signals DCLK, DE1, Hsync, and Vsync are input, the detector 241 supplies the first data enable signal DE1 among the synchronization signals DCLK, DE1, Hsync, and Vsync to the image processor 244. At the same time, the first data enable signal DE1, the horizontal sync signal Hsync, and the vertical sync signal Vsync are supplied to the control signal generator 243. However, if at least one of the synchronization signals DCLK, DE1, Hsync, and Vsync is not input, the supply of the synchronization signals DCLK, DE1, Hsync, and Vsync is stopped and the first operation signal CSet1 is generated. The synchronization signal generator 242 is supplied. In addition, the detector 241 stops output of the synchronization signals DCLK, DE1, Hsync, and Vsync in response to the input of the second operation signal CSet2 from the determination unit 245, and the first operation signal CSet1. ) Is supplied to the sync signal generator 242.

The synchronization signal generator 242 generates a second data enable signal DE2 when the first operation signal CSet1 is input from the detector 241 to simultaneously transmit the second data enable signal DE2 to the image processor 244 and the control signal generator 243. Supply. In this case, the second data enable signal DE2 is a signal generated at a predetermined cycle having a predetermined predetermined pulse width and is preferably generated to match the first data enable signal DE1 as much as possible.

The control signal generator 243 generates the gate control signal GCS and the data control signal DCS by using the synchronization signals DCLK, DE1, Hsync, and Vsync supplied from the detector 241 to generate the gate driver 120. ) And the data driver 130. The gate control signal GCS and the data control signal DCS may be generated using only the first data enable signal DE1. However, when the second data enable signal DE2 is input from the sync signal generator 242 without the sync signals DCLK, DE1, Hsync, and Vsync, only the second data enable signal DE2 is input. The gate driver 120 and the data driver 130 are controlled by generating a gate control signal GCS and a data control signal DCS.

Here, since the second data enable signal DE2 is input with a pulse width of a predetermined period, the gate control signal GCS and the data control signal DCS have a constant pulse width of the second data enable signal DE2. It is preferable that the black image is generated to be displayed on the liquid crystal panel 110 as a whole.

The image processor 244 arranges the image data RGB input from the outside to be suitable for driving the liquid crystal panel 110 and supplies the image data RGB to the data driver 130. However, when the second data enable signal DE2 is input from the synchronization signal generator 242, only black data of black gray is supplied to the data driver 130 to be synchronized with the second data enable signal DE2. .

The determination unit 245 receives all of the synchronization signals DCLK, DE1, Hsync, and Vsync, the gate control signal GCS, and the data control signal DCS to receive the synchronization signals DCLK, DE1, Hsync, and Vsync. It is determined whether the control signal GCS and the data control signal DCS are synchronized, and when the at least one signal is not synchronized, the second operation signal CSet2 is generated and output to the detection unit 241. Specifically, the synchronization signal DCLK, DE1, Hsync, Vsync and the gate start pulse GSP of the gate control signal GCS are compared with the data start pulse DSP of the data control signal DCCS to determine whether to synchronize. do. When the at least one synchronization signal DCLK, DE1, Hsync, Vsync, the gate start pulse GSP, and the data start pulse DSP are not synchronized, the second operation signal CSet2 is generated to detect the detection unit 241. Will output

FIG. 6 is a timing diagram illustrating waveforms of input / output signals of the controller illustrated in FIG. 5.

The control unit 240 shown in FIG. 6 is supplied with a first data enable signal DE1, a vertical sync signal Vsync, a horizontal sync signal Hsync, and a main clock DCLK not shown. The gate start pulse GSP is a signal for enabling the gate driver 120 among the gate control signals GCS, and the data start pulse DSP is a signal for enabling the data driver 130 among the data control signals DCS. to be. Here, the first data enable signal DE1 defines an effective section and a blank section in which RGB image data is transmitted every 1 frame (1F). In addition, a data valid section and a blank section of the data enable signal DE may be distinguished in each horizontal section.

In the “B” section, at least one sync signal DCLK, DE1, Hsync, Vsync and the gate start pulse GSP of the gate control signal GCS and the data start pulse DSP of the data control signal DCS are not synchronized. In this case, since the display quality of the image is deteriorated, the synchronization signals DCLK, DE1, Hsync, and Vsync, the gate control signal GCS, and the data control signal DCS must be corrected. . Therefore, when the " B " section starts, the second data enable signal DE2 is generated to display black data of gray data on the liquid crystal panel 110. FIG.

The second operation signal CSet2 is generated when the at least one synchronization signal DCLK, DE1, Hsync, Vsync, the gate start pulse GSP, and the data start pulse DSP are not synchronized.

That is, the determination unit 245 synchronizes the synchronization signals DCLK, DE1, Hsync and Vsync with the gate start pulse GSP among the gate control signal GCS and the data start pulse DSP among the data control signal DCS. When not determined, the second operation signal CSet2 is generated and supplied to the detector 241 so that the detector 241 transmits the synchronization signals DCLK, DE1, Hsync, and Vsync to the control signal generator 243. The first operation signal CSet1 is not generated and supplied to the synchronization signal generator 242. Here, the detector 241 generates the first operation signal CSet1 for three frame periods 3F (3frames). Therefore, the sync signal generator 242 generates the second data enable signal DE2 for three frame periods and simultaneously supplies the sync signal generator 242 to the image processor 244 and the control signal generator 243. The black data is output to the liquid crystal panel 110 for three frame periods. Then, at the end of the " B " period, the gate control signal GCS and the data control signal DCS are generated using the synchronization signals DCLK, DE1, Hsync and Vsync to generate the synchronization signals DCLK, DE1 and Hsync. And Vsync are synchronized with the gate control signal GCS and the data control signal DCS.

The driving method of the liquid crystal display according to the second exemplary embodiment of the present invention will be described in detail with reference to FIGS. 5 and 6 as follows.

First, when the synchronization signals DCLK, DE1, Hsync, and Vsync are input from the outside, the detector 241 may output the first data enable DE1 signal among the synchronization signals DCLK, DE1, Hsync, and Vsync. At the same time, the data first data enable signal DE1, the horizontal sync signal Hsync, and the vertical sync signal Vsync are supplied to the control signal generator 243. The image processor 244 arranges and supplies the image data RGB input from the outside to the data driver 130 in synchronization with the first data enable signal DE1. At this time, the control signal generator 243 uses the supplied first data enable signal DE1, the horizontal sync signal Hsync, and the vertical sync signal Vsync to control the gate control signal GCS and the data control signal GCS. ) Is supplied to the gate driver 120 and the data driver 130. Meanwhile, the determination unit 245 receives the synchronization signals DCLK, DE1, Hsync, and Vsync, the gate control signal GCS, and the data control signal GCS to receive the synchronization signals DCLK, DE1, Hsync, and Vsync. It is determined whether the gate control signal GCS and the data control signal GCS are synchronized. Here, when at least one of the synchronization signals DCLK, DE1, Hsync, Vsync, the gate control signal GCS, and the data control signal GCS is not synchronized, the second operation signal CSet2 is generated and detected by the detection unit. Supply to (241). When the second operation signal CSet2 is input, the detector 241 stops the output of the synchronization signals DCLK, DE1, Hsync, and Vsync and generates the first operation signal CSet1 to the synchronization signal generator 242. Supply. When the first operation signal CSet1 is applied, the synchronization signal generator 242 generates the second data enable signal DE2 and supplies it to the image processor 244 and to the control signal generator 243. The control signal generator 243 generates the gate control signal GCS and the data control signal DCS by using the second data enable signal DE2 and supplies them to the gate driver 120 and the data driver 130, respectively. do. In this case, the image processor 244 supplies the data of the black gradation to the data driver 130 in response to the second data enable signal DE2. Therefore, the black image is displayed on the liquid crystal panel 110. Here, the detector 241 outputs the first operation signal CSet1 for three frame periods, and again outputs the first data enable signal DE1 among the synchronization signals DCLK, DE1, Hsync, and Vsync. The data first data enable signal DE1, the horizontal sync signal Hsync, and the vertical sync signal Vsync are supplied to the control signal generator 243. Therefore, the synchronization signal generator 242 does not generate the second data enable signal DE2 any more as the first operation signal CSet1 is not input. In addition, the control signal generator 243 generates the gate control signal GCS and the data control signal DCS using the input synchronization signals DCLK, DE1, Hsync, and Vsync, and the gate driver 120 and the gate driver 120. Supply to the data driver 130, respectively. In this case, the image processor 244 arranges the image data RGB input from the outside in response to the first data enable signal DE1 to be suitable for driving the liquid crystal panel 110, and supplies the image data to the data driver. The image data RGB is displayed on the display 110.

As described above, the driving device and the driving method of the liquid crystal display according to the second exemplary embodiment of the present invention do not input at least one of the synchronization signals DCLK, DE1, Hsync, and Vsync, The black image may be displayed when at least one of the DCLK, DE1, Hsync, Vsync, the gate control signal GCS, and the data control signal DCS is not synchronized. Accordingly, the display quality of the image may be reduced when the synchronization signals DCLK, DE1, Hsync, and Vsync and the control signals GCS and DCS are not synchronized with each other. Eliminates inconvenience of turning on / off, and displays when the power is turned off / on, the timing at which the image is output, and the timing at which the synchronization signals DCLK, DE1, Hsync, and Vsync are not matched. This can solve the problem of broken or blurred.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

As described above, the liquid crystal display and the driving method thereof according to the present invention have the following effects.

The black image is displayed when at least one of the synchronization signals input from the outside is not input or when at least one of the synchronization signals, the gate control signal, and the data control signal is not synchronized. Therefore, the inconvenience of turning off / on the power in the related art is eliminated, and the displayed image is broken because the timing at which the power is turned off / on and the timing at which the image is output and the timing at which the synchronization signals are input do not match. The problem of blurring can be solved.

Claims (10)

A display panel displaying an image; A driving unit driving the display panel; And, At least one control signal for controlling the driving unit is generated using at least one synchronization signal among a plurality of synchronization signals input from an external device, and the synchronization signal is synchronized with the at least one synchronization signal. And a control unit which controls the driving unit to display an image set on a display panel. The method of claim 1, The driving unit A gate driver supplying scan pulses to the display panel; And a data driver for supplying an image signal to the display panel. The method of claim 1, The control unit A detector configured to generate a first operation signal when the at least one synchronization signal is not input; A synchronization signal generator for generating and outputting a first data enable signal in response to a first operation signal from the detector; A control signal generator for generating and outputting a gate control signal and a data control signal in response to a first data enable signal from the synchronization signal generator; An image processor configured to output preset image data in response to a first data enable signal from the synchronization signal generator; And, And a determination unit configured to determine whether the at least one synchronization signal input from the detection unit and the at least one control signal input from the control signal generation unit are synchronized to generate a second operation signal in asynchronous manner, and to output the second operation signal to the detection unit. An apparatus for driving an image display device. The method of claim 3, wherein The detection unit When the synchronization signals are normally input, the synchronization signals are supplied to the control signal generator, and when the second operation signal is input from the determination unit, the synchronization signals are stopped and the first operation signal is supplied to the synchronization signal. A driving apparatus of an image display apparatus, which outputs to a generation unit. The method of claim 3, wherein The control signal generator The gate control signal and the data control signal are generated and output using the synchronization signals from the detection unit. When the first data enable signal is input, the gate control signal and the data control signal are generated using only the first data enable signal. And a drive device for an image display device. The method of claim 3, wherein The image processor Image data is output in response to the second data enable signal input from the detection unit, and when a first data enable signal is input from the synchronization signal generator, data of black gradation in response to the first data enable signal is output. A drive device for an image display device, characterized by outputting only bay. Generating and outputting control signals using at least one synchronization signal from among synchronization signals from the outside; Determining whether the at least one synchronization signal is synchronized with the at least one control signal; Generating an internal synchronization signal according to the synchronization; Generating and outputting control signals using the internal synchronization signal; And, And outputting predetermined image data in response to the internal synchronization signal. The method of claim 7, wherein Generating the internal synchronization signal And generating the internal synchronization signal when the at least one synchronization signal is not input. The method of claim 7, wherein The step of determining whether the synchronization And determining when the at least one synchronization signal, a gate start pulse of the gate control signal, and a data start pulse of the data control signal are not synchronized. The method of claim 7, wherein The preset image data is And a black gradation data for displaying only a black image on the front surface of the liquid crystal panel.

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