KR20070093161A - Control circuit device of digital instrument and power control method for digital instrument using the same - Google Patents

Abstract

A control circuit device for a digital appliance and a power control method of the digital appliance using the same are provided to boot an SoC(System on Chip) having a processor fast by using an STR(Suspend To RAM) method. When a power shutdown instruction is received(S102), it is determined whether a power shutdown sequence is set to a fast boot mode(S104). If the power shutdown sequence is not set to the fast boot mode, SoC power and external memory power are shut off(S120). If the power shutdown sequence is set to the fast boot mode, system backup is performed(S106). A shutdown instruction of SoC main power is given(S108). An external memory is set to a self refresh mode(S110). If a power supply instruction is received while the external memory is set to the self refresh mode, an STR booting process is performed(S112). It is determined whether a memory card is removed(S114). If the memory card is removed, a shutdown instruction of the external memory power is given(S118).

Description

Control circuit device for digital devices and power control method for digital devices using the same {control circuit device of digital instrument and power control method for digital instrument using the same}

1 is a power-off sequence by the STR technique of a conventional SoC.

2 is a block diagram illustrating a control circuit device for a digital device according to an embodiment of the present invention.

FIG. 3 is a block diagram illustrating an exemplary embodiment of the SoC power control unit 100 of FIG. 2.

4 is a block diagram for explaining another preferred embodiment of the SoC power control unit 100 of FIG.

FIG. 5 is a block diagram illustrating an exemplary embodiment of an internal configuration of the memory card detector 60 of FIG. 2.

6 and 7 are flowcharts illustrating a power control method using the fast boot method of the present invention performed by the control circuit device for the digital device of FIG. 2.

8 is a block diagram illustrating an internal configuration of a digital camera as an example of a digital apparatus equipped with a control circuit device for a digital apparatus of the present invention.

The present invention relates to a control circuit device for a digital device and a power supply control method for a digital device to be booted quickly by using a suspend to RAM (STR) technique in a system on chip (SoC) having a processor.

The booting of electronic products can be largely divided into cold booting and warm booting.

Cold booting refers to a case in which power is booted at power on after power off.

In contrast, warm booting is a case where a reboot is performed without power off.

When cold booting after power off, the CPU clock setting, DRAM initialization, and if necessary, load a product's execution program from ROM to RAM, and then perform many initialization operations. Therefore, a cold boot takes a lot of boot time.

To solve this cold boot time problem, a technique called suspend to RAM (STR) is designed to supply only RAM when the product is turned off.

1 is a power-off sequence by the STR technique of a conventional SoC.

When the power off instruction occurs in the normal operation state (S10) (S20), when not in the STR boot (S30), the SoC power and SDRAM power are all cut off (S70). The boot in this case is cold boot.

When the power-off instruction occurs in the normal operation state (S10) (S20), in the case of STR booting (S30), the built-in processor of the SoC performs a system backup (S40), and puts the SDRAM into the self refresh mode. After setting (S50), the SoC built-in processor itself enters a sleep mode (S60). In the STR technique, by using the self-refresh mode of the SDRAM, the data written to the RAM is maintained, and if the data is written by reading the RAM at boot time, only the CPU clock is set and the data is written without any other initialization operation. The code jumps to the RAM address. This saves time during the initial startup process, such as RAM initialization or moving executable programs from ROM to RAM.

When the SoC's embedded processor goes to sleep to use the STR technique in these SoCs, a negligible amount of leakage current flows. With the recent trend of digital convergence, the amount of leakage current increases as the components integrated into the SoC increase.

In consideration of this leakage current problem, the system is controlled by using a separate external processor with a small leakage current to use the STR technique instead of putting the SoC in sleep mode. There is also.

The present invention is to provide a control circuit for a digital device having a SoC that can use the STR technique that can reduce the leakage current without using a separate external processor and a power control method of the digital device using the same. have.

According to an aspect of the present invention, there is provided a control circuit device for a digital device, including: an external memory capable of a self-less operation; An internal processor that controls each electronic component of a digital device, a memory controller for setting the external memory to the self-refresh mode, a first control signal SoC_power_on for switching the SoC main power, and a second control for switching the external memory power A SoC unit having a SoC power control unit for outputting a signal ram_power_on; Detects whether a memory card is inserted and outputs the second control signal as a third control signal as it is, regardless of whether the memory card is inserted when the first control signal is on, and the first control signal is off and the memory card Outputs the second control signal as the third control signal as it is, and outputs the third control signal in the off state when the first control signal is off and the memory card is not inserted. A memory card detector; A SoC backup power unit (VDD_KAU) connected to a backup battery for supplying power to the SoC power control unit, an SoC main power unit for supplying / blocking the main power (VDD_SoC) to the SoC according to the first control signal, and the third control signal. A power supply unit including an external memory power supply unit supplying / blocking power of the external memory; And an operation button for receiving a power from the backup power supply unit to generate a power supply / discharge instruction signal, wherein the SoC power controller is configured to instruct the power off while the internal processor sets the power down sequence to the fast boot mode. When is input, the first control signal is turned off and output, and the second control signal is characterized in that to maintain the on state.

The memory card detection unit is a tri-state buffer, wherein the first control signal is connected to an inverse enable terminal, the memory card insertion detection result is connected to an input terminal, An output terminal comprising: a first buffer connected to the SoC backup power supply with a pull-up resistor; And a second buffer, wherein the output terminal of the first buffer is connected to an enable terminal, the second control signal is connected to an input terminal, and the output terminal has a second buffer connected to a ground by a pull-down resistor. The third control signal may be output through the output terminal of the second buffer.

The SoC power control unit may include a timer circuit that checks the elapse of a predetermined time after the first control signal is turned off.

The SoC power control unit, the SoC unit further comprises a real time clock (RTC) is supplied from the SoC backup power supply, the clock used in the SoC power control unit is preferably provided by the RTC.

In addition, the power control method of the digital device for achieving the above technical problem, in order to implement a control sequence of the power off / supply in the digital device having the control circuit device, when the power off instruction is input to the fast boot mode ( determining whether it is set to a fast boot mode; Instructing to turn off the SoC power supply and the external memory power when the fast boot mode is not set; Performing a system backup when set to a fat boot mode; Instructing the SoC main power to shut off; Setting the external memory to the self refresh mode; Performing a suspend to RAM (STR) boot process when a power supply instruction is input while the external memory is set to a self refresh mode; Determining whether the memory card has been removed; And instructing to cut off power of the external memory when it is determined that the memory card is removed.

The method for controlling power of the digital device may include: determining whether a predetermined time has elapsed after an instruction to cut off the SoC main power has occurred; And instructing to shut off the power of the external memory when it is determined that a predetermined time has elapsed after the instruction to shut down the SoC main power.

Hereinafter, the configuration and operation of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote components that perform the same function.

Hereinafter, the name of the power off / supply sequence of the present invention which is distinguished from the power off / supply sequence by the conventional STR technique will be referred to as “fast boot”.

In the fast boot of the present invention, the DRAM is set to the self-refresh mode when the power is cut off, and the SoC power is cut off. This is a fundamental difference from the SoC embedded processor being set to sleep mode in a conventional STR.

A power down sequence of the fast boot scheme implemented by the control circuit device for a digital device of the present invention will be described with reference to FIG. 6.

2 is a block diagram illustrating a control circuit device for a digital device according to an exemplary embodiment of the present invention, which includes an external memory 20, an SoC unit 10, a power supply unit 40, and a backup battery 30. do.

The external memory 20 can perform a self-refresh operation. The external memory 20 may be provided as a commercially available SDRAM (Synchronous Dynamic RAM) or DDR (Double Data Rate) SDRAM, and various control signals (ex: CLK, CKE, / CS, / RAS, / CAS, / WE, / RE, BA, SA, DQM) and pins for inputting and outputting data (ex: D [0: 7]) 21. In order to maintain the external SDRAM 20 in the self refresh mode, CKE (Clock Enable) must be kept at "L".

When "L" is input to the CKE input pin of the external SDRAM 20, the clock operation stops, all other inputs are ignored, and the self refresh mode is operated. In self-refresh mode, all input pins except CKE input pins are disabled. In the self-refresh mode, writing is prohibited, and upon reading, previous data is continuously latched and output.

The SoC 10 is configured to switch the internal processor 108 that is in charge of controlling each electronic component of the digital device, the memory controller 106 that sets the external memory 20 to the self-refresh mode, and the SoC main power supply 46. An SoC power control unit 100 for outputting a first control signal SoC_power_on and a second control signal ram_power_on for switching the external memory power source 44, and a bus 104 connecting them.

The embedded processor 108 sets the fast boot mode of the present invention and transmits a power off indication signal to the SoC power control unit 100 connected through the buses 104 and 101.

In the normal operation state of the SoC 10, the SoC power control unit 100 outputs both the first control signal SoC_power_on and the second control signal ram_power_on in an on state. The SoC power controller 100 switches the first control signal SoC_power_on to the off state and outputs the second control signal when the power-off instruction is input while the embedded processor 108 sets the power-down sequence to the fast boot mode. The control signal ram_power_on is kept on and output.

The memory controller 106 embedded in the SoC 10 controls the control signals of the external SDRAM 20 (ex: CLK, CKE, / CS, / RAS, / CAS, / WE, / RE, BA, SA, DQM). The external SDRAM 20 and data ex: D [0: 7] are inputted and outputted. The memory controller 106 controls the external SDRAM 20 in the self refresh mode or the normal mode through the CKE output. In the present invention, the pull-down resistor 111 is connected between the CKE terminal and the ground terminal of the external SDRAM 20 so that the CKE remains in the "L" state even after the VDD_SoC 45 is cut off and the memory controller is not operated. do.

The SoC 10 may further include a real time clock (RTC) circuit. In the present invention, the use of the RTC 110 will be described in FIG.

When the external power button 50 and the play button 51 are directly connected to the input pins of the SoC 10, the chattering circuit 112 inside the SoC 10 to remove the chattering generated from the button. It may be further provided. The chattering power button signal 113 and the play button signal 114 may be input to the onboard processor 108 or / and the SoC power control unit 110 via the bus 108. Here, the power button 50 and the play button 51 use the SoC backup power (VDD_KAU) as a power source.

In addition to the components shown in the drawing, the SoC 10 may be equipped with a digital signal processor (DSP), internal memory, embedded software, or the like, depending on the system in which the SoC 10 is to be mounted. In addition, according to system specifications, peripheral modules such as a driving circuit, a communication circuit, and a camera module of a terminal such as a display device and an audio device may be embedded.

The memory card detection unit 60 uses the first control signal SoC_power_on and the memory card insertion detection signal Card_insert as control inputs, and uses the second control signal ram_power_on of the SoC power control unit 100 as the SDRAM power supply unit 44. To pass.

The memory card detection unit 60 detects whether the memory card 70 is inserted or not (Card_insert). When the first control signal SoC_power_on is turned on, the memory card detection unit 60 generates the second control signal ram_power_on regardless of whether the memory card is inserted (Card_insert). The third control signal 61 is output as it is, and when the first control signal SoC_power_on is off and the memory card is inserted, the second control signal ram_power_on is output as the third control signal 61 as it is. When the first control signal SoC_power_on is in the off state and no memory card is inserted, the third control signal 61 in the off state is output.

These conditions are summarized in the truth table as shown in Table 1 below.

First control signal (SoC_power_on) Card_insert Second control signal (ram_power_on) Third control signal 61 (VDD_RAM on / off) One × One One 0 One One One 0 One 0 0 0 0 × 0

In the present invention, as long as the SoC_power_on signal maintains a "1" state as shown in Table 1, the ram_power_on signal maintains a "1" state.

The implementation of the truth table as shown in Table 1 in the memory card detection unit 60 is to forcibly switch to cold booting by blocking the VDD_RAM 43 when the memory card is removed after the first control signal SoC_power_on signal is turned off. to be.

When the SoC power supply VDD_SoC is cut off and the external SDRAM 20 is fast booted while operating in the self refresh mode, the system is immediately started by reading the address of the external SDRAM 20. At this time, if the memory card is removed during the self refresh operation of the external SDRAM 20, an error occurs during fast boot. In order to prevent such an error, the operation of Table 1 by the memory card detection unit 60 immediately cuts off the VDD_RAM 43 that is the power supply of the external SDRAM 20 when the memory card insertion detection signal Card_insert is "0". Force a cold boot.

An example of a circuit in which the memory card detection unit 60 is specifically implemented will be described with reference to FIG. 5.

In addition, although the memory card detection unit 60 is illustrated as being provided outside the SoC 10 in the drawing, those skilled in the art will understand that the SoC 10 may be implemented by being connected to the SoC power control unit 100.

The power supply unit 40 is the SoC main power supply unit 46 and the third control signal 61 which supply / block the main power supply VDD_SoC, 45 to the SoC according to the SoC backup power supply VDD_KAU 32 and the first control signal SoC_power_on. The external memory 20 includes an external memory power supply 44 for supplying power VDD_RAM 43 to the external memory 20.

The VDD_SoC 45 provides power for the SoC internal core and power for the IO except the SoC power control unit 100 in the SoC 10.

Here, the SoC backup power supply VDD_KAU 32 may be provided by the backup battery 30, the diode 31, and the backup power supply 42 line of the power supply 40. In the SoC 10, the SoC power control unit 100 receives power from the SoC backup power supply 32.

FIG. 3 is a block diagram illustrating a preferred embodiment of the SoC power control unit 100 inside the SoC 10 of FIG. 2 as a characteristic component for implementing a fast boot of the present invention. 206, a switching signal generator 204, a counter 200, and a decoder 202.

The SoC power control unit 100 receives power from the SoC backup power supply VDD_KAU and operates by the data D [n: 0] and the clock pcu_clk input through the buses 104 and 101 of FIG. 2. . The clock pcu_clk is used as a clock of the register logic of the counter 200, the register 206, and the switching signal generator 204, and the data D [n: 0] is input as the data of the register 206. . An input of the power button 113 (FIG. 2) or the play button (114-FIG. 2) may be input to the register 206 via a data line.

The register unit 206 may be provided with registers as illustrated in Table 2 below.

register Explanation   PCU_MINUTE Set the count value to cut off the SoC main power in the fast boot mode to cut off the RAM power after a certain period of time.   IS_FAST_BOOT "1" set if booted in fast boot mode   FAST_MODE "1" set if you always want to boot in fast boot mode only   RAM_PWR_OFF set to "1" to switch the ram_power_on signal to "L"   DSP_PWR_OFF set to "1" to switch dsp_power_on signal to "L"

In Table 2, the essential registers of the present invention are the DSP_PWR_OFF register and the RAM_PWR_OFF register.

When the DSP_POWER_OFF register is set, the switching signal generation unit 204 switches the SoC_power_on signal to the OFF state (H → L) and outputs the signal.

In addition, the switching signal generator 204 may output the SoC_power_on signal by turning off (H → L) the SoC_power_on signal according to the output of the decoder 202.

After the DSP_POWER_OFF register is set and the SoC_power_on signal turns off (H → L), the counter 200 and the decoder 202 count and output the elapsed predetermined time for turning off the RAM power set in the PCU_MINUTE register. In response, the switching signal generator 204 switches the ram_power_on signal to the off state (H → L).

The IS_FAST_BOOT register, the FAST_MODE register, and the like can be added for extended use of the present invention.

The IS_FAST_BOOT register indicates booting in fast boot mode. Set to "1" when the onboard processor is started and remain "1" unless ram_power_on is turned off. If ram_power_on turns off, it is set to "0".

In addition, as long as the FAST_MODE register is set to "1", the switching signal generation unit 204 keeps the ram_power_on signal always on (H).

FIG. 4 is a block diagram illustrating another exemplary embodiment of the SoC power control unit 100 inside the SoC 10 of FIG. 2 and uses an output clock of the RTC 110.

The RTC 110 operates as a SoC backup power supply (VDD_KAU) and operates by receiving an oscillator input of 32.768 KHz.

In the embodiment of FIG. 4, the clock divided by the RTC 110 is used as the register clock pcu_clk of the SoC power supply controller 100, and the second signal of the RTC 110 output is used as the counter 200 clock. do.

As such, by using the slow clock output from the RTC 110 instead of the system clock as the internal clock of the SoC power controller 100, power consumption of the SoC power controller 100 may be reduced.

In FIG. 4, the power button input 113 and the play button input 114 are connected to the switching signal generator 204.

In this case, in Table 2, when the IS_FAST_BOOT register is set to "1" and the DSP_PWR_OFF register is set to "1", when the power button input 113 occurs, the switching signal generator 204 switches the SoC_power_on signal to the off state. It can be implemented to (H → L).

In addition, in Table 2, when the power button input 113 or the play button input 114 occurs when the IS_FAST_BOOT register is set to "1" and the DSP_PWR_OFF register is set to "0", the switching signal generator 204 generates SoC_power_on. It may be implemented to turn the signal on (L-H).

If the power button input 113 is input while the IS_FAST_BOOT register is "0", the switching signal generator 204 may be implemented to switch the SoC_power_on signal and the ram_power_on signal to an on state (L → H).

FIG. 5 is an example of a circuit in which the memory card detector 60 of FIG. 2 is specifically implemented. The circuit of FIG. 2 described in FIG. 2 is implemented.

Referring to FIG. 5, the memory card detection unit 60 uses the first control signal SoC_power_on and the Card_insert signal as control inputs, the second control signal ram_power_on as an input, and the first buffer 63 and the second buffer. And a pull-up resistor R1 and a pull-down resistor R2.

The first buffer 63 is a tri-state buffer. The first control signal SoC_power_on is connected to an inverse enable terminal, and a memory card insertion detection result (Card_insert) is input. The output terminal is connected to a SoC backup power supply (VDD_KAU) with a pullup resistor (R1).

The second buffer 62 is a tri-state buffer in which a pulled-up output terminal of the first buffer 63 is connected to an enable terminal, a second control signal ram_power_on is connected to an input terminal, and an output terminal 61. Is connected to the ground with a pull-down resistor (R2).

FIG. 6 is a diagram illustrating a power down sequence by the fast boot technique of the present invention performed by the control circuit device for the digital device of FIG. 2, which will be described below with reference to FIG. 2.

If a power off instruction occurs in the normal operation state (S100) (S102), it is determined whether the STR boot is set (S104). The power off instruction S102 may be generated by an input of an external power button or may occur when a digital device is not used for a predetermined period of time.

If it is not set to STR boot, both SoC power and SDRAM power are cut off (S120). In this case, cold booting is performed.

If it is set to STR boot (S104), the built-in processor (108 in FIG. 2) performs a system backup (S106).

After performing the system backup, the SoC power controller 100 switches the SoC_power_on signal from H to L (S108), and sets the SDRAM to the self refresh mode (S110). Here, step S110 is performed simultaneously with or immediately after step S108.

The SoC main power supply 46 blocks the VDD_SoC output 45 in response to the input SoC_power_on signal being switched from H to L (S112).

When the power is turned off, the SoC main power supply 46 is not blocked until the VDD_SoC output 45 is actually blocked (S112) even after the SoC_power_on signal is switched from H to L (S108) due to the response speed and parasitic voltage caused by the capacitance component of the circuit. It takes a predetermined time Δt. Therefore, the internal processor 108 of the SoC 10 performs the normal operation during the power off time Δt, and the external SDRAM 20 may be set to the self refresh mode through the memory controller 106 (S110). ).

After the VDD_SoC power is cut off (S112), the SoC power controller 100 supplied with the VDD_KAU 32 power determines whether the memory card is removed after the SoC_power_on signal is switched from H to L (S108) (S114).

If an indication signal for fast-upping the SoC 10 such as a play button, a power button, or the like, such as a power button input or a play button input, occurs before a predetermined time (t _off ), only the clock is set and another initialization operation is performed. It will jump to the address of RAM where data is recorded and perform STR boot operation.

When this predetermined period t _off has elapsed, the SoC power control unit 100 switches the ram_power_on signal from H to L (S116).

The SDRAM power supply 44 blocks the VDD_RAM output 43 in response to the input ram_power_on signal being switched from H to L (S118). The subsequent boot operation is performed as a cold boot operation (S122).

FIG. 7 is another example of a power down sequence by the fast boot method of the present invention performed by the control circuit device for the digital device of FIG. 2, in which step S122 of FIG. 6 is added.

When the memory card is not removed after the VDD_SoC power is cut off (S112) (S114), the SoC power control unit 100 supplied with the VDD_KAU 32 power is predetermined after the SoC_power_on signal is switched from H to L (S108). It is determined whether the period t _off has elapsed (S124).

If an indication signal for fast-upping the SoC 10 such as a play button, a power button, or the like, such as a power button input or a play button input, occurs before a predetermined time (t _off ), only the clock is set and another initialization operation is performed. It will jump to the address of RAM where data is recorded and perform STR boot operation.

When this predetermined period t _off has elapsed, the SoC power control unit 100 switches the ram_power_on signal from H to L (S116).

The SDRAM power supply 44 blocks the VDD_RAM output 43 in response to the input ram_power_on signal being switched from H to L (S118). The subsequent boot operation is performed as a cold boot operation (S122).

8 is a block diagram illustrating an internal configuration of a digital camera as an example of a digital apparatus equipped with a control circuit device for a digital apparatus of the present invention.

The optical system OPS including the lens unit and the filter unit optically processes light from a subject. The lens unit in the optical system OPS includes a zoom lens, a focus lens, and a compensation lens.

A photoelectric conversion unit (OEC) of a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) converts light from an optical system (OPS) into an electrical analog signal. Here, the DSP 307 controls the timing circuit 302 to control the operations of the photoelectric converter OEC and the analog-digital converter 301. The CDS-ADC (Correlation Double Sampler and Analog-to-Digital Converter) element 301 as an analog-to-digital converter processes the analog signal from the photoelectric converter (OEC), removes the high frequency noise, and adjusts the amplitude. (auto gain control, AGC) and then convert to a digital signal. The DSP 307 processes the digital signal from the CDS-ADC element 301 to generate a digital image signal classified into luminance and chroma signals.

The DRAM (Dynamic Random Access Memory) 304 temporarily stores digital image signals and other temporary processing data from the DSP 307.

The EEPROM (Electrically Erasable Programmable Read Only Memory) 305 stores algorithms and setting data necessary for the operation of the DSP 307. The memory card of the user is attached to or detached from the memory card interface 306.

The digital image signal from the DSP (Digital Signal Processor) 307 is converted into the display signal of the LCD panel by the LCD driver 314 so that the image is displayed on the color LCD panel 317.

On the other hand, the digital image signal from the DSP 307 can be transmitted by serial communication via a universal serial bus (USB) connection 318 or an RS232C interface 308 and its connection 319, and the video filter 309 And a video signal through the video output unit 320.

The audio processor 313 outputs the audio signal from the microphone MIC to the DSP 307 or the speaker SP, and outputs the audio signal from the DSP 307 to the speaker SP.

The user input unit INP may include a shutter button, a mode selection button, a function selection button, a zoom button, a direction movement button, and the like. The user input unit INP is operated by the user to generate a command for performing each function according to the user's instruction.

The microcontroller 312 controls the lens driver 310, whereby the zoom motor M _Z , the focus motor M _F , and the aperture motor M _A are zoom lenses in the optical system OPS, The focus lens and the aperture are driven respectively. The light emitting unit LAMP driven by the microcontroller 312 may include a self-timer lamp, an auto-focus lamp, a strobe standby lamp, and the like. On the other hand, the microcontroller 312 drives the strobe 315 by controlling the operation of the strobe controller 311 according to the signal from the strobe-light sensor 316.

The function of the microcontroller 312 may be implemented in one chip with the DSP 307.

Among the components shown in FIG. 8, the CDS-ADC 301, the timing circuit 302, the RTC 303, the DSP 307, the EEPROM 305, the audio processor 313, the LCD driver 314, the microcomputer. Electronic components such as controller 312 may all be contained in a single SoC.

In this case, the microcontroller 312 corresponds to the embedded processor 108 of FIG. 2. If the DRAM 304 uses an SDRAM capable of setting a self-refresh mode, additionally includes the SoC power control unit 100 of FIG. 2 inside the SoC, and operates the SoC according to the flows of FIGS. 6 and 7, The digital camera system to which the control circuit device for a digital device is applied is completed.

The best embodiments have been disclosed in the drawings and specification above. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the control circuit device for a digital device of the present invention provides an SoC that can use the STR technique that can reduce leakage current without using an external processor. According to the present invention, when the memory card is removed in the self-refresh mode of the external memory, the external memory is forcibly cut off to switch to a cold boot state, thereby preventing a boot error due to the removal of the memory card in the self-refresh mode.

The invention is not limited to the examples described above and represented in the drawings. Those skilled in the art taught by the above-described embodiments, many modifications to the above-described embodiments are possible by substitution, erasure, merging, etc. within the scope and object of the present invention described in the following claims.

Claims (6)

An external memory capable of self-less operation; An internal processor that controls each electronic component of a digital device, a memory controller for setting the external memory to the self-refresh mode, a first control signal SoC_power_on for switching the SoC main power, and a second control for switching the external memory power A SoC unit having a SoC power control unit for outputting a signal ram_power_on; Detects whether a memory card is inserted and outputs the second control signal as a third control signal as it is, regardless of whether the memory card is inserted when the first control signal is on, and the first control signal is off and the memory card Outputs the second control signal as the third control signal as it is, and outputs the third control signal in the off state when the first control signal is off and the memory card is not inserted. A memory card detector; A SoC backup power unit (VDD_KAU) connected to a backup battery for supplying power to the SoC power control unit, an SoC main power unit for supplying / blocking the main power (VDD_SoC) to the SoC according to the first control signal, and the third control signal. A power supply unit including an external memory power supply unit supplying / blocking power of the external memory; And An operation button for receiving power from the backup power supply and generating a power supply / blocking indication signal, The SoC power control unit outputs the first control signal by turning off the first control signal when the power-off instruction is input while the embedded processor sets the power-off sequence to the fast boot mode. A control circuit device for a digital device, characterized by maintaining an on state. The memory card detector of claim 1, wherein the memory card detection unit comprises: A tri-state buffer, wherein the first control signal is connected to an inverse enable terminal, the detection result of the memory card insertion is connected to an input terminal, and the output terminal is the SoC backup power supply. A first buffer connected to the pull-up resistor to the first buffer; And As a three-state buffer, the output terminal of the first buffer is connected to the enable terminal, the second control signal is connected to the input terminal, the output terminal has a second buffer connected to the ground by a pull-down resistor, And the third control signal is output through the output terminal of the second buffer. The method of claim 1, wherein the SoC power control unit, And a timer circuit for checking a lapse of a predetermined time after switching the first control signal to an off state. The method of claim 3, The SoC unit further includes a real time clock (RTC) that is powered from the SoC backup power supply, The clock used in the SoC power control unit is a control circuit device for a digital device, characterized in that provided in the RTC. In order to implement a control sequence of power off / supply in a digital device having the control circuit device of any one of claims 1 to 4, Determining whether a fast boot mode is set when a power off instruction is input; Instructing to turn off the SoC power supply and the external memory power when the fast boot mode is not set; Performing a system backup when set to a fat boot mode; Instructing to shut down the SoC main power; Setting the external memory to the self refresh mode; Performing a suspend to RAM (STR) boot process when a power supply instruction is input while the external memory is set to a self refresh mode; Determining whether the memory card has been removed; And And instructing to cut off power of the external memory when it is determined that the memory card has been removed. The method of claim 5, Determining whether a predetermined time has elapsed after an instruction to shut down the SoC main power has occurred; And And instructing to cut off power of the external memory if it is determined that a predetermined time has elapsed after the SoC main power cutoff instruction occurs.

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