KR20070068142A - Formation method of surface passivation and etching method using the same - Google Patents

Formation method of surface passivation and etching method using the same Download PDF

Info

Publication number
KR20070068142A
KR20070068142A KR1020050129914A KR20050129914A KR20070068142A KR 20070068142 A KR20070068142 A KR 20070068142A KR 1020050129914 A KR1020050129914 A KR 1020050129914A KR 20050129914 A KR20050129914 A KR 20050129914A KR 20070068142 A KR20070068142 A KR 20070068142A
Authority
KR
South Korea
Prior art keywords
coating
polymer
etching
pdms
protective layer
Prior art date
Application number
KR1020050129914A
Other languages
Korean (ko)
Other versions
KR101147374B1 (en
Inventor
이경일
김광일
Original Assignee
재단법인 포항산업과학연구원
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 재단법인 포항산업과학연구원 filed Critical 재단법인 포항산업과학연구원
Priority to KR1020050129914A priority Critical patent/KR101147374B1/en
Publication of KR20070068142A publication Critical patent/KR20070068142A/en
Application granted granted Critical
Publication of KR101147374B1 publication Critical patent/KR101147374B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052—Wet cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

A method for forming a surface passivation layer is provided to protect an interconnection in a TMAH(tetra-methyl ammonium hydroxide) etching process by forming a surface passivation layer on a polymer layer by PDMS(poly dimethylsiloxane). A process for forming a surface passivation layer(300) for protecting an interconnection is composed of a pre-coating process for coating polymer and a main-coating process for coating PDMS. The pre-coating process includes a first baking step of silicon, a polymer spin-coating step, a leaving step in a flat place, a second baking step and a third baking step. The main-coating process includes an O2 plasma step performed on a polymer surface of polymer-coated silicon, a PDMS coating step and a fourth baking step. The pre-coating step is repeated twice. In the main-coating process, the O2 plasma step can be performed for a time interval of four minutes and thirty seconds to five minutes.

Description

표면보호층 형성방법 및 이를 이용한 에칭방법{Formation method of surface passivation and etching method using the same}Forming method of surface protection layer and etching method using same {Formation method of surface passivation and etching method using the same}

도 1은, 본 발명에 의하여 형성되는 표면보호층을 이용한 디바이스 제작 공정 예시도.1 is an illustration of a device fabrication process using the surface protective layer formed by the present invention.

도 2는, 디바이스 제작 후의 배선의 전자현미경 사진으로서, (a)는 종래기술과 같이 폴리머에 의하여 보호된 배선의 사진, (b)는 본 발명과 같이 폴리머 및 PDMS에 의하여 보호된 배선의 사진.Fig. 2 is an electron micrograph of wiring after device fabrication, (a) is a photograph of wiring protected by a polymer as in the prior art, and (b) is a photograph of wiring protected by a polymer and a PDMS as in the present invention.

도 3은, 본 발명에 의한 보호층 형성방법의 플로챠트.3 is a flowchart of a method for forming a protective layer according to the present invention.

도 4는, 본 발명에 의한 에칭방법의 플로챠트.4 is a flowchart of an etching method according to the present invention.

도 5는, 프리코팅(pre-coating) 단계에 대한 상세 플로챠트.5 is a detailed flowchart of the pre-coating step.

도 6은, 메인코팅(main coating) 단계에 대한 상세 플로챠트.6 is a detailed flowchart of the main coating step.

도 7은, 린스(rinse) 단계에 대한 상세 플로챠트.7 is a detailed flowchart of the rinse step.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

100 : 배선층100: wiring layer

200 : 폴리머층200: polymer layer

300 : 표면보호층300: surface protective layer

본 발명은, 표면보호층 형성방법 및 이를 이용한 에칭방법에 관한 것으로서, 더욱 상세히는, 폴리머층의 위에 PDMS에 의한 표면보호층을 형성하며, 이 표면보호층에 의하여 TMAH 에칭시에 배선을 보호할 수 있는 에칭방법에 관한 것이다.The present invention relates to a method for forming a surface protective layer and an etching method using the same, and more particularly, to form a surface protective layer by PDMS on a polymer layer, and to protect wiring during TMAH etching by the surface protective layer. It relates to an etching method that can be.

일반적으로, 반도체를 비롯한 각종 디바이스의 구조물 형성을 위하여, 배선이 형성되는 표면의 반대면, 즉 디바이스 이면에 대하여, TMAH(Tetra-methyl ammonium hydroxide)를 이용한 에칭(Etching)을 행하게 되는 경우가 있다. 이러한 공정은, MEMS(Micro Electric Mechanical systems) 디바이스나 NEMS(Nano Electric Mechanical systems) 디바이스를 제작함에 있어서도 널리 이용되고 있다. 이때, TMAH에 반응하는 모든 종류의 배선, 즉 알루미늄 등의 소재로 이루어지는 배선 등을 보호하는 조치를 취할 필요가 있다.In general, in order to form structures of various devices including semiconductors, etching may be performed using tetra-methyl ammonium hydroxide (TMAH) on the opposite surface of the surface on which the wiring is formed, that is, the back surface of the device. Such a process is also widely used in manufacturing MEMS (Micro Electric Mechanical systems) devices and NEMS (Nano Electric Mechanical systems) devices. At this time, it is necessary to take measures to protect all kinds of wirings that react to TMAH, that is, wirings made of materials such as aluminum.

종래에는, 디바이스 이면의 가공을 위한 TMAH를 이용한 벌크 실리콘의 에칭시에, 배선보호(Passivation)를 위해서 폴리머(Polymer)로 코팅을 하거나, 각종 지그를 이용하여 TMAH가 침투하지 않도록 하는 방법을 이용하고 있다.Conventionally, during the etching of bulk silicon using TMAH for processing the back side of the device, a method of coating with polymer for wiring protection or using various jigs to prevent penetration of TMAH is used. have.

그런데, 폴리머를 이용할 경우에는, 이 폴리머가 디바이스를 100% 보호하지 못하여 TMAH가 침투되어, 결국 칩의 수율(Yield)이 100%가 되지 못하고 있는 것이 현 실정이다.By the way, when the polymer is used, the polymer does not protect the device 100% and TMAH penetrates, and thus the yield of the chip is not 100%.

또한, 각종 지그를 이용하게 되면, 공정의 불편함은 물론, 시간상 많은 제약을 받으며, 역시 TMAH의 누수가 있을 경우는, 칩의 전체가 불량이 되어 버리는 문 제가 있었다. In addition, when various jigs are used, the process is inconvenient, as well as a lot of time constraints, and if there is a leak of TMAH, there is a problem that the entire chip becomes defective.

본 발명은, 상기한 바와 같은 종래기술의 문제점을 해결하기 위하여 안출된 것으로서, 폴리머층의 위에 이 폴리머층의 결함을 보완시키는 층을 형성시켜서, 배선의 보호 정도를 향상시켜서 수율을 향상시키는 기술을 제공하고자 하는 것이다.SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and provides a technique for forming a layer on the polymer layer to compensate for the defects of the polymer layer, thereby improving the degree of protection of the wiring and improving the yield. It is to provide.

또한, 간단한 공정만으로도 배선 보호를 효율적으로 행할 뿐만 아니라, TMAH 에칭 후에 간단하게 이 보호층을 제거할 수 있는 기술을 제공하고자 하는 것이다.In addition, it is intended to provide a technique that not only effectively protects wiring through a simple process but also can easily remove the protective layer after TMAH etching.

또한, 각종 디바이스나 칩의 제작에 있어서, 생산성을 향상시키고, 공정시간을 단축시키는 기술을 제공하고자 하는 것이다.In addition, in the manufacture of various devices and chips, it is intended to provide a technique for improving productivity and shortening the process time.

상기한 바와 같은 기술적 과제를 달성하기 위한, 본 발명에 따른 표면보호층 형성방법은, TMAH 에칭시에 배선보호를 위한 표면보호층을 형성하는 방법으로서, 폴리머를 코팅하는 프리코팅 단계와 PDMS를 코팅하는 메인코팅 단계로 이루어지고, 상기 프리코팅 단계는, 벌크실리콘에 대한 제1 베이킹 단계와, 폴리머의 스핀코팅 단계와, 평탄한 곳에서의 방치 단계와, 제2 베이킹 단계와, 제3 베이킹 단계로 이루어지고, 상기 메인코팅 단계는, 폴리머가 코팅된 실리콘의 폴리머 면에 대한 O2 플라즈마 단계와, PDMS 코팅 단계와, 제4 베이킹 단계로 이루어지며, 상기 프리코팅 단계는 2회 반복되도록 구성됨을 특징으로 한다.In order to achieve the above technical problem, the method for forming a surface protection layer according to the present invention is a method of forming a surface protection layer for wiring protection during TMAH etching, the pre-coating step of coating the polymer and coating PDMS It consists of a main coating step, wherein the pre-coating step, the first baking step for the bulk silicon, the spin coating step of the polymer, the standing in a flat place, the second baking step, the third baking step Wherein the main coating step comprises an O 2 plasma step on the polymer side of the polymer-coated silicon, a PDMS coating step, and a fourth baking step, wherein the pre-coating step is configured to be repeated twice. It is done.

여기서, 상기 메인코팅 단계에 있어서의 O2 플라즈마는 4분 30초 내지 5분간 실시됨이 바람직하다.Here, the O 2 plasma in the main coating step is preferably performed for 4 minutes 30 seconds to 5 minutes.

한편, 본 발명에 의한 표면보호층을 이용한 에칭방법은, TMAH 에칭시에 배선보호를 위한 표면보호층을 형성하고, 이를 이용하여 TMAH 에칭을 행하는 방법으로서, 제1항에 기재된 방법에 의하여 폴리머를 코팅하는 프리코팅 단계와 PDMS를 코팅하는 메인코팅 단계를 행한 후, TMAH 에칭을 행하는 에칭 단계와, 상기 에칭액 및 보호층의 제거를 행하는 린스 단계로 이루어지며, 상기 린스 단계는, 린스액에서의 오버플로우 단계와, KSR1에 의한 PDMS의 제거 단계와, IPA에 의한 세정 단계와, 폴리머 제거를 위한 O2 플라즈마 단계로 구성됨을 특징으로 한다.On the other hand, the etching method using the surface protection layer according to the present invention is a method of forming a surface protection layer for wiring protection at the time of TMAH etching, and performing TMAH etching using the same. After performing the pre-coating step of coating and the main coating step of coating PDMS, the etching step of TMAH etching and the rinsing step of removing the etching liquid and the protective layer are performed. And a flow step, a removal step of PDMS by KSR1, a cleaning step by IPA, and an O 2 plasma step for polymer removal.

여기서, 상기 KSR1은, Xylene계 용액임이 바람직하다.Here, the KSR1 is preferably a Xylene-based solution.

[실시예]EXAMPLE

이하, 첨부된 도면을 참조하여, 본 발명에 따른 표면보호층 형성방법 및 이를 이용한 에칭방법에 관한 바람직한 실시예에 대하여, 보다 상세히 설명한다. 여기서, 구체적으로 예시되는 수치는, 2인치 실리콘에 대하여 본 발명을 적용하는 경우의 수치이며, 본 발명은 이 수치에 의하여 한정되는 것은 아니다.Hereinafter, with reference to the accompanying drawings, a preferred embodiment of a method for forming a surface protective layer and an etching method using the same according to the present invention will be described in more detail. Here, the numerical value specifically illustrated is a numerical value at the time of applying this invention with respect to 2 inch silicon, and this invention is not limited by this numerical value.

도 1은, 본 발명에 의하여 형성되는 표면보호층을 이용한 디바이스 제작 공정 예시도이다. 그리고, 도 3은, 본 발명에 의한 보호층 형성방법의 플로챠트이고, 도 4는, 본 발명에 의한 에칭방법의 플로챠트이다.1 is a diagram illustrating a device fabrication process using the surface protective layer formed by the present invention. 3 is a flowchart of the protective layer forming method according to the present invention, and FIG. 4 is a flowchart of the etching method according to the present invention.

<보호층의 형성><Formation of protective layer>

도 3에 의하면, TMAH 에칭에 견딜 수 있는 보호층은 프리코팅 단계(10)와 메인코팅 단계(20)에 의하여 수행된다. 상기 프리코팅 단계(10)는, 바람직하게는 2회 연속 수행된다. 이하, 분설한다.According to FIG. 3, a protective layer capable of withstanding TMAH etching is performed by a precoating step 10 and a maincoating step 20. The precoating step 10 is preferably performed twice in succession. Hereinafter, powdering is performed.

도 5는, 프리코팅(pre-coating) 단계(10)에 대한 상세 플로챠트이고, 도 6은, 메인코팅(main coating) 단계(20)에 대한 상세 플로챠트이다.FIG. 5 is a detailed flowchart of the pre-coating step 10, and FIG. 6 is a detailed flowchart of the main coating step 20. As shown in FIG.

프리코팅 단계(10)는, 알루미늄 등 TMAH에 반응하는 소재로 이루어진 배선층(100)이 형성되어 있는 디바이스(도 1의 (a)) 표면 상의 배선보호(Passivation)를 위해서, 배선층(100)이 형성되어 있는 면, 즉 표면(도 1의 상면)에 폴리머로 코팅된 폴리머층(200)(도 1의 (b))을 형성하는 단계이다. 이는 제1 베이킹(11), 스핀코팅(12), 방치(13), 제2 베이킹(14), 제3 베이킹(15)의 단계를 거친다.In the precoating step 10, the wiring layer 100 is formed for passivation on the surface of the device (FIG. 1A) on which the wiring layer 100 made of a material reacting with TMAH, such as aluminum, is formed. It is a step of forming a polymer layer 200 (FIG. 1B) coated with a polymer on a surface, that is, a surface (top surface of FIG. 1). This is a step of the first baking 11, spin coating 12, left 13, the second baking 14, the third baking (15).

먼저, 디바이스에 대하여 제1 베이킹 단계(11)를 행한다. 이는 2인치 실리콘의 경우에, 바람직하게는 200℃에서 5분간 행한다. 이에 의하여 폴리머와의 밀착도가 최대가 된다.First, a first baking step 11 is performed on the device. This is done for 2 minutes of silicon, preferably at 200 ° C. for 5 minutes. Thereby, adhesiveness with a polymer becomes the maximum.

다음으로, 스핀코팅 단계(12)를 행한다. 폴리머의 스핀코팅 조건은 2인치 실리콘의 경우에, 1st 2000 rpm 0초, 2nd 2000 rpm 15초를 행한다. 이 스핀코팅 단계는, 폴리머의 코팅 품질을 결정하는 단계이다.Next, the spin coating step 12 is performed. Spin coating conditions of the polymer are 1st 2000 rpm 0 seconds and 2nd 2000 rpm 15 seconds in the case of 2 inch silicon. This spin coating step is to determine the coating quality of the polymer.

다음으로, 방치 단계(13)를 행한다. 방치는 평탕한 곳에서 예컨대 10분간 행한다. 이로써, 기판의 가장자리 부분까지 폴리머의 평탄도가 일정해진다.Next, the leaving step 13 is performed. Neglect is performed in a flat place, for example, for 10 minutes. As a result, the flatness of the polymer becomes constant up to the edge of the substrate.

다음으로, 제2 베이킹 단계(14)를 행한다. 이는 바람직하게는 2인치 실리콘의 경우에, 50℃에서 30분간 행한다. 이에 의하여 2차 폴리머 코팅층과의 밀착도가 강하게 나타난다.Next, a second baking step 14 is performed. This is preferably done at 50 ° C. for 30 minutes in the case of 2 inch silicon. As a result, the adhesion with the secondary polymer coating layer is strongly shown.

다음으로, 제3 베이킹 단계(15)를 행한다. 바람직하게는 2인치 실리콘의 경우에, 200℃에서 60분간 행한다. 상술한 바와 같이, 상기 프리코팅 단계(10)는, 2회 반복됨이 바람직하다. 이는 폴리머층이 유효한 두께를 가지기 위한 중요한 단계이다. Next, a third baking step 15 is performed. Preferably in the case of 2 inch silicon, it is performed at 200 ° C. for 60 minutes. As described above, the precoating step 10 is preferably repeated twice. This is an important step for the polymer layer to have an effective thickness.

이에 의하여 상기 프리코팅 단계(10)가 종료되며, 이로써 디바이스의 표면에는 강건한 폴리머층(200)이 형성된다.This ends the precoating step 10, thereby forming a robust polymer layer 200 on the surface of the device.

그 다음으로, 메인코팅 단계(20)를 행한다. 이 메인코팅 단계(20)는 상기 폴리머층(200) 위에 PDMS로 이루어지는 보호층(300)(도 1의 (b), (c))을 형성시키기 위한 단계이다. 이 메인코팅 단계(20)는, O2 플라즈마(21), PDMS코팅(22), 제4 베이킹(23) 단계를 수행하여 이루어진다.Next, the main coating step 20 is performed. This main coating step 20 is a step for forming a protective layer 300 (Fig. 1 (b), (c)) made of PDMS on the polymer layer 200. The main coating step 20 is performed by performing an O 2 plasma 21, a PDMS coating 22, and a fourth baking 23 step.

먼저, O2 플라즈마(21)를 행한다. 이는 예열된 폴리머층(200)과 PDMS로 이루어지는 보호층(300) 사이의 접착력을 높이기 위하여 행하는 중요한 공정이다. 이 단계는 실리콘의 크기에 상관없이, 4분 30초 내지 5분간, 바람직하게는 5분간 행한다. 4분 30초 이하로 행하는 경우에는, 폴리머층(200)이 너무 매끄러운 상태라서, 보호층(300)과의 접착이 곤란하고, 5분 이상으로 행하는 경우에는, 폴리머층(200)이 너무 식각되어 손상될 우려가 있다.First, the O 2 plasma 21 is performed. This is an important process performed to increase the adhesion between the preheated polymer layer 200 and the protective layer 300 made of PDMS. This step is carried out for 4 minutes 30 seconds to 5 minutes, preferably 5 minutes, regardless of the size of the silicon. When it is performed for 4 minutes and 30 seconds or less, since the polymer layer 200 is too smooth, adhesion with the protective layer 300 is difficult, and when it is performed for 5 minutes or more, the polymer layer 200 is too etched. It may be damaged.

다음으로, PDMS코팅(22)을 행한다. PDMS의 스핀코팅 조건은, 2인치 실리콘의 경우에, 1st 1500 rpm 5초, 2nd 3500 rpm 20초이며, 이로써 최대의 막두께와 평탄도를 얻을 수 있다.Next, PDMS coating 22 is performed. Spin coating conditions of PDMS are 1st 1500 rpm 5 seconds and 2nd 3500 rpm 20 seconds in the case of 2 inch silicon, thereby obtaining the maximum film thickness and flatness.

다음으로, 제4 베이킹 단계(23)를 행한다. 이는 바람직하게는 2인치 실리콘의 경우에, 150℃에서 30분간 행한다. 이로써 PDMS코팅이 폴리머층(300) 위에 강건히 형성되어 건조 고착된다.Next, a fourth baking step 23 is performed. This is preferably done at 150 ° C. for 30 minutes in the case of 2 inch silicon. As a result, the PDMS coating is firmly formed on the polymer layer 300 and dried.

상기와 같이 형성된 PDMS코팅은, TMAH 에칭액에 수밀하게 대항할 수 있는 표면보호층(300)이 된다. 이제, 상기와 같이 보호층(300)이 형성된 디바이스에 대하여 TMAH 에칭을 실시하더라도, 배선에 에칭액이 접촉되지 않으므로, 불량률이 극히 저감된다.The PDMS coating formed as described above becomes the surface protective layer 300 that can be tightly opposed to the TMAH etching solution. Now, even when TMAH etching is performed on the device on which the protective layer 300 is formed as described above, since the etching liquid does not contact the wiring, the defective rate is extremely reduced.

<에칭과 에칭 후의 처리><Process after etching and etching>

상기와 같은 폴리머층(200) 및 보호층(300)의 형성 후에는, TMAH 에칭을 실시할 수 있다.After the formation of the polymer layer 200 and the protective layer 300 as described above, TMAH etching can be performed.

도 4는, 본 발명에 의한 에칭방법의 플로챠트이고, 도 7은, 린스(rinse) 단계에 대한 상세 플로챠트이다.4 is a flowchart of the etching method according to the present invention, and FIG. 7 is a detailed flowchart of the rinse step.

상기 에칭방법은, 상기 보호막 형성방법에서 수행되는 프리코팅 단계(10)와 메인코팅 단계(20)의 이후에 이루어지는 것으로서, 에칭 단계(30)와, 린스 단계(40)를 포함하여 이루어진다.The etching method is performed after the precoating step 10 and the main coating step 20 performed in the protective film forming method, and includes an etching step 30 and a rinsing step 40.

상기 에칭 단계(30)는, TMAH로 에칭을 실시하는 단계이다.The etching step 30 is a step of etching with TMAH.

상기 린스 단계(40)는, 상기 에칭액과 보호층, 폴리머층을 제거하는 단계로 서, 도 7에 나타낸 바와 같이, 린스 오버플로우(overflow)(41), KSR1(42), IPA(43), O2 플라즈마(44) 단계로 이루어진다.The rinse step 40 is a step of removing the etching solution, the protective layer, and the polymer layer, as shown in FIG. 7, the rinse overflow 41, the KSR1 42, the IPA 43, O 2 plasma 44 is made up of steps.

상기 린스 오버플로우 단계(41)는, 바람직하게는 20분간 행하여진다.The rinse overflow step 41 is preferably performed for 20 minutes.

상기 KSR1 단계(42)는, 예컨대 Xylene계 용액으로 2인치 실리콘의 경우에, 50℃에서 2분간 행함이 바람직하다.The KSR1 step 42 is preferably performed at 50 ° C. for 2 minutes, for example, in the case of 2 inch silicon as an Xylene-based solution.

이로써, 보호층(300) 제거 공정이 마무리된다.As a result, the process of removing the protective layer 300 is completed.

상기 IPA(이소프로필 알콜; isopropyl alcohol) 단계(43)는, Xylene계의 용액을 세정하는 단계로서, 2인치 실리콘의 경우에, 1분간씩 2회 행함이 바람직하다.The IPA (isopropyl alcohol) step 43 is a step of washing the Xylene-based solution. In the case of 2-inch silicon, the IPA (isopropyl alcohol) step 43 is preferably performed twice for 1 minute.

상기 O2 플라즈마 단계(44)는, 바람직하게는 2인치 실리콘의 경우에, 5분간 실시한다.The O 2 plasma step 44 is carried out for 5 minutes, preferably in the case of 2 inch silicon.

이로써, 폴리머층(200) 제거 공정이 마무리된다.As a result, the polymer layer 200 removing process is completed.

<비교 사진><Comparative photo>

도 2는, 디바이스 제작 후의 배선의 전자현미경 사진으로서, (a)는 종래기술과 같이 폴리머에 의하여 보호된 배선의 사진, (b)는 본 발명과 같이 폴리머 및 PDMS에 의하여 보호된 배선의 사진이다.Fig. 2 is an electron micrograph of wiring after device fabrication, (a) is a photo of wiring protected by polymer as in the prior art, and (b) is a photo of wiring protected by polymer and PDMS as in the present invention. .

(a) 및 (b)의 사진의 비교에 의하여, 종래기술에 의한 폴리머만을 이용한 방식의 경우에는, 배선에 결함이 발생하여 있다는 것을 알 수 있으며, 이와 대비하 여, 본 발명에 따른 폴리머와 PDMS를 이용한 방식의 경우는, 배선에 있어서 전체는 물론, 제일 취약한 가장자리 부분까지도 극히 깨끗하게 보존되어 있다는 것을 알 수 있다.By comparing the photographs of (a) and (b), it can be seen that in the case of using the polymer according to the prior art, a defect occurs in the wiring. In contrast, the polymer according to the present invention and the PDMS In the case of using the method, it can be seen that not only the whole but also the most fragile edge portion of the wiring is kept extremely clean.

상기와 같은 구성을 가지는 본 발명에 의하면, 폴리머층의 위에 이 폴리머층의 결함을 보완시키는 층을 형성시켜서, 배선의 보호 정도를 향상시켜서 수율을 향상시키는 효과가 있다.According to the present invention having the above-described configuration, there is an effect of forming a layer that compensates for the defect of the polymer layer on the polymer layer, improving the degree of protection of the wiring, and improving the yield.

또한, 간단한 공정만으로도 배선 보호를 효율적으로 행할 뿐만 아니라, TMAH 에칭 후에 간단하게 이 보호층을 제거할 수 있는 효과가 있다.In addition, the wiring protection can be efficiently performed only by a simple process, and the protective layer can be easily removed after TMAH etching.

또한, 각종 디바이스나 칩의 제작에 있어서, 생산성을 향상시키고, 공정시간을 단축시키는 효과가 있다.In addition, in the production of various devices and chips, there is an effect of improving the productivity and shortening the process time.

Claims (4)

TMAH 에칭시에 배선보호를 위한 표면보호층을 형성하는 방법으로서, A method of forming a surface protective layer for wiring protection during TMAH etching, 폴리머를 코팅하는 프리코팅 단계와 PDMS를 코팅하는 메인코팅 단계로 이루어지고, It consists of a precoating step of coating the polymer and a main coating step of coating the PDMS, 상기 프리코팅 단계는, The precoating step, 실리콘에 대한 제1 베이킹 단계와, 폴리머의 스핀코팅 단계와, 평탄한 곳에서의 방치 단계와, 제2 베이킹 단계, 제3 베이킹 단계로 이루어지고, A first baking step for silicon, a spin coating step of the polymer, a standing step on a flat surface, a second baking step, a third baking step, 상기 메인코팅 단계는, The main coating step, 폴리머가 코팅된 실리콘의 폴리머 면에 대한 O2 플라즈마 단계와, PDMS 코팅 단계와, 제4 베이킹 단계로 이루어지며, An O 2 plasma step on the polymer side of the polymer coated silicon, a PDMS coating step, and a fourth baking step, 상기 프리코팅 단계는 2회 반복되도록 구성됨을 특징으로 하는, 표면보호층 형성방법.The pre-coating step is characterized in that it is configured to be repeated twice, the surface protective layer forming method. 제1항에 있어서, The method of claim 1, 상기 메인코팅 단계에 있어서의 O2 플라즈마는, 4분 30초 내지 5분간 실시됨을 특징으로 하는, 표면보호층 형성방법.The O 2 plasma in the main coating step, characterized in that performed for 4 minutes 30 seconds to 5 minutes, the surface protective layer forming method. TMAH 에칭시에 배선보호를 위한 표면보호층을 형성하고, 이를 이용하여 TMAH 에칭을 행하는 방법으로서, As a method of forming a surface protection layer for wiring protection at the time of TMAH etching, and performing TMAH etching using this, 제1항에 기재된 방법에 의하여 폴리머를 코팅하는 프리코팅 단계와 PDMS를 코팅하는 메인코팅 단계를 행한 후, TMAH 에칭을 행하는 에칭 단계와, 상기 에칭액 및 보호층의 제거를 행하는 린스 단계로 이루어지며, After the precoating step of coating the polymer and the main coating step of coating the PDMS by the method of claim 1, the etching step of performing TMAH etching, and the rinsing step of removing the etching solution and the protective layer, 상기 린스 단계는, The rinse step, 린스액에서의 오버플로우 단계와, KSR1에 의한 PDMS 제거 단계와, IPA에 의한 세정 단계와, 폴리머 제거를 위한 O2 플라즈마 단계로 구성됨을 특징으로 하는, 표면보호층을 이용한 에칭방법.An overflow method in a rinse liquid, a PDMS removal step by KSR1, a cleaning step by IPA, and an O 2 plasma step for polymer removal. 제3항에 있어서, The method of claim 3, 상기 KSR1은, Xylene계 용액임을 특징으로 하는, 특징으로 하는, 표면보호층을 이용한 에칭방법.The KSR1 is characterized in that the xylene-based solution, characterized in that, etching method using a surface protective layer.
KR1020050129914A 2005-12-26 2005-12-26 Formation method of surface passivation and etching method using the same KR101147374B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020050129914A KR101147374B1 (en) 2005-12-26 2005-12-26 Formation method of surface passivation and etching method using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020050129914A KR101147374B1 (en) 2005-12-26 2005-12-26 Formation method of surface passivation and etching method using the same

Publications (2)

Publication Number Publication Date
KR20070068142A true KR20070068142A (en) 2007-06-29
KR101147374B1 KR101147374B1 (en) 2012-05-23

Family

ID=38366634

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020050129914A KR101147374B1 (en) 2005-12-26 2005-12-26 Formation method of surface passivation and etching method using the same

Country Status (1)

Country Link
KR (1) KR101147374B1 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001053041A (en) * 1999-08-11 2001-02-23 Nippon Sheet Glass Co Ltd Method of protecting front surface and holding semiconductor wafer during processing of rear surface thereof
KR20040012009A (en) * 2002-07-31 2004-02-11 주식회사 디지탈바이오테크놀러지 Method for manufacturing a microchip

Also Published As

Publication number Publication date
KR101147374B1 (en) 2012-05-23

Similar Documents

Publication Publication Date Title
US10879212B2 (en) Processed stacked dies
US6245677B1 (en) Backside chemical etching and polishing
WO2009032536A3 (en) Method for manufacturing a semiconductor die and a semiconductor device comprising the semiconductor die obtained thereby
US8425713B2 (en) Bonding apparatus, method for preventing dissolving of adhesive agent, and bonding method
JP2007335659A (en) Method of manufacturing semiconductor device
JP5016321B2 (en) Support plate processing method
KR100558164B1 (en) Etchant for etching nitride and method for removing nitride film of semiconductor device using the same
KR101147374B1 (en) Formation method of surface passivation and etching method using the same
KR100722128B1 (en) Fabricating method of semiconductor device
KR20070074398A (en) Semiconductor wafer including contamination removal part
KR20110036990A (en) Method of growing uniform oxide layer and method of cleaning substrate
KR100902586B1 (en) Method for removing poly silicon
US7288465B2 (en) Semiconductor wafer front side protection
JP4958287B2 (en) Peeling method in peeling device
KR100729117B1 (en) Method for manufacturing the metal line of digital light processing device
JP5332120B2 (en) Manufacturing method of semiconductor device
JP2019142209A (en) Film forming method of baseboard and manufacturing method of liquid discharge head
JPH05109702A (en) Manufacture of semiconductor device
JP2005311342A5 (en)
KR100604541B1 (en) Method for manufacturing the via hole of digital light processing device
KR100269291B1 (en) Method for rinsing wafer
JP5285793B2 (en) Support plate processing method
KR100779399B1 (en) Method for fabricating a semiconductor device
KR100620163B1 (en) Method for backgrinding a semiconductor
WO2001022476A2 (en) Backside chemical etching and polishing

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20150507

Year of fee payment: 4

FPAY Annual fee payment

Payment date: 20160404

Year of fee payment: 5

FPAY Annual fee payment

Payment date: 20170410

Year of fee payment: 6

FPAY Annual fee payment

Payment date: 20180425

Year of fee payment: 7