KR20070067306A - Remote field programmable gate array programming apparatus and the method thereof - Google Patents

Abstract

A device and a method for programming an FPGA by using IPC are provided to enable a remote board to program the FPGA with FPGA programming data excluding IPC information by transmitting the FPGA programming data including IPC ID information to the remote board through the IPC. A data processor(110) extracts source data to be output to a processor(120) from user data received from the outside by using an ID and outputs the source data to the processor. The processor receives and stores the source data to a flash memory(140), and outputs an FPGA programming command to an FPGA programming controller(130). The FPGA programming controller reads the FPGA programming data from the source data stored in the flash memory after receiving the FPGA programming command and programs the FPGA(111) of the data processor. The flash memory stores the source data received from the processor part. The data processor and the processor perform communication through an IPC protocol.

Description

FPC programming device using IPC and its method {Remote field programmable gate array programming apparatus and the method}

1 is a block diagram of a prior art Field Programmable Gate Array (FPGA) programming device,

Figure 2 is a block diagram of a remote FFP programming device of the present invention,

FIG. 3 is a block diagram of an FFP programming controller of FIG. 2.

4 is a diagram illustrating a data storage area of a flash memory unit of FIG. 2;

FIG. 5 is a flowchart illustrating a process of a remote field programmable gate array (FPGA) programming method of the present invention.

6 is a schematic block diagram of a W-CDMA user traffic processing apparatus according to an embodiment to which the present invention is applied.

Description of the main symbols in the drawings

1, 100: FGA programming apparatus

11: central processing unit (CPU)

12: Joint Test Access Group (JTAG) Connector

13: Fusing ROM section

20: board

21, 111 ': First FFP

22, 112 ': Second FFP

23, 113 ': Third FFP

110: data processor 111: FGA

120: processor unit

130: FPGA programming control unit

140: flash memory unit

150: internal processor communication (IPC)

Field Programmable Gate Array (FPGA) programming of the present invention, and more particularly, to the FGP (FGA) mounted on the remote board by transmitting the FGGA programming data to the remote board ( The present invention relates to a remote FFP programming device and a method for performing programming on an FPGA.

Fig. 1 is a block diagram of a prior art Field Programmable Gate Array (FPGA) programming device 1.

As shown in FIG. 1, a prior art Field Programmable Gate Array (FPGA) programming device 1 includes a Field Programmable Gate Array (FPGA) programming device 10 for processing FG programming. ) May be connected to the board 20 through a serial communication interface to program at least one or more FGAs, such as the first to third FFAs 21, 22, and 23 mounted on the board 20. It is configured to.

In the above-described configuration, the field programmable gate array (FPGA) programming device 10 includes a central processing unit (CPU) for processing field programmable gate array (FPGA) programming by dedicated programming therein; A JTAG connector unit 12 which receives JTAG data for field programmable gate array (FPGA) programming through a parallel cable and converts the signal to an appropriate voltage level; It consists of a fusing ROM unit 13 that stores the FGA data (FPGA) output through the joint test action group (JTAG) connector unit 12.

In the prior art Field Programmable Gate Array (FPGA) programming device 1 having the above-described configuration, the central processing unit (CPU) 11 is adapted to upgrade at least one or more FGEAs (FPGA1, FPGA2, FPGA3). After creating the required JTAG (Joint test Action Group) data, determine the JTAG state machine by TMS (test mode selection) and TCLK (task clock) among the JTAG signals, and then TDO (test data output) and TDI. (Test data input) and the like are outputted to the fusing ROM unit 13 through the JTAG connector unit 12 and stored.

Thereafter, the FP A programming device 10 is connected to a board 20 'having a plurality of FP AGAs by a serial cable and the like, and then the data of the fusing ROM unit 13 is transferred to the central processing unit 11. The first to third FpGs 21, 22, and 23 are sequentially fused by transmitting the same to the board 20 according to the control command.

In the prior art, as described in the above, FFP programming is performed after FFP programming using the software tool and the cable. Board 20 having respective F-PGEs (e.g., first to third F-PGAs 21, 22, and 23) connected in series to the Fiji programming device unit 10. ) To program FFP through serial cable.

In addition, when the FFP programming for one board 20 is terminated, after connecting the FFP programming device 20 with the other board, the process as described above is repeated, and the FPI for each board is repeated. A programming will be performed.

Therefore, in the case of the conventional FFIAGE programming device and method as described above, the FFF mounted on the board after connecting directly to the position of the communication station where the respective boards are installed is connected to the FFIAGE programming device. Since Fiji A needs to be programmed, it requires a lot of manpower, time, and cost to manage FFI AGE per board.

Accordingly, the present invention is to solve the above-described problems of the prior art, the FPP A programming data having identifier information for the IPC (Internal Processor Communication Protocol) communication of the processor unit of the board connected to the communication network (FPGA: Field Programmable Gate Array Programming Data) provides a remote FPM programming device and a method for performing the FPC programming in which the IPC (IPC) information is extracted from a corresponding board when transmitted through a communication network. For that purpose.

The remote field programmable gate array (FPGA) programming device of the present invention for achieving the above object, extracts the processor unit output target data using the identifier from the user data received from the outside and outputs it to the processor unit A data processor; A processor unit which receives the processor unit output target data input from the data processor, stores the target object output data in a flash memory unit, and outputs a field programmable gate array (FPGA) command to the FPC controller; An FFP programming controller configured to read the FPI programming data among the processor unit output target data stored in the flash memory unit after receiving the FPP programming command and then perform programming for the FPI of the data processing unit; ; And a flash memory unit for storing processor output target data input from the processor unit.

The data processor and the processor perform communication through an IPC (Internal Processor Communication Protocol). In addition, data communication is performed with the Field Programmable Gate Array (FPGA) control unit by an internal parallel bus.

In this case, an address for an internal processor communication protocol (IPC) is allocated to the processor unit, and an address of the processor unit is set as a destination address in the processor unit output target data. In this case, the address information of the processor unit becomes the identifier. The address assigned to the processor is an IP address when the present invention is applied to an IP network, and a VPI / VCI (Virtual Path Identifier / Virtual Channel Identifier) when applied to an ATM network.

Accordingly, the data processing unit checks the destination address information of the input data, and if the destination address information matches the address information assigned to the processor unit, identifies the data as the processor unit output target data and then extracts the data to the IPC method. To the processor unit.

The processor output target data detected by the data processor includes firmware data for driving the processor and field programmable gate array (FPGA) data.

Accordingly, the flash memory unit may include a firmware storage area for storing firmware data for driving the processor, an FPM programming data storage area for storing FPI programming data, and an old version of FPM programming data. The storage program consists of programming backup data storage area.

The FP programming controller temporarily stores transmission / reception data of the processor unit and the flash memory unit, and when the FP programming is performed, a buffer for blocking a connection from the processor unit to the flash memory unit; When the processor receives the FPI programming command, the processor disables the buffer, reads programming data into the FPI of the flash memory unit, and executes an FPI program for the FPI of the data processor. A programming logic unit; characterized in that comprises a.

In order to achieve the above object, the remote FFP programming of the present invention (Field Programmable Gate Array) (FPGA) method,

A processor unit output target data detection process of detecting, by the data processor, the processor unit output target data using an identifier among the received data from the outside and outputting the data to the processor unit;

A flash memory unit storing process of storing the processor unit output target data in the flash memory;

When the storage of the processor unit output target data is ended, a field programmable gate array (FPGA) programming command is output and the processor unit output target data is used for the FPI of the data processor of the data processor. It is characterized in that it comprises a; F-P-G programming process for performing the F-P-G programming for this.

The processor unit output target data detection process may detect the data as processor unit output target data when the destination address information of the received data is address information allocated to the processor.

In this case, the identifier is address information allocated to the processor unit for IPC communication, and the address is set to an IP address in case of an IP network, and VPI / VCI (Virtual Path Identifier) when applied to an ATM network. / Virtual Channel Identifier).

In the process of detecting the processor unit output target data, the processor unit output target data is output to the processor unit by IPC (Internal Processor Communication Protocol).

In this case, the processor unit output target data includes firmware data as an application program for driving the processor unit and FFP programming data.

The flash memory unit storing process may include: a firmware data storing process of storing firmware data among the detected data; Among the detected data, the FPGA Programming data is stored in the FPGA Programming backup data storage area and the FPGA Programming data storage area is set as the FPGA programming data storage area. Process;

A step of setting an FPGA programming backup data storage area to set the FPGA programming data storage area as an FPGA programming backup data storage area. do.

The program processing may include: a buffer blocking process for disabling an output of a buffer between the processor unit and the flash memory unit; After the buffer blocking process, the data processing unit FPI A programming process for performing the programming by reading the F-PI programming data of the flash memory unit is characterized in that it comprises a.

In the data processing unit FPI programming, the FPM backup programming reads data from the F programming backup data storage area and re-executes FPGA programming when an error occurs during the programming. Process; If the FPM backup program is normally operated after the FPC backup program, the FPM program re-requests data to the upper system processor, and then returns to the processor unit output target data detection process to repeat the process. The process; characterized in that further comprises.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

Figure 2 is a block diagram of a remote FFP programming device of the present invention.

As shown in FIG. 2, the remote FFP programming device 100 includes: a data processor 110 for extracting processor unit output target data from user data received from the outside and outputting the output data to the processor unit; After receiving the processor 120 output target data input from the data processor 110 and storing it in the flash memory unit 140 via the buffer 131 of the FP programming controller 130, the FPI program A processor unit 120 outputting a ramming command to the FP programming controller 130; After receiving the Field Programmable Gate Array (FPGA) programming command, the program processor reads the program programming data among the processor unit output target data stored in the flash memory unit, and then, A field programmable gate array (FPGA) programming controller 130 for performing programming; And a flash memory unit 140 storing processor output target data input from the processor unit.

The data processor 110 is connected to the processor 110 to perform communication by IPC (Internal Processor Communication Protocol), and is connected to a physical link to transmit and receive user traffic and IP data with the outside, It is also connected to the switching block for data and IP data communication with other component blocks in the system, and performs the function of transmitting and receiving data and IP data for user traffic between the switching block and the physical link in the system, and the data transmitted and received An FFP unit 111 which detects IP data (processor unit output target data) destined for the processor unit 110 as a destination and outputs it to the processor unit 110 is provided.

The FP 111 of the data processor 110 having the above-described configuration communicates with the processor 110 in an internal processor communication protocol (IPC) method. In addition, data communication with the Field Programmable Gate Array (FPGA) programming controller 120 is performed by an internal parallel bus.

The processor unit 120 is assigned an address for the transmission and reception of IPC data, and the processor unit output target data (IPC data) transmitted and received through the data processing unit 110. The address of the processor unit 110 is set as a destination address. In this case, the address assigned to the processor 110 may be assigned an IP address when the present invention is applied to an IP network, and a VPI / VCI may be assigned when the present invention is applied to an ATM network. As described above, an address for the processor unit output target data is an address of the processor unit set as the destination address in the data to be transmitted and received.

Accordingly, the data processor 110 checks the destination address information of the input data, and if the destination address information matches the address information assigned to the processor unit, identifies and extracts the output data (PC data) of the processor unit. After the output to the processor unit 120 by the IPC (IPC) method.

The FP programming controller 130 stores output data of the processor unit 120 in the flash memory unit 140, and the processor unit 120 accesses the flash memory unit 140 to read and drive the firmware program. Do it. In addition, when the FPI programming command is input from the processor 120, the FPS programming for the FGE 111 of the data processing unit 110 is performed.

FIG. 3 illustrates a detailed configuration of the FPM programming controller 130. The FFP programming controller 130 is a processor 120 that accesses and transmits data to and from the flash memory unit 140. FIG. A buffer 131 for temporarily storing the block and blocking the connection from the processor unit 120 to the flash memory unit 140 when FPI programming is performed; When the FPI programming command of the processor unit 120 is input, the FFP programming logic unit is driven to perform the FFP programming for the FGA unit 111 of the data processing unit 110 ( 132).

When the FPM programming controller 130 having the above-described configuration receives an FFP programming command from the processor unit 120, the FFP programming logic unit 132 is configured to include the processor unit ( In order to block the connection to the flash memory unit 140 of the 120, the output of the buffer 131 is disabled, and then the flash memory unit 140 is connected to read programming data into the FPI to read the data processor. The FFIAGE programming is performed on the FFP unit 111 of 110. In this case, the FFP programming logic unit 132 is preferably implemented as a programmable logic device (PLD).

In the present invention having the above-described configuration, the data transmitted and received by the data processing unit 110 includes user traffic data such as voice and PCC data as processor unit output target data transmitted / received between a processor in the system, and the data processing unit ( The processor unit output target data (PCC data) detected by the controller 110 includes firmware data for driving the processor unit 120 and field programmable gate array (FPGA) data. .

Therefore, the flash memory unit 140 classifies each data and stores the data for each area. 4 is a diagram illustrating a structure of a storage area of a flash memory unit 140 for classifying and storing data as described above. As shown in FIG. 4, the flash memory unit 140 is configured to drive a processor unit. A firmware storage area 141 in which firmware data is stored, an FPM programming data storage area 142 in which an update target FPGA programming data is stored, and an FPI programming data before updating. Is configured as an FGI programming backup data storage area 143.

5 is a flowchart illustrating a process of a remote FFP programming method of the present invention.

Referring to FIGS. 2 to 4, a process of the field programmable gate array (FPGA) programming method of the present invention of FIG. 5 will be described.

Data including user traffic and IPC data as processor unit output target data from a switching block or an external physical link in a board-mounted system having the program target FPI of the present invention (processor output target data) ) Is input, the data processing unit 110 determines whether IPC data including the processor 110 as a destination is included. In this process, the determination of the output target data of the processor unit 110 is determined using the address information assigned to the processor unit 120 as an identifier, and the destination address of the input IP data is allocated to the processor unit 120. The data corresponding to the address is determined as IP data as the processor 120 output target data. The address of the processor unit 120 becomes an IP address when applied to an IP network, and VPI / VCI (Virtual Path Identifier / Virtual Channel Identifier) information when applied to an ATM network (S10).

If no data using the processor 120 as the destination address is detected among the user traffic and the IP data traffic input in step S10, after the general data processing for processing the user traffic data is performed, the processing is terminated (S20). ).

On the contrary, if IPC data having the processor 120 as the destination address is detected among the data traffic inputted as a result of the determination of S10, the IPC data is detected by detecting the corresponding IPC data. Output to the processor unit 120 in a Communication Protocol) manner. As described above, the IPC data, the firmware data for driving the processor 120, and the FPI programming data are included (S30).

The processor unit 120 that receives the IPC data from the data processor 110 stores the received data in the flash memory unit 140 through the FPC programming controller 130. At this time, the firmware data for driving the processor 120 among the IPC data is stored in the firmware data storage area 141, and the FPI programming data is stored in the FPI programming backup data storage area. The firmware data, the FP A programming data, and the FP A by displaying the F.P programming data storage area and setting the conventional F.P programming data storage area to the F.P programming backup data storage area. The programming backup data is classified and stored (S40).

After the storage of the flash memory unit 140 for the IP data is terminated by the process S40, the processor unit 120 outputs the FPI programming command to the FPM programming controller 130 (S50).

When the FP A programming command is received from the processor 120, the F P A programming logic unit 132 of the F P A programming controller 130 is activated to disable the output terminal of the buffer 131. The connection of the flash memory unit 140 of the processor unit 120 is blocked. Subsequently, the data of the fP A programming data storage area 142 of the flash memory unit 140 is read and then programmed into the F PGA unit 111 of the data processing unit 110 (fusing). Perform (S60).

In the step S60, if there is an error in the FP programming data or an error occurs during the FPGA programming, the FP programming logic unit 132 stores the FP programming backup data of the flash memory unit 140. Read data from the area and re-execute FFP programming. After that, if normal operation is performed by programming with the FPI programming data before the error, the error status is reported to the system processor module and updated by repeating the above process by retransmitting the FFP programming data. This ends FGF for this programming.

In the present invention as described above, when the processor 120 of a board having a corresponding FPG is transmitted from a remote location, the FPG programming data is transmitted using the destination address as an identifier, and the data processing unit 110 of the board includes the FPC. After identification and detection, the processor unit 120 outputs the processor 120 by an IPC method, and the processor unit 120 performs programming (fusing) on the FFP of the board to be programmed. Allows you to perform programming on FPI.

6 is a schematic block diagram of a W-CDMA user traffic processing apparatus according to an embodiment to which the present invention is applied.

As shown in FIG. 6, when the present invention is applied to a W-CDMA user traffic processing apparatus based on an ATM network, the board 100 ′ for user traffic processing is as described in FIGS. 2 to 5. The data processing unit 110 ′ and the processor unit 120 for processing W-CDMA user traffic, the FPM programming controller 130, and a flash memory unit 140 are configured.

In the above configuration, the processor unit 120 is assigned VPI / VCI as address information, and the processor unit 120 output target data is assigned a VPI / VCI address of the processor unit 120 as a destination address.

The data processing unit 110 ′ for the user traffic processing includes a first F for performing ATM cell interface functions and extracting IPC data as data output from the processor unit from data traffic for data communication with a switching block. FPGA1 (111 ') and a second AFP (FPGA2) that performs an AAL (ATM Adaptation Layer) frame, in particular AAL2 (ATM Adaptation Layer Type 2) frame processing function and a segmentation and reassembly (SAR) function ( 112 ') and a third FFP3 (113') which provides a physical link interface for a physical link of an IP network, and performs user data traffic processing for transmitting and receiving voice and multimedia data packets. do.

That is, in the above-described configuration, the first FP 111 111 'performs the function of extracting the IP data as output data of the processor unit 120 according to the present invention.

In the W-CDMA user traffic processing apparatus having the configuration of FIG. 6 described above, an operation process for programming FGF according to the present invention will be described.

The data processor 110 ′ performs a function of transmitting and receiving data between the switching block and the physical link in the WCDMA system using the first through third FGEs 111 ′ 112 ′ 113 ′. At this time, in order to communicate with the processor module of the entire board-mounted system, the IPC data in the form of ATM cell is transmitted and received with the processor unit 120 in the module using a data path for transmitting user traffic. The first FP 111 111 detects IPC data as the output data of the processor 120 from the transmitted data, and outputs the IPC data to the processor 120 by the IPC method. . On the contrary, the IPC data received from the processor 120 is output as a switching block and transmitted to another processor in the system.

In the above-described process, the condition for distinguishing the IPC data from the general user data is classified by the VPI / VCI field value of the ATM. That is, the data having the VPI / VCI information allocated to the processor 120 is detected as IP data. User data other than IPC data is transmitted through a physical link, and user data received through the physical link is transmitted through a switching block.

The processor unit 120 that receives the IP data from the first FP 111 of the data processing unit 110 ′ transmits each function unit and a function execution option through the CPU bus, and each function unit Understand the condition. Also, among the received IPC data, the FPGA programming data is transferred to the FPGA programming data storage area 142 of the flash memory unit 140 through the FP programming controller 130. Save it.

As illustrated in FIG. 3, the FPGA programming controller 130 includes a buffer 131 and an FPGA programming logic unit 132 to store the FPGA programming data in a flash memory. The first to third FGEAs 111 of the data processing unit 110 ′ with the function of storing the data in the unit 140 and the data of the FPGA programming data storage area 142 of the flash memory unit 140. ', 112', 113 ').

The above-described functions are all performed by the FPI programming logic unit 132 configured of a programmable logic device (PLD). Among the FPI update functions, the FP programming logic unit 132 outputs the buffer 131 to prevent data collision due to access to the flash memory unit 140 of the processor unit 110. After the operation is set to a high impedance state, the flash memory unit 140 is controlled to read the FPGA programming data to update the FPGAs of the data processing unit 110 ′. Perform the function.

In addition, as illustrated in FIG. 4, the flash memory unit 140 includes a firmware data storage area 141, an FPGA programming data storage area 142, and an F FIG programming. The backup data storage area 143 has been described above.

In the above-described configuration, the processor unit 120 updates the first to third FGEs 111 ′, 112 ′, and 113 ′ of the data processor 110 ′ with the FP programming controller 130. command), the FG programming logic unit 132 of the FG A programming controller 130 performs the functions as described above, so that the first to third FGE of the data processing unit 110 '(FPGA) are executed. (111 ', 112', 113 ') is performed (fusing).

At this time, if there is an error in the FPGA programming data or an error occurs during FPGA programming, the data processing unit 110 ′ malfunctions and the user ( User) Data as well as IPC (IPC) data can not be transmitted and received. At this time, the FP programming logic unit 132 of the FP programming controller 130 reads the data of the FP programming backup data storage area of the flash memory unit 140 and reprograms the FPGA programming. To perform. After normal operation, the remote FPI programming is terminated by reporting an error state to the system processor module, retransmitting the FFP programming data, and repeating the above process.

According to the present invention, the FFIAGE programming data including an identifier for identifying the data for the FPGA programming of the board in the data traffic transmitted and received is transmitted to the board equipped with the FTJI with user data. By transmitting, you can perform FPI programming, such as remote update, so that you can easily manage the update and save time and money for system management. .

In addition, the present invention described above is able to store both the firmware data, the F-PG A programming data, and the F-P-G programming backup data in a single flash memory, so that the F-F-A programming such as the F-P-A update can be stably performed. It also provides an effect.

Claims (13)

A data processing unit which extracts processor unit output target data from the user data received from the outside and outputs the data to the processor unit; A processor unit configured to receive processor unit output target data inputted from the data processor, store the data in a flash memory unit, and output a field programmable gate array (FPGA) programming command to an FPGA programming controller; ; After receiving the FPGA programming command (FGA) to read the FG programming data of the processor unit output target data stored in the flash memory unit and the F processor to perform programming for the F TAG An FPGA programming control unit; And a flash memory unit for storing processor output target data inputted from the processor unit. The apparatus of claim 1, wherein the data processing unit and the processor unit communicate with each other by an internal processor communication protocol (IPC). The apparatus of claim 1, wherein the identifier is an address for internal processor communication protocol (IPC) communication allocated to the processor unit. The apparatus of claim 3, wherein an IP address allocated to the processor unit is any one of an IP address and a virtual path identifier / virtual channel identifier (VPI / VCI). The remote processor of claim 1, wherein the processor unit output target data detected by the data processor includes firmware data for driving the processor unit, and FPGA programming data. A programming device. The method of claim 1, wherein the flash memory unit, A firmware storage area for storing firmware data for driving the processor unit, an Fp programming data storage area for storing the FP programming data, and an Fp programming program for storing the FPI programming data before updating A remote FPM programming device comprising: a programming backup data storage. The program of claim 1, wherein the FPM programming controller comprises: A buffer which temporarily stores transmission / reception data of the processor unit and the flash memory unit and blocks the connection from the processor unit to the flash memory unit when FPI programming is performed; When the processor receives the FPI programming command, the processor disables the buffer, reads programming data into the FPI of the flash memory unit, and executes an FPI program for the FPI of the data processor. A programming logic unit; a remote AFP programming device comprising a. A processor unit output target data detection process of detecting, by the data processor, the processor unit output target data using an identifier among the received data from the outside and outputting the data to the processor unit; A flash memory unit storing process of storing the processor unit output target data in the flash memory; If the storage of the output data of the processor unit is finished, the F pid A programming process for outputting the F pid A programming for the F pid A of the data processing unit; This programming method on remote FPI. The remote FP programming of claim 8, wherein the detecting of the processor unit output target data comprises outputting the detected processor unit output target data to the processor unit by using an internal processor communication protocol (IPC) method. Way. The method of claim 8, wherein the detecting of the processor unit output target data comprises: And if the destination address information of the received data is address information assigned to the processor, detecting the data as processor unit output target data. The method of claim 8, wherein the identifier is set to an address for an IPC of the processor unit, and the address of the processor unit is set to one of an IP address or a virtual path identifier / virtual channel identifier (VPI / VCI). Featuring Remote FPI Programming Method. The method of claim 8, wherein the flash memory unit storage process, A firmware data storing step of storing firmware data among the detected data; Field Programmable Gate Array (FPGA) data among the detected data is stored in the field Programmable Gate Array (FPGA) backup data storage area. Programmable Gate Array) programming) data storage process; Field Programmable Gate Array (FPGA) data storage area is set as a Field Programmable Gate Array (FPGA) backup data storage area. Array) Programming) Remote FPM programming method comprising a; backup data storage area setting process. The method of claim 8, wherein the FFP programming process comprises: A buffer blocking process for disabling an output of a buffer between the processor unit and the flash memory unit; An FPM backup programming process of re-executing FFP programming by reading data in the FPP programming backup data storage area when an error occurs during the FFP programming after the buffer blocking process; If the FPM backup program is normally operated after the FPC backup program, the FPM program re-requests data to the upper system processor, and then returns to the processor unit output target data detection process to repeat the process. Remote fPGE programming method characterized in that it further comprises a.

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