KR20070048382A - Display system for high definition electric bulletin board compromising data speed - Google Patents

Abstract

The system of the present invention comprises an input block, a memory block, and an output block, wherein the input block is configured to display a video signal from a serial communication line in a high-resolution display system for displaying a high quality image regardless of a data input speed. An input unit for receiving input, (2) an input buffer for receiving and collecting data from the input unit, and transferring data collected in a predetermined amount to a memory set for input among double frame memories; and (3) data for the input unit if a start code is detected. (4) a buffer control unit for synchronizing the input buffer after detecting a start code by detecting a start code and detecting a data transfer rate when the transfer is initiated and the end code is detected. The memory block (1) receives data from the input buffer and collects a predetermined amount of data. Double frame memory to transfer data, and (2) start data transmission when the input buffer is full, and when one of the double frame memories set for input is full, it is switched for output and is connected to the electronic board interface at 60 sec. And a memory controller for starting data writing to a frame and switching the other memory for input to start reading data from the input buffer, wherein the output block is (1) for output among the double frame memories. And a display board connected to the display board by receiving data from the set memory, and (2) the display board connected to the display board interface.

Data rates, high definition billboards, display systems, buffers, frames

Description

Display system for high definition electric bulletin board compromising data speed}

1 is an overall block diagram of the system of the present invention.

2 is a flowchart showing the control flow of the input control unit.

3 is a flowchart showing the control flow of the buffer control unit.

4 is a flowchart showing the control flow of the memory control unit.

<Description of Symbols for Main Parts of Drawings>

10: input block

11: Video signal input unit

12: Input buffer

13: input control unit

14: buffer control unit

20: memory block

21: double frame memory

22: memory controller

30: output block

31: billboard interface

32: scoreboard

The present invention relates to a high-definition display board display system that complements the data rate, and more particularly, to a full-color display board system, high-definition image information of 60 frames per second according to the visual characteristics of a human being regardless of the transmission speed of the input image. To display on.

In general, the electric signboard system is largely divided into a monochromatic sign board and a full color sign board. In the monochromatic light display board, the control of each pixel is performed by turning on and off. In some cases, the entire display board may be actually a pixel device of one color, but the pixel devices of 1 to 3 colors may only be turned on and off. It is also included. The full-color electronic display board is a high-definition electronic display board, which is based on three primary colors of red, green, and blue (RGB) colors, and enables not only on / off adjustment but also brightness adjustment for each pixel unit. Configure. As a display element constituting each pixel of the light-emitting plate, a light-emitting body such as a light emitting diode or a fluorescent lamp is mainly used. Such electric signboards are mainly installed indoors and outdoors, and are used to provide various people with the necessary information and advertisements by various graphics and moving pictures.

The monochromatic light display board can be controlled by having only one bit of information amount of on and off for each pixel. Therefore, the image data used in the monochromatic display board system is a small amount, and the input of such small amount of image information can be processed through the low speed serial communication for the conventional lighting and sound control.

However, the full color billboard must have a 24-bit information amount for each pixel. Therefore, the image data used in the full-color electronic display system is large, and the input of this data is impossible to process through the low speed serial communication for the conventional lighting and sound control, and therefore, the high speed and high capacity data processing is possible. It is handled through parallel communication.

However, in this way, the full color display system cannot maintain compatibility with the serial communication protocols commonly used in lighting and sound systems including the existing monochromatic display boards, and the data through the serial communication network that is already widely used. Has become impossible to send or receive.

In addition, although a case may be considered in which data is input directly through a serial communication in a full color billboard system, since the speed of serial communication is significantly lower than a processing speed of the full color billboard system, a line is displayed horizontally on the screen. Displayed in the order of receiving a single line of data occurred, there was a problem that a significant degradation of the display quality for advertising and information provision.

In the present invention, while displaying a high-resolution, high-definition image on the electronic display board, it is possible to use the serial communication protocol used in the existing lighting and sound system (maintain compatibility), to provide a method for ensuring the compatibility of the system I want to.

In addition, when implementing a signboard system, to provide a system capable of displaying a constant high-definition image even for the image input through a relatively slow communication speed.

In order to achieve the above object, the system of the present invention is composed of an input block, a memory block, and an output block, the display block display system for displaying in high quality regardless of the data input speed, the input block is (1) (2) an input buffer for receiving a video signal from a serial communication line, (2) an input buffer for receiving and collecting data from the input unit, and transferring a predetermined amount of data to a memory set for input in a double frame memory; and (3) a start code. Detects a data transmission speed by detecting the start code; and (4) detecting a data transmission rate after detecting a start code. And a buffer control unit for matching the memory block, wherein the memory block comprises (1) receiving data from the input buffer and A double frame memory for transferring the collected data to the electronic board interface, and (2) when the input buffer is full, data transmission is started, and when one of the double frame memories is set for input, the data is switched for output. And a memory control unit for starting data writing to the interface at 60 frames per second and at the same time switching the other memory for input to start reading data from the input buffer, wherein the output block comprises: (1) the double frame; And a display board interface for receiving data from a memory set for output in the memory, the display board interface being displayed on the display board, and (2) the display board connected to the display board interface.

Here, the buffer control unit sets a read point of the input buffer based on the start code and the transfer rate, and the memory controller starts data transmission from the read point of the input buffer when the input buffer is full. It may be characterized in that it is configured to.

Here, the start code is a bit string having a predetermined length consisting of repetitions of 0 and 1, and the buffer control unit is configured to detect the number of repetitions of 0 and 1 and the speed of repetition to detect a data transmission rate. It may be featured.

In this case, the input buffer may be configured as a dual port buffer in which the input portion of the data and the output portion of the data are controlled asynchronously.

Here, the video signal input from the serial communication line to the input unit may be characterized by consisting of video information of 60 frames or less per second.

<Example>

EMBODIMENT OF THE INVENTION Hereinafter, the structure of this invention is demonstrated in detail with reference to an accompanying drawing. Here, the detailed description may be omitted for the configuration having the same function, with reference to the same symbol.

1 is an overall block diagram of the system of the present invention.

The system of the present invention is largely composed of three blocks of an input block 10, a memory block 20, and an output block 30. The organic combination of these blocks constitutes an electronic display system for displaying in high quality regardless of data input speed.

The input block 10 includes an input unit 11, an input buffer 12, an input control unit 13, and a buffer control unit 14. The input block 10 receives a video signal and adjusts the speed of the input video from the input video signal. After detection and synchronization, the data is stored in the input buffer 12.

The input unit 11 is a component that receives a video signal from a serial communication line. The serial communication is a communication method that has conventionally been used for electronic data input, and its transmission speed is slower than that of parallel communication. For example, a video signal input from the serial communication line to the input unit 11 is generally composed of video information of 60 frames or less per second.

The input buffer 12 receives data from the input unit 11, collects the data, and collects a predetermined amount of data into a later double frame memory 21, that is, a memory set for input among the first memory or the second memory. The component to transmit. Here, the input buffer 12 is preferably composed of a two-layer dual port buffer in which the input and output of the data is controlled asynchronously. This is to prevent overwriting of data to be output by input and to safely support fast input / output.

2 is a flowchart showing the control flow of the input control unit 13.

The input control unit 13 is a component that controls the input unit 11. The input control unit 13 is controlled to start data transmission of the input unit 11 when detecting the start code and to stop data transmission of the input unit 11 when detecting the end code. Here, the start code is a kind of identification code for notifying the start of the video data, and may be formed of a bit string having a predetermined length consisting of 0 and 1 repetitions, for example.

3 is a flowchart showing the control flow of the buffer control unit 14.

The buffer control unit 14 is a component that controls the input buffer 12. The buffer control unit 14 detects the start code to detect the data transfer rate, and then synchronizes the input buffer 12. In addition, the buffer control unit 14 may be configured to set the time point at which the input buffer 12 is read out based on the start code and the transmission speed. The buffer controller 14 may be configured to detect the number of repetitions of 0 and 1 and the speed of repetition of the start code and detect the data transfer rate therefrom.

The memory block 20 includes a double frame memory 21 and a memory controller 22, and a signal control function for transmitting data stored in the input buffer 12 to the double frame memory 21; It has a signal control function for transmitting the data stored in the double frame memory 21 to the electronic display board interface (31).

The double frame memory 21 is composed of a first memory and a second memory that receive data from the input buffer 12 and transmit data, which is collected in a predetermined amount, to the electronic display board interface 31 at the rear stage. One side of the first memory and the second memory of the double frame memory 21 is set for input, and the other side thereof is set for output. Therefore, the memory set for the input receives and stores data from the input buffer 12, while the memory set for the output transmits the data to the electronic display board interface 31. The input and output operations are performed simultaneously, and when the input is completed, the roles of these input and output memories are configured to be reversed. The double frame memory 21 may be constituted by one memory element, divided by its internal address, or constituted by two separate memory elements. For ease of implementation and system cost, it is desirable to be physically located in one memory device. For this purpose, it is preferable to apply a time division technique to read and write in memory access.

4 is a flowchart showing the control flow of the memory control unit 22.

The memory controller 22 is a component that controls the double frame memory 21. The memory controller 22 starts data transfer when the input buffer 12 is full. The data is transmitted to the double frame memory 21. When one of the first memory and the second memory of the double frame memory 21 is set for input by the data transfer, the setting is switched for output. At the same time, the other memory originally set for output is switched for input, and control is started to start reading data from the input buffer 12. At the same time, from the memory set for the output, data writing is started in the frame interface 31 at 60 frames per second.

Here, when the input buffer 12 is full, the memory controller 22 controls to start data transfer from the time point at which the input buffer 12 is set to be read.

The output block 30 is composed of a signboard interface 31 and a signboard 32, and generates an interface signal to read image data from the double frame memory 21 and display the sign on the signboard. This block is visible.

The electronic board interface 31 is a component that receives data from the first memory or the second memory, which is the double frame memory 21, is set for output, and is displayed on the electronic board 32. The data transmitted to the sign board interface 31 is output as it is to the sign board 32 connected thereto through a well-known process, and is visible.

Hereinafter, the operation of the present invention will be described in detail.

When a video signal is input to the input unit 11 via the serial communication protocol, the input control unit 13 detects a predefined start code and transmits the video data up to the stop code to the input buffer 12. Then, the buffer control unit 14 detects the speed of the video signal from the start code input with the predefined pattern, and sets the time point at which the input buffer 12 is read out based on this. At this time, in order to facilitate speed detection from the start code, it is preferable to take a code pattern in which 0 and 1 values are repeatedly displayed. In addition, the signal frequency for speed detection uses a clock frequency of the output block 30. By doing so, the ease of system implementation and the accuracy of speed detection can be ensured.

When the data recorded in the input buffer 12 fills the preset amount in the buffer control unit 14, the memory control unit 22 enters the memory set as an input (write to the memory) of the double frame memory 21. Perform signal processing for the write operation.

The double frame memory 21 is composed of two memories, namely, a first memory and a second memory, each of which stores one frame of data. In particular, the memory used for the operation of reading data from the input buffer 12 and storing the data and the memory used for the operation of reading the stored data and transmitting it to the electronic display board interface 31 are separately managed. Each of these memories is configured to switch their roles.

If the first memory is receiving data of the first frame from the input buffer 12 and the second memory is empty, the first memory is a memory set as an input, and the second memory is set (or not set) as an output. Memory. When data transfer is completed and the first memory is in a state in which all data of the first frame is stored, the following is obtained.

First memory: first frame data

Second memory: empty.

The memory controller 22 switches the roles of the first memory and the second memory to each other. That is, the first frame data is transmitted from the first memory to the display board interface 31 and displayed on the display board, and the second frame data is transmitted from the input buffer 12 to the second memory. That is, the first memory is a memory set as an output, and the second memory is a memory set as an input.

First memory: first frame data (during output)

Second memory: second frame data (in input)

When the transfer is complete,

First memory: first frame data (output complete)

Second memory: second frame data (input completed)

The memory controller 22 again switches the roles of the first memory and the second memory. That is, the second frame data is transmitted from the second memory to the display board interface 31 and displayed on the display board, and the third frame data is transmitted from the input buffer 12 to the first memory. That is, the second memory is a memory set as an output, and the first memory is a memory set as an input.

First memory: third frame data (in input)

Second memory: second frame data (during output)

When the transfer is complete,

First memory: third frame data (complete input)

Second memory: second frame data (output complete)

Again, the switching operation is performed by the memory controller 22, and the switching is repeated.

Thus, the input and output of each frame of memory is as follows (frames are numbers only. Input and output are output).

First memory: 1 (in) → 1 (out) → 3 (in) → 3 (out).

Second memory: 0 → 2 (in) → 2 (out) → 4 (in).

In the setting of the switching time point, it is preferable that the switching request signal is generated when the input to the memory set as the input is completed, and the switching operation is performed after the display of the frame on the actual display board 32 is completed. Do.

In this case, in the output of the frame in which the double frame memory 21 is written (input to the memory), the flicker of the image frame is not displayed to the viewer by the control of the memory controller 22. In this case, the video must be continuously displayed at 60 frames per second. This may be complemented by the above-described setting of the frame switching timing.

Finally, the memory control unit 22 displays the electronic display interface for displaying on the electronic display board on the basis of the memory converted to the read (read from memory) frame after the writing (writing to the memory) of the double frame memory 21 is completed. (31) A control signal is generated, and the electronic sign interface 31 outputs the video signal to the electronic sign 32 in synchronization with this.

If the input video signal is data of 30 frames per second, and the transmission rate of the serial communication itself satisfies the minimum required speed, one frame may be stored in the memory every 1/30 seconds, and the electronic display board interface 31 may be used. In order to output every 1/60 second, it is necessary to repeat the switching operation after outputting the same frame twice. In other words, although it is output at the rate of 60 frames per second, what is actually seen is an image rate of 30 frames per second. However, since the data corresponding to one frame is output twice, visual flicker does not occur.

If the input video signal is 30 frames per second and the transmission rate of the serial communication itself is 1/2 of the minimum required rate, one frame may be stored in the memory every 1/15 seconds, and the display board interface ( To output every 1/60 second to 31), it is necessary to repeat the switching operation after outputting the same frame four times. In other words, although it is output at the rate of 60 frames per second, what is actually seen is an image rate of 15 frames per second. However, since the data corresponding to one frame is output four times, visual flicker does not occur.

In the above, the present invention has been described by way of examples, but the present invention is not limited thereto, and various changes can be made by those skilled in the art without changing the technical configuration of the present invention, which is within the scope of the present invention. It is obvious that it is included.

According to the present invention as described above, it is possible to ensure the compatibility of the system by displaying a high-resolution, high-definition image on the electronic signboard, while maintaining (compatibility maintained) the serial communication protocol used in the existing lighting and sound system. .

In addition, when implementing the electronic signboard system, it is possible to display a constant high-definition image even for a video input through a relatively slow communication speed.

Claims (5)

In the electronic display display system consisting of an input block, a memory block, and an output block to display in high quality regardless of the data input speed, The input block is, (1) an input unit for receiving a video signal from a serial communication line, (2) an input buffer which receives and collects data from the input unit and transfers the collected data to a memory set for input among the double frame memories; (3) an input control unit for starting data transmission of the input unit when detecting a start code, and stopping data transmission of the input unit when detecting a ending code; (4) a buffer control unit which detects a start code to detect a data transmission rate and synchronizes the input buffer; Consisting of, The memory block, (1) a double frame memory for receiving data from the input buffer and transmitting data collected in a predetermined amount to an electronic board interface; (2) When the input buffer is full, data transmission is started. When one of the double-frame memories set for input is full, the data is switched for output to start writing data at 60 frames per second to the electronic board interface. A memory controller for switching the other memory for input to start reading data from the input buffer; Consists of, The output block is, (1) an electronic board interface for receiving data from a memory set for output in the double frame memory and displaying it on the electronic board; (2) an electronic board connected to the electronic board interface Consist of High-definition billboard display system, characterized in that to complement the data rate. The method according to claim 1, The buffer control unit sets a read point of time of the input buffer based on the start code and the transmission speed, The memory controller is configured to start data transmission from a reading point of the input buffer when the input buffer is full. High-definition billboard display system, characterized in that to complement the data rate. The method according to claim 1, The start code is a bit string of a predetermined length consisting of repetitions of 0 and 1, The buffer controller is configured to detect a data transmission rate by detecting the number of repetitions of 0 and 1 and the speed of repetition. High-definition billboard display system, characterized in that to complement the data rate. The method according to claim 1, The input buffer is composed of a dual port buffer in which the input and data output portions of the data are controlled asynchronously. High-definition billboard display system, characterized in that to complement the data rate. The method according to claim 1, The video signal input to the input unit from the serial communication line is composed of video information of 60 frames or less per second. High-definition billboard display system, characterized in that to complement the data rate.

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