KR20070022157A - Burst mode receiver based on charge pump PLL with idle-time loop stabilizer - Google Patents

Abstract

The enhanced burst mode receiver includes a digital phase detector for receiving an input signal. The receiver also compares an input clock phase with a locally generated clock phase and a charge pump that receives pulse signals from the digital phase detector that controls the charge pump, and a loop filter that receives charge values from the charge pump and generates a control signal. And a local clock generator that receives the control signal, generates a recovery clock, and provides the recovery clock to the digital phase detector.

Description

Burst mode receiver based on charge pump PLL with idle-time loop stabilizer

The present invention relates to the processing of signals in a network environment. An implementation of a burst mode receiver for receiving packets in burst mode with possible idle periods between successive receptions. The function of the burst mode receiver associated with the present invention is to lock on the incoming signal and recover the clock and data from the signal. In particular, the present invention relates to the use of the burst mode receiver described above in high speed optical systems (such as 10 Gbps or 40 Gbps), cross-bar switches and all-optical networks. .

Fiber-optic infrastructure is an important element in today's rapidly changing global network. As a result of the new applications, the application of a new solution is required for the exponential growth of data traffic as well as the strong demand for interconnectivity, in particular optical implementations of routers that handle optical packets. There is a need for optical routing solutions. These emerging optical routers must be able to handle terabytes of data arriving from different sources in a burst mode, and multi-layer routing structure based on DWDM optical. To handle burst mode traffic, the optical router must be able to send burst packets to targeted routers and receive burst packets from source routers.

An important component in an optical router is a burst mode receiver (BMR). This component receives packets of fixed size or variable size at high speed in burst mode with possible unknown periods between successive receptions and recovers clock and data from the signal. In general, a clock and data recovery receiver (CDR), which is not locked to an incoming signal, needs a period of active signal before it can extract the correct clock and data from the input signal. Shall be. This period is called the receiver "locking time" or "acquisition time".

In continuous systems, the sender sends packets continuously to the receiver, so the receiver needs a single locking time to lock to the input signal when it first appears. Assuming the signal arrives without interference, it remains locked thereafter. If the transmitter does not have packets to send, the transmitter continues to send a dummy sequence to keep the receiver locked.

In a burst mode system, the transmitter sends a signal in bursts, so at the beginning of each burst of data the receiver needs a locking time to lock on the signal. Since the receiver cannot extract valid clock and data during the locking time, the transmitter starts each burst with a preamble sequence for the locking time. After that, the data itself is sent. Since it is the easiest pattern to lock on, the preamble sequence is used to indicate “101010... Is often used.

In a burst mode system, the preamble sequence maintained during the locking time is the transmission time spent since it does not carry valid data. Therefore, locking time should be minimized as much as possible to realize high performance systems. Burst mode receivers are receivers with much shorter locking times when compared to continuous mode receivers.

Burst mode receivers can be classified into two groups: over sampling clock recovery and non-over sampling clock recovery. Oversampling clock recovery receivers use the concept of sampling each bit of the input signal several times with high speed samplers to detect the transition of samples. The advantage of these receivers is that the locking time can be very short. However, since these receivers need to sample at least four samples per bit, these types of receivers are limited to low speed systems (lower than 1 Gbps). The use of such receivers is preferred in the passive optical networks (PON) standard operating at 622 Mbps. This kind of receivers is very difficult to implement and requires a 40 Gpbs or 160 Gbps sampling rate that may not be possible in today's technology, so in high speed systems such as 10 Gbps or 40 Gbps, this kind of Receivers cannot be used. This method also requires that the receiver and transmitter clocks be close enough to achieve an appropriate lock.

For these high speed networks, non oversampling clock recovery receivers that can reach 10 Gbps and even 40 Gbps line rates are more preferred. Therefore, there is a need to propose a burst mode receiver that has a reduced locking time without increasing noise in the recovery clock and that does not lose synchronization after synchronization is achieved.

According to one embodiment of the invention, a burst mode receiver is disclosed. The receiver includes a digital phase detector for receiving an input signal and a local recovery clock, a charge pump for receiving pulse signals from the digital phase detector for controlling a charge pump, a loop filter for receiving charge values from the charge pump and generating a control signal. And a clock generator that receives the control signal, generates a recovery clock, and provides the recovery clock to a digital phase detector.

The clock generator may also be a voltage controlled oscillator or a direct digital synthesizer. The loop filter may be a resistor and a capacitor in series, the charge pump to provide a charge value to the loop filter in such a way that electrical charge is injected into or removed from the capacitor of the loop filter. Can be configured. The burst mode receiver may include a clock generator for outputting the recovered clock signal, and the digital phase detector may receive the recovered clock signal. The digital phase detector may also be configured to compare the input signal with a local generated clock, wherein the digital phase detector determines whether the locally generated clock is ahead of or behind the input signal. Can be configured to output the charge value on the basis of this.

The burst mode receiver also receives a reference clock source for generating a locally generated clock signal, a second digital phase detector for receiving the locally generated clock signal, and generating the second pulse signals, and receiving the second pulse signals. And a second charge pump providing a second charge value to the loop filter. The receiver is in series with the reference clock source, the second digital phase detector, and the second charge pump, the shut off switch configured to prevent the second charge value from being provided to the loop filter. It may further include. The burst mode receiver may further include a frequency divider that receives the recovery clock and provides a divided frequency recovery clock signal to the second digital phase detector.

According to a further embodiment of the invention, a method of recovering a clock signal at a burst mode receiver is also disclosed. The method comprises: receiving, by a digital phase detector, an input signal, comparing the input signal phase with the locally generated clock phase, and by a charge pump, receiving pulse signals from the digital phase detector to receive the charge. Controlling a pump, receiving a charge value from the charge pump by a loop filter, generating a control signal by the loop filter, and controlling a local clock generator to generate a recovery clock. do.

According to a further embodiment of the invention, a burst mode receiver is disclosed. The receiver comprises: receiving means for receiving an input signal, generating means for generating pulse signals based on the input signal, charge pumping means for pumping charge based on the pulse signals, generating a filtered control signal, and Loop filtering means for receiving charge from the charge pumping means, and control means for controlling the generating means based on the control signal and generating a recovery clock.

In order that the present invention may be more readily understood and immediately practiced, preferred embodiments will be described in conjunction with the following drawings, but such embodiments are for illustrative purposes only and are not intended to limit the invention.

1 illustrates a typical phase locked loop circuit according to a conventional design technique.

2 illustrates an exemplary charge pump based phase locked loop circuit in accordance with an embodiment of the present invention.

3 shows a charge pump based phase locked loop according to an embodiment of the present invention with a pause-time stabilizer for burst mode applications.

4 illustrates a current attenuator / amplifier proposed in accordance with an embodiment of the present invention, which may be used with the burst mode circuit shown in FIG.

5 illustrates a method according to an embodiment of the present invention for achieving synchronization in a burst mode receiver.

The present invention relates to the implementation of a burst mode receiver based on a charge pump PLL approach. Embodiments of the present invention also relate to an idle-cycle loop ballast that avoids loop capacitor discharge problems and can lock quickly even after a long idle period. The idle-period loop ballast further includes a digital phase detector, a charge pump, and a current attenuator / amplifier module.

A conventional phase locked loop (PLL) based receiver, shown in FIG. 1, includes a voltage control oscillator (VCO) 103 or a direct digital synthesizer (DDS), phase, for generating a local clock signal. Detector 101, and loop filter 102. The phase detector 101 compares the local clock signal phase with the input signal phase and generates a phase error signal. This signal is smoothed by the loop filter 102. The output of the loop filter 102 is used to tune the local clock oscillator 103 (VCO or DDS) in the direction of decreasing phase error. When the phase error is small enough, the receiver is locked and the recovery clock samples the input signal (one sample per bit) and extracts the data.

A receiver using a delay lock loop (DLL) is similar to a PLL except that it uses a local clock oscillator fixed at the correct received clock and a phase error signal is used to adjust the phase of the local phase oscillator. .

In both DLL and PLL receivers, the reduction in locking time is limited by the loop's ability to adjust the local clock oscillator fast enough and close to the input signal clock, and these parameters are controlled by the loop filter. Wider loop filter means shorter delay of loop filter and provides faster response. However, the obstacle to widening the loop filter is that more noise is induced into the loop, jitter can be added to the local clock, and the likelihood that the receiver will lose synchronization after locking is achieved.

To overcome this obstacle, the present invention proposes PLL based receivers comprising a charge pump based PLL, according to the embodiment shown in FIG. The charge pump PLL is a digital phase detector 201 that can be implemented from digital logic blocks, a current charge pump 202, a low pass filter 203 that generates a control voltage to a voltage controlled oscillator, and a voltage controlled oscillator 204. ). The digital phase detector 201 may compare the input signal phase with a locally generated clock (output of the VCO) and generate a series of pulses indicating whether the internal clock is ahead or behind the input signal. These pulses drive a charge pump 202 that slowly injects charge into or removes charge from capacitor 203b of the low pass filter. This capacitor 203b maintains a VCO control voltage that sets the operating frequency of the VCO. The fact that such a charge pump based PLL can operate at the highest speed at which a process can create a working flip-flop is an improvement over the present invention over prior art methods. Also, being able to easily implement this embodiment makes this kind of PLL very useful in high speed clock-data recovery devices.

Another advantage of the charge pump PLL is that the process of locking to frequency can be quickly synchronized to the input signal phase, even though it takes a longer time period. This feature makes the charge pump PLL a more suitable approach for implementing burst mode receivers than other approaches. However, a major obstacle to using the charge pump PLL for burst mode receivers is that the loop capacitors will be discharged when no signal is supplied to the loop (during idle time). In this case, when the signal arrives after a long pause, the loop capacitor needs to be recharged before the PLL achieves valid synchronization.

In order to solve the loop stability problem during idle-periods, a further embodiment of the present invention as shown in FIG. 3 is disclosed. This configuration uses two loops, a strong loop that pulls the local signal into the input signal and a weak loop that pulls the local signal into the local reference clock. The strong loop is responsible for locking the local clock source to the input signal when the input signal is available. When the input signal is not available, the charge pump 302 does not generate current pulses, and the weak loop is responsible for locking the local clock source to the local reference clock.

In other embodiments, the strong loop includes a digital phase detector 301 that compares the input signal phase with the voltage controlled oscillator 304 output. Depending on whether the local signal phase is ahead or behind the input signal phase phase, the digital phase detector generates an up command or down command to the charge pump 302. In response to the up and down commands, the charge pump 302 generates positive or negative current pulses that charge or discharge the capacitor 303b in the loop filter 303. This changes the input voltage to VCO 304 which changes the VCO output frequency and phase.

The weak loop includes an optional frequency divider 309 that divides the VCO 304 output into lower frequencies, and the local clock source 310 need not be the same as the output frequency of the frequency divider 309 but the frequency divider. It has a frequency close to the output frequency of 309. Phase detector 305 compares the two signals and issues an up command and a down command to charge pump 306. Output current pulses from the charge pump 306 pass through an optional shut off switch 307. The shut off switch may cause the weak loop to “turn off” in accordance with an external control signal or input signal power detection control. The charge pump output current is optionally attenuated or amplified by the current attenuation circuit 308 before being directed to the loop filter 303 to a desired level.

If shut off switch 307 is not used in the circuit, loop filter 303 accepts current Ip from the strong loop and current Is from the weak loop. In order to avoid interference between the strong loop and the weak loop, the weak loop current Is is preferably smaller than the strong synchronous current Ip. Based on computer simulations and laboratory tests, Ip must be 10 times stronger than Is (Is ~ Ip / 10) to achieve the desired behavior. On the other hand, Is is important to be able to compensate for the leakage current to discharge the capacitor. If the current from the weak loop is much smaller than the leakage current, the capacitor 303b will discharge and the effect of keeping the loop in the correct frequency range will be lost.

4 illustrates a circuit that may be used as a current attenuator or amplifier, shown as component 308 in FIG. 3. The circuit includes two wide-band operational amplifiers 401 and 402 that are cascaded together to implement the desired operation and include four resistors R ₁ -R ₄ .

In accordance with an embodiment of the present invention, a process for recovering a clock signal at a burst mode receiver is shown in FIG. In step 501, the input signal is received by the digital phase detector, and in step 502, pulse signals are generated by the digital phase detector and received by the charge pump. In step 503, the charge pump provides a charge value to the loop filter based on the pulse signals. In step 504, the loop filter provides a control signal to the local clock generator, and in step 505, the digital phase detector compares the locally generated clock phase with the input clock phase. Through this loop, in step 506, a reconstruction signal is generated to allow the receiver to properly process the received signal.

Although the present invention has been described based on the above-described preferred embodiments, it will be apparent to those skilled in the art that various changes, modifications, and other configurations are possible within the scope of the present invention. Accordingly, in order to determine the boundaries and limitations of the present invention, reference should be made to the appended claims.

Claims (26)

A digital phase detector for receiving an incoming signal; A charge pump receiving pulse signals from the digital phase detector controlling a charge pump; A loop filter receiving a charge value from the charge pump and generating a control signal; And And a local clock generator for receiving the control signal, generating a recovered clock, and supplying the recovered clock to the digital phase detector. The method of claim 1, wherein the local clock generator, A burst mode receiver comprising a voltage controlled oscillator. The method of claim 1, wherein the local clock generator, A burst mode receiver comprising a direct digital synthesizer. The method of claim 1, wherein the loop filter, A burst mode receiver comprising a resistor and a capacitor in series. The method of claim 4, wherein the charge pump, And provide a charge value to the loop filter in such a manner that electrical charge is injected into or removed from the capacitor of the loop filter. The method of claim 1, The local clock generator outputs the restored clock signal, and And said digital phase detector receives said recovered clock signal. The method of claim 1, wherein the digital phase detector, And configured to compare the input signal with a local generated clock. The method of claim 7, wherein the digital phase detector, Burst mode receiver configured to output the charge value based on whether the locally generated clock is ahead or behind the input signal. The method of claim 1, A reference clock source for generating a locally generated clock signal; A second digital phase detector for receiving the locally generated clock signal and generating second pulse signals; And And a second charge pump that receives the second pulse signals and provides a second charge value to the loop filter. The method of claim 9, And a shut off switch in series with the reference clock source, the second digital phase detector, and the second charge pump and configured to prevent the second charge value from being provided to the loop filter. Burst mode receiver, characterized in that. The method of claim 9, And a frequency divider for receiving the recovered clock and providing a divided frequency recovered clock signal to the second digital phase detector. A method for recovering a clock signal at a burst mode receiver, comprising: Receiving, by the digital phase detector, an input signal; Receiving pulse signals from the digital phase detector to control a charge pump; Receiving, by a loop filter, a charge value from the charge pump; Generating, by the loop filter, a control signal; And Controlling the digital phase detector via the control signal to generate a reconstructed clock. The method of claim 12, wherein controlling the digital phase detector comprises: Method performed by a voltage controlled oscillator. The method of claim 12, wherein controlling the digital phase detector comprises: A method performed by a direct digital synthesizer. The method of claim 12, The loop filter includes a resistor and a capacitor in series, Receiving a charge value by the loop filter comprises receiving a charge value by the resistor and a capacitor. The method of claim 16, wherein receiving a charge value by the loop filter comprises: Electrical charge is carried out in such a way that it is injected into or removed from the capacitor of the loop filter. The method of claim 12, wherein receiving the input signal by the digital phase detector comprises: Comparing the input signal with a locally generated clock. The method of claim 17, wherein receiving a charge value by the loop filter comprises: Outputting the charge value based on whether the locally generated clock is ahead or behind the input signal. The method of claim 12, Generating, by the reference clock source, a locally generated clock signal; Receiving, by a second digital phase detector, the locally generated clock signal; Generating second pulse signals by the second digital phase detector; Receiving the second pulse signals by a second charge pump; And Providing a second charge value to the loop filter based on the second pulse signals. Receiving means for receiving an input signal; Generating means for generating pulse signals based on the input signal; Charge pumping means for pumping charge based on the pulse signals; Loop filtering means for generating a filtered control signal and receiving charge from said charge pumping means; And And control means for controlling said generating means based on said control signal and generating a recovered clock. The method of claim 20, wherein the loop filtering means, Include resistors and capacitors in series, And the charge pumping means is configured to provide the charge to the resistor and the capacitor. The method of claim 20, wherein the generating means, And a comparison means for comparing the input signal with a locally generated clock. The method of claim 22, And said generating means is configured to generate pulse signals based on whether said locally generated clock is ahead or behind said input signal. The method of claim 20, Generating means for generating a locally generated clock signal; Second generating means for generating second pulse signals based on the locally generated clock signal; And And a second charge pumping means for pumping a second charge value to said loop filtering means based on said second pulse signals. The method of claim 24, Shut off means for shutting off said second charge value in a manner to prevent said second charge value from being provided to said loop filter switch, And said shut-off means is in series with said generating means, said second generating means, and said second charge pumping means. The method of claim 24, And frequency dividing means for dividing the frequency of the received signal, the frequency dividing means being configured to receive the recovered clock and to provide a divided frequency recovered clock signal to the generating means. Mode receiver.

Images