KR20060132147A - Processor of distribute storage structure - Google Patents

Abstract

A processor of a distributed storage structure is provided to increase memory efficiency of an external data bus, and properly distribute use of an internal and external memory. The processor(510) executes an application using the internal and/or external memory(520,200). The internal memory is placed in a device and stores processed data. An external memory interface(530) accesses the external memory connected to the device. A virtual bus master(540) distributes a memory use request of the processor to the internal and external memory at a specific ratio. An internal bus(550) forms a communication path between the processor and the bus master. An internal memory bus forms the communication path among the virtual bus master, the internal memory, and the external memory.

Description

PROCESSOR OF DISTRIBUTE STORAGE STRUCTURE}

1 is a block diagram showing the structure of a processor according to the prior art;

2 is a memory map illustrating a memory addressing structure in a typical processor using internal and external memory.

3 is a graph illustrating a data width usage distribution of an internal bus when the processors of FIG. 1 simultaneously execute the corresponding tasks in the memory map structure of FIG. 2;

4 is a graph illustrating a data width usage distribution of an external bus when the processors of FIG. 1 simultaneously execute the corresponding tasks in the memory map structure of FIG. 2;

5 is a block diagram showing the structure of a processor according to an embodiment of the present invention;

FIG. 6 is a graph illustrating a data width usage distribution of an external bus when the processors of FIG. 5 simultaneously execute the corresponding tasks in the memory map structure of FIG. 2; FIG.

* Explanation of symbols for the main parts of the drawings

200: external memory 500: processor

510: calculator 520: internal memory

530: external memory interface 540: virtual bus master

550: operation unit bus 560: internal memory bus

The present invention relates to a processor that executes one or more tasks simultaneously using an internal memory and an external memory. In particular, it is an invention useful for a media processor with many processing of stream data.

The media processor continuously receives and processes video and / or audio data. As such, the processor that handles the stream data steadily uses the data bandwidth above a certain level. For this purpose, only internal memory may be used, but when the size of the stream data increases, there is a limit in processing data with limited internal memory.

Processing stream data using internal memory has advantages such as improved system performance, power savings, and efficient use of data widths. However, when the size of stream data increases, there is a limit in processing data with limited internal memory. At this time, the external memory is used to allocate insufficient space in the internal memory. If the data width of the external memory is not secured enough, the performance of the system is reduced.

1 illustrates a structure of a general processor having an internal memory interface for accessing an internal memory and an external memory, and FIG. 2 illustrates a general memory map of a general multitasking processor that simultaneously executes one or more tasks.

Task A is a task that uses both internal and external memory to store / process stream data, and task B is assumed to use only external memory. Data width usage of the internal bus and the external bus when the two tasks are processed at the same time is as shown in FIGS. 3 and 4.

By the way, while the data width usage of the internal bus of FIG. 3 is constant, the data width usage of the external bus of FIG. 4 is not evenly distributed on the time axis and has a peak value for a certain period. Therefore, in order for the processor to smoothly handle task A and task B at the same time, an external memory bus must be manufactured to satisfy the performance of the .peak value. The use of additional memory buses to solve this problem leads to an increase in pin count, chip size, and cost.

The present invention has been made to solve the above problems, an object of the present invention is to provide a processor of a distributed storage structure that can increase the use efficiency of the external data bus.

It is another object of the present invention to provide a processor of a distributed storage structure capable of appropriately distributing the use of an internal memory and an external memory.

In order to achieve the above object, the processor of the present invention can access an internal memory and an external memory, supports a multitasking function capable of executing two or more tasks simultaneously, and provides a continuous program address on an application (or task). Characterized in that the stream data having a distributed in the internal memory and the external memory. In the distributed storage method, the internal granule data value, which is the amount of data stored in the internal memory at one time, and the external granule data value, which is the amount of data stored in the external memory at one time, are set, and the stream data is changed by the corresponding granule data value. Cut and store alternately in internal memory and external memory. Therefore, the processor of the distributed storage structure of the present invention is characterized by including a virtual bus master for performing alternating storage of the memory and remapping of addresses at read / write.

Before describing the present invention, the concept of granules will be clarified. When performing distributed storage according to the present invention, the storage operation to the internal memory and the storage operation to the external memory are alternated, so that the granule is used to store the data stored at the time of one storage during the alternation to the internal memory or the external memory. It means a block. The internal memory and the external memory may have alternating frequency and storage capacity, and thus the internal granule size and the external granule size may be different.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, terms or words used in the specification and claims should not be construed as having a conventional or dictionary meaning, and the inventors should properly explain the concept of terms in order to best explain their own invention. Based on the principle that it can be defined, it should be interpreted as meaning and concept corresponding to the technical idea of the present invention. Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiment of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.

(Example)

The processor of the distributed storage structure of this embodiment as shown in FIG. 5 includes: an operation unit 510 for executing an application (one or more tasks) using an external memory and / or an internal memory; An internal memory 520 positioned inside the device and configured to store data in operation; An external memory interface 530 for accessing an external memory 200 connected to the outside of the device; A virtual bus master 540 for receiving the memory use request of the operation unit 510 and distributing it to the internal memory 520 and the external memory 200 at a predetermined ratio; An operation unit bus 550 for forming a communication path between the operation unit and the virtual bus master; And an internal memory bus 560 forming a communication path between the virtual bus master 540, the internal memory 520, and the external memory interface 530.

This embodiment is developed by designing a processor of a distributed storage structure according to the spirit of the present invention by minimizing deformation in the design of a processor using a conventional internal / external memory as shown in FIG. The goal is to minimize manufacturing costs. In addition, in this embodiment, the inner granules and the outer granules are alternately stored one by one in the manner of "inner granule-outer granule-inner granule-outer granule".

The internal memory 520 and the external memory interface 530 have almost the same structure as in the prior art, and even use a hardware block IP used by other bus master components (virtual bus master in this embodiment) to call. You can also use it as it is. The IP refers to a semiconductor layout design IP used in designing / manufacturing a System on Chip (SoC) chip.

The operation unit 510 also has a structure similar to that of the operation unit, which is a bus master of the related art. However, when performing access to the memory, the operation unit 510 does not distinguish between the external memory 200 and the internal memory 520 and is generally unified. Recognized as one virtual address space, it performs as access to a single virtual memory.

In the prior art illustrated in FIG. 1, the computing unit and the internal memory / external memory interface form a direct communication channel through an internal bus. However, in the present exemplary embodiment, the computing unit bus 550 connected to the computing unit 510 and the internal communication channel are internally connected. The memory bus 560 connected to the memory 520 and the external memory interface 530 is divided and implemented, and the virtual bus master 540 relays data communication between the operation unit bus 550 and the memory bus 560. Is implemented.

The virtual bus master 540 constituting the features of the present invention performs the following functions.

The virtual bus master 540 of the present embodiment is characterized by having an operation of distributed storage of stream data. However, according to the purpose, the virtual bus master 540 may be implemented to select the data storage mode from the distributed storage mode and the simple storage mode according to the conventional method. In this case, the function of selecting the storage mode must also be performed.

In addition, the virtual bus master 540 sets granule sizes of internal and external memories. The granule size of the internal memory is set between the minimum access value of the internal memory, which is the minimum value, and the maximum transmission value according to the weight cycle of the memory bus 560, which is the maximum value. The granule size of the external memory is set between an access minimum unit value of the external memory which is the minimum value and a maximum transmission value according to the weight cycle of the memory bus 560 which is the maximum value.

In the embodiment of the simplest structure, the storage mode selection or the granule size setting may be fixed to one value and may not have meaning, and may be implemented according to a set of logic values applied to an external pin for setting. It may be implemented to be performed according to the value recorded in the processor element internal register.

In order to distribute and store stream data having consecutive program addresses in the internal memory and the external memory, the virtual bus master 540 stores the program address for the stream data that is requested to be accessed, the physical address of the actual internal memory and the external memory. You must perform address remapping to change to an address.

The address remapping process upon storage of data includes selecting a storage location of the first granule for the stream data; Dividing the stream data into alternating inner granules and outer granule units; Storing the stream data divided by the internal granule unit in an internal memory; Storing stream data divided by the external granule unit in an external memory; And creating and recording a remapping index.

When storing the data, address remapping should perform a function of receiving a program address, converting it into a physical address of an internal / external memory, and outputting the same.

,

,

(RAi: actual physical address of internal memory

RAe: actual physical address of external memory

PA: Program Address

IS: Internal Memory Granule Size

ES: External Memory Granule Size

Of: addressing offset value)

The remapping index indicates a structure in which corresponding stream data is distributed and stored when data is read. The remapping index indicates a corresponding program address space (the corresponding size of the total stream data) and identification symbols of distributed and stored granules. The values that are known are recorded.

The address remapping process when reading data includes: receiving a program address space to be read; Retrieving a start address of the address space from a remapping index to find a corresponding granule identifier and an address within the granule; Retrieving the end address of the address space from a remapping index to find a corresponding granule identifier and an address within the granule; Reading the data from the corresponding granules from the start address to the end address.

In the read address remapping process, the remapping is performed according to a predetermined conversion function. Since the data remapping can be inferred from the description of the address remapping process, detailed description thereof will be omitted.

The virtual bus master 540 may be provided with a granule buffer for the operation. That is, when burst lead / write access occurs, the internal granule buffer and / or adjustable external granule size corresponds to the maximum value of the adjustable internal granule size for efficient interface with internal and / or external memory. It may be provided with an external granule buffer corresponding to the maximum value of. In this case, the virtual bus master 540 temporarily stores the access result from the memory in the granule buffer and transfers the result of the access to the bus master through the virtual bus master in the order of access.

On the other hand, in the case of performing an application using only internal memory, the virtual bus master 540 requests access of a memory area of the same type as a conventional internal memory access request so that all access operations through the conventional internal memory interface can be implemented. Is received from the bus master 510 and transferred to the internal memory 520, and symmetrically, the virtual bus master 540 receives the result of the internal memory access and transfers the result to the bus master 510.

In addition, even when performing alternating accesses to the inside and the outside according to the spirit of the present invention, if the burst size does not exceed the granule size of the internal memory, of course, the same as the single transfer access. On the other hand, if the burst size exceeds the granule size of the internal memory, the excess access is transferred to the external memory interface. The access result is temporarily stored in the granule buffer in memory and transferred to the bus master through the virtual bus master in the order of access.

Similarly, if storage first occurs to the external memory granules first, then the same as single transfer access if the burst size does not exceed the granule size of the external memory. On the other hand, if the burst size exceeds the granule size of the external memory, the excess access is transferred to the external memory interface.

Although the present invention has been described by way of limited embodiments and drawings, the present invention is not limited thereto, and the technical spirit of the present invention and the claims to be described below by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible within the scope of equivalents.

For example, in the above description, it has been described that distributed storage is performed on stream data. However, depending on the implementation, the present invention may be applied to a storage device that stores program code data or general data. This is because if the address corresponds to data stored in a contiguous space, there is a real advantage to perform distributed storage according to the spirit of the present invention.

By implementing the processor of the distributed storage structure according to the present invention, by appropriately distributing the use of the internal memory and the external memory, it is possible to increase the efficiency of using the external data bus of the processor.

Claims (5)

An operation unit for executing an application using an external memory and / or an internal memory; An internal memory located inside the device for storing data in operation; An external memory interface for accessing an external memory connected to the outside of the device; A virtual bus master configured to receive a memory use request of the calculator and to distribute the memory to the internal memory and the external memory at a predetermined ratio; An operation unit bus forming a communication path between the operation unit and the virtual bus master; And An internal memory bus forming a communication path between the virtual bus master and the internal memory and an external memory interface Processor of a distributed storage structure comprising a. The method of claim 1, wherein the virtual bus master, A processor in a distributed storage structure in which an internal granule value indicating an amount of data accessing internal memory at one time and an external granule value indicating an amount of data accessing external memory at one time are recorded. The method of claim 2, wherein the virtual bus master, And storing the internal granule 1 unit data in an internal memory, and storing the external granule 1 unit data in an external memory. The method of claim 2, wherein the virtual bus master, An internal granule buffer for storing at least one unit of internal granule data; And External granule buffer for storing at least 1 unit of external granule data Processor of a distributed storage structure comprising a. The method according to any one of claims 2 to 4, The virtual bus master is a processor of a distributed storage structure that performs address remapping as in the following equation.

,

(RAi: actual physical address of internal memory RAe: actual physical address of external memory PA: Program Address IS: Internal Memory Granule Size ES: External Memory Granule Size Of: addressing offset value)

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