KR20060122530A - Direct memory access control apparatus for transmitting burst of image data that is different with sampling and the burst transmitting method thereof - Google Patents

Abstract

An image processing apparatus capable of transmitting the burst of image data with different sampling extraction ratios and a burst transmitting method thereof are provided to differently make the structure of data without changing the size of the burst. Image data are stored in a memory(420). The memory is divided into a Y memory area and a Cb/Cr memory area. Y is stored in the Y memory area and Cb and Cr are alternately and sequentially stored in the Cb/Cr memory area. A DMA(Direct Memory Access) control device(430) stores the Y outputted by the line unit through an image data pre-processor(410) and an image decoder(450) in the Y memory area of the memory and the Cb and Cr in the Cb/Cr memory area. The DMA control device reads the components of Y, Cb and Cr in the image data with any one of the sample extraction ratios of Y:Cb:Cr=4:2:2 or 4:1:1 and transmits the read sample extraction ratio to an image compressor(440).

Description

Direct memory access control apparatus for transmitting burst of image data that is different with sampling and the burst transmitting method

1 is a block diagram of a conventional image processing apparatus;

2 shows an embodiment of a conventional image data format;

3 is a diagram showing a data structure of a conventional memory area;

4 is a block diagram of an image processing apparatus according to an embodiment of the present invention;

5 is a view showing an embodiment of an image data format by the image processing apparatus of the present invention;

6 is a detailed block diagram of a DMA control apparatus according to an embodiment of the present invention;

7 is a diagram showing the data configuration of a memory area by the DMA control apparatus of the present invention; and

8 is a flowchart provided to explain a burst transmission method of an image processing apparatus according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

410: Image data preprocessor 420: Memory

430: DMA controller 440: image compressor

450: image decoder

The present invention relates to an image processing apparatus and a burst transmission method, and more particularly, to an image processing apparatus and a burst transmission method for transmitting image data having different sampling ratios in accordance with a maximum burst size.

The image processing apparatus is an apparatus for processing an image input from the outside. Specifically, the image processing apparatus compresses image data corresponding to an image input from an external input / output device into a Joint Photographic Experts Group (JPEG) to directly access memory. Or image data stored in the memory at the request of an external input / output device through the DMA operation.

The DMA operation is an operation in which data transfer is directly performed between a memory connected to a bus and a channel without being controlled by a CPU through a central processing unit (CPU), and is performed by a DMA controller provided in an image processing apparatus. The DMA controller transfers data directly between the memory and the channel via the bus.

1 is a block diagram of a conventional image processing apparatus.

Referring to FIG. 1, a conventional image processing apparatus includes an image data preprocessor 110, a memory 120, a DMA controller 130, an image compressor 140, and an image decoder 150.

The image data preprocessor 110 sets the luminance component Y, the chrominance component Cb, Cr of the image data Y: Cb: Cr = 4: 2: 2: and Y: Cb. : Cr = 4: 1: The sampling ratio of any one of them is output. At this time, the image data preprocessor 110 is Y, Cb, Cr Raster output in line units of sequence.

The DMA controller 130 stores image data output in units of lines in an area of the memory 120 corresponding to each component area. Then, the DMA controller 130 selects the image data components Y, Cb, and Cr stored in the memory 120 from Y: Cb: Cr = 4: 2: 2 and Y: Cb. : Cr = 4: 1: 1 The reading ratio of any one of the 8 pixel * 8 pixel block at a sampling ratio is transmitted to the image compressor 140.

Specifically, when the bus width is 32 bits and a sampling ratio of Y: Cb: Cr = 4: 2: 2 is used, the DMA controller 130 may store data of 16 pixels (4 words) in which Y is an image compressor ( Burst is transmitted to 140, and Cb and Cr respectively transmit 8 pixels (2 words) of data to the image compressor 140.

The image compressor 140 sequentially encodes and compresses the image data components transmitted using Discrete Cosine Transform (DCT), quantization, and Huffman code into binary data. Compressed image data is stored in the memory 420.

The image decoder 150 performs the reverse process of the operation performed by the image compressor 140 to convert the image data into Y: Cb: Cr = 4: 2: 2 and Y: Cb. : Cr = 4: 1: Restores one of the formats.

The DMA control unit 130 is Y: Cb: Cr = 4: 2: 2: and Y: Cb : Cr = 4: 1: 1 Each component data restored in one of the formats is stored in the memory 120.

2 is a diagram illustrating an embodiment of a conventional image data format. As shown in Fig. 2, the image data is in units of 8 * 8 blocks for each component, and Y: Cb. : Cr = 4: 2: 2. Here, Y consists of two blocks Y1 and Y2. In other words, Y is an 8 * 8 block, Y2 is an 8 * 8 block, a total of 16 * 8 blocks, Cb per 2 pixels, and Cr is an 8 * 8 block.

3 is a diagram illustrating a data structure of a conventional memory area. Referring to FIG. 3, the data structure of each component region of the memory 120 illustrated in FIG. 1 is illustrated. Y shown in FIG. 2: Cb : Cr = 4: 2: A storage format in the case of 2: Y, Cb, and Cr each have a separate memory area.

Y is stored in n * l structures in 8 * 8 blocks, and Cb and Cr are stored in n * l structures in 8 * 8 blocks. At this time, the data of more than 8 pixels, that is, 2 words, has a different address of the memory area.

Therefore, since Cb _and Cr are transferred to only one bus occupancy up to 2 word bursts of half of Y, the time required to request and prepare for bus usage is more than the actual data transfer time, that is, the bus occupation time. May occur.

In addition, since the address of the memory area beyond 2 words is different, two addresses are generated to transfer Y 4 words, one to transfer Cb 2 words, and one to transfer Cr 2 words. You must perform an address generation operation. This is not possible with a burst operation, which can result in a slowdown resulting in performance degradation.

If the burst length of Cb and Cr is to be increased and transmitted, temporary storage space of Cb and Cr is required. Therefore, the structure and operation are complicated because additional memory and address generation for Cb and Cr stored in the added memory are required. Problems may arise.

Accordingly, an object of the present invention is to provide an image processing apparatus capable of burst transmission of image data having different sampling ratios by changing the data structure without changing the burst size of each component even when the sampling ratio of each component constituting the image data is different; The burst transmission method is provided.

An image processing apparatus according to the present invention for achieving the above object is a memory that stores the luminance component data in the luminance component region, the first and second color difference component data in the color difference component region, and the luminance component data Store in the luminance component region and intersect the first and second chrominance components in the chrominance component region, and store the luminance component data and the first and second chrominance component data in predetermined units of n pixels * m pixels, respectively. And a DMA controller for reading from the memory.

The DMA controller further includes an address generator for generating an address for a memory of the luminance component data, the first and second color difference component data in units of n pixels, and the luminance component data and the first and second color differences. It is preferable to include at least one FIFO for generating component data in a predetermined unit of the n pixel * m pixel.

The luminance component data is Y, the first chrominance component data is Cb, the second chrominance component data is Cr, and a predetermined unit of the n pixels * m pixels is 16 pixels * 8 pixel blocks. .

On the other hand, the burst transmission method of the image processing apparatus of the present invention, generating an address for the memory of the luminance component data, the first and second color difference component data, the memory component data to correspond to the generated address; Storing the first and second color difference components in the color difference component region of the memory, and storing the first and second color difference components in the luminance component region of the memory; Reading from the memory in predetermined units of n pixels * m pixels, respectively.

The luminance component data is Y, the first chrominance component data is Cb, the second chrominance component data is Cr, and a predetermined unit of the n pixels * m pixels is 16 pixels * 8 pixel blocks. .

Hereinafter, with reference to the drawings will be described in detail the present invention.

4 is a block diagram of an image processing apparatus according to an embodiment of the present invention.

According to the image processing apparatus of the present invention, even when the sampling ratios of the respective component data, that is, Y, Cb, and Cr, which constitute the image data corresponding to the image are different, sampling is performed by changing the data structure without changing the burst size of each component data. Burst transmission of image data with different ratios is possible.

Referring to FIG. 4, the image processing apparatus includes an image data preprocessor 410, a memory 420, a DMA controller 430, an image compressor 440, and an image decoder 450.

The image data preprocessor 410, the image compressor 440, and the image decoder 450 may be connected to the image data preprocessor 110, the image compressor 140, and the image decoder 150 illustrated in FIG. 1. Since the same operation is performed, the description of the operation will be omitted.

Image data is stored in the memory 420. In detail, the memory 420 is divided into a Y memory area and a Cb / Cr memory area, where Y is stored in the Y memory area and Cb and Cr are crossed and sequentially stored in the Cb / Cr memory area.

The DMA controller 430 stores Y output in the unit of lines by the image data preprocessor 410 and the image decoder 450 in the Y memory area of the memory 420, and crosses Cb and Cr, respectively. The memory 420 is stored in the Cb / Cr memory area of the memory 420.

The DMA controller 430 then converts the image data components Y, Cb, and Cr stored in the memory 420 into Y: Cb: Cr = 4: 2: 2 and Y: Cb. The read ratio of any one of: Cr = 4: 1: 1 is read in units of 16 pixels * 8 pixels and transferred to the image compressor 440.

Specifically, when the bus width is 32 bits and a sampling ratio of Y: Cb: Cr = 4: 2: 2 is used, the DMA controller 430 is configured to store data of 16 pixels (4 words) in Y. Burst transfer to 440, and similarly, Cb and Cr burst transfer data of 16 pixels (4 words) to the image compressor 440, each of 8 pixels (2 words).

5 is a diagram showing an embodiment of an image data format by the image processing apparatus of the present invention.

As shown in Fig. 5, the image data is in units of 8 * 8 blocks for each component, and Y: Cb. : Cr = 4: 2: 2. According to the present invention, Y is 8 * 8 blocks, Y2 8 * 8 blocks, 16 * 8 blocks in total, Cb per 2 pixels, and Cr is 8 * 8 blocks, 16 * 8 blocks, respectively, to obtain 2 pixels of data. Has the form

Due to this, Y: Cb The format of: Cr = 4: 2: 2 remains unchanged, and only the data structures of Cb and Cr change. As the data structure changes, the burst length of each of Cb and Cr does not change, but the total burst length becomes equal to Y.

Therefore, the DMA controller 430 transmits Y1 for 2 words, Y2 for 2 words, a total of 4 words and 8 lines, that is, 16 * 8 blocks, Cb for 2 words, Cr for 2 words, and 4 words for 8 lines. That is, it becomes possible to burst transfer a 16 * 8 block.

6 is a detailed block diagram of a DMA control apparatus according to an embodiment of the present invention.

Referring to FIG. 6, the DMA controller 430 includes a controller 432, an address generator 434, a FIFO 436, a 16 * 8 FIFO 438, and a 16 * 8 FIFO 438-1. do.

The address generator 434 generates an address of the memory 420 in units of 16 pixels, that is, 4 words, under the control of the controller 432. Specifically, the address generator 434 generates the address of the Y memory area for storing / reading Y 4 words, and the Cb / Cr memory area for storing / reading Cb 2 word, Cr 2 word, and 4 words in total. Create an address.

The FIFO (First In First Out) 436 inputs and outputs image data under the control of the controller 432. The 16 * 8 FIFOs 438 and 438-1 block 16 * 8 blocks of Y, Cb, and Cr input line by line from the image preprocessor 410 or the image decoder 450 under the control of the controller 432. Input and output in units.

Fig. 7 is a diagram showing the data structure of the memory area by the DMA control apparatus of the present invention.

As shown in FIG. 7, a data structure stored in a memory region for each component of the memory 420 illustrated in FIG. 4 is illustrated. Y shown in Figure 5: Cb A storage format in the case of a format of Cr = 4: 2: 2, where Y, Cb, and Cr are designated as Y memory regions and Cb / Cr memory regions, respectively.

Y is stored in an n * l structure in 8 * 8 block units, and Cb and Cr intersect in 8 * 8 block units and are sequentially stored to have the same n * l structure as Y.

At this time, the data of more than 16 pixels, that is, 4 words has a different address of the memory area. For this reason, the address generator 434 performs only one address generation of the memory area for Y 4 words, one address generation of the memory areas for Cb and Cr 4 words, and a total of two address generations in order to store / read image data. Just do it.

8 is a flowchart provided to explain a burst transmission method of an image processing apparatus according to an embodiment of the present invention.

Referring to FIG. 8, the image data preprocessor 410 or the image decoder 450 outputs image data in units of lines (S800).

The DMA controller 430 generates an address of a memory for the output image data (S810). The address generator provided in the DMA controller 430 generates an image data in units of 16 pixels, that is, 4 words.

The DMA controller 430 stores the image data output to correspond to the generated memory address in the memory 420 (S820). At this time, the DMA controller 430 stores the luminance component Y of the output image data in the Y region of the memory 420 according to the address generated by the address generator 434 in units of 16 pixels, that is, 4 words, and the color difference. The components Cb and Cr cross each 8 pixels, and are sequentially stored in the Cb / Cr region of the memory 420 according to the address generated by the address generator 434 in units of 16 pixels in total.

The DMA controller 430 determines whether an image data request has been input (S830).

The DMA controller 430 reads the stored image data in units of 16 * 8 blocks (S840). Specifically, the sample presentation ratio is Y: Cb In the case of a format of Cr = 4: 2: 2, the DMA controller 430 converts 4 words of Y stored in the Y area of the memory 420 corresponding to the address generated by the address generator 434 in units of 4 words. 8 lines each, or 16 * 8 blocks. The DMA controller 430 is a total of 4 words, 8 lines of Cb and Cr stored in the Cb / Cr region of the memory 420 corresponding to the address generated by the address generator 434 in units of 4 words. , Output as 16 * 8 block.

Y: Cb In the case of a format of Cr = 4: 1: 1, the DMA controller 430 uses 16 words stored in the Y area of the memory 420 corresponding to the address generated by the address generator 434 in units of 4 words. 4 blocks are output as 8 blocks. The DMA controller 430 outputs a block of 16 * 8 blocks of Cb and Cr stored in the Cb / Cr region of the memory 420 corresponding to the address generated by the address generator 434 in units of 4 words. .

As described above, according to the present invention, the burst length is increased according to the structure change of the data without changing the burst length of each component data constituting the image data, thereby reducing the time consumed by the bus occupancy and improving performance. It also simplifies address generation because there is no need to change the address of the memory area beyond 8 pixels and no additional memory is required.

In addition, although the preferred embodiment of the present invention has been shown and described above, the present invention is not limited to the specific embodiments described above, but the technical field to which the invention belongs without departing from the spirit of the invention claimed in the claims. Of course, various modifications can be made by those skilled in the art, and these modifications should not be understood from the technical spirit or the prospect of the present invention.

Claims (5)

A memory for storing luminance component data in the luminance component region and storing first and second color difference component data in the chrominance component region; And The luminance component data is stored in the luminance component region, the first and second color difference components are stored in the color difference component region, and the luminance component data and the first and second color difference component data are each n pixels *. and a DMA controller for reading from the memory in predetermined units of m pixels. The method of claim 1, DMA controller, An address generator for generating an address for a memory of the luminance component data and the first and second color difference component data in units of n pixels; And And at least one FIFO for generating the luminance component data and the first and second color difference component data in a predetermined unit of n pixels * m pixels. The method of claim 1, The luminance component data is Y, the first color difference component data is Cb, the second color difference component data is Cr, The predetermined unit of the n pixel * m pixel is 16 pixels * 8 pixel block unit. Generating an address for a memory of the luminance component data and the first and second chrominance component data; Storing the luminance component data in the luminance component region of the memory so as to correspond to the generated address, and storing the first and second color difference components in the color difference component region of the memory; And And reading out the luminance component data and the first and second chrominance component data from the memory in predetermined units of n pixels * m pixels, respectively, when a data output request is input. Burst transmission method. The method of claim 4, wherein The luminance component data is Y, the first color difference component data is Cb, the second color difference component data is Cr, The predetermined unit of the n pixel * m pixel is a 16 pixel * 8 pixel block unit burst transmission method of the image processing apparatus.

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