KR20060109281A - Test method of lsi - Google Patents

Abstract

A method of testing an LSI(Large Scale Integration) is provided to reduce error rate of a test result by comparing values of a scan flip-flop before and after a signal change in order to discriminate a defective LSI. Scan flip-flops are formed at input and output portions of an LSI, which includes a combinational circuit. Configuration information of the combinational circuit and start and end scan flip-flops are designated. A signal value of the start scan flip-flop is generated as an initialized test pattern. A signal, which is obtained by inputting a post-change value to the end scan flip-flop, is generated as a first monitoring test pattern. A signal, which is obtained by inputting a pre-change value to the end scan flip-flop, is generated as a second monitoring test pattern. A first delay error test pattern is generated based on the first monitoring test pattern. A second delay error test pattern is generated based on the second monitoring test pattern. It is determined that the LSI normal, when no delay error is detected during test processes using the first and second delay error test patterns.

Description

Test method of LSI {TEST METHOD OF LSI}

1 is a flowchart of a delay test method of an LSI showing an embodiment of the present invention.

2 is a schematic configuration diagram of an LSI having a scan test function.

3 is a signal waveform diagram illustrating operation of a conventional delay test in the LSI of FIG. 2.

4 is an explanatory diagram illustrating a configuration of a delay test of the LSI of FIG. 2.

FIG. 5 is a flowchart showing a conventional LSI delay test method for detecting delay failure using the configuration of the delay test shown in FIG. 4.

Fig. 6 is a signal waveform diagram showing the operation of the delay test in the embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings *

S1, S2: Setting process for test pattern generator

S3: Generation process of initialization test pattern

S4, S4A: Generation process of observation test pattern

S5, S5A: Generation processing for delayed failure test pattern

S6, S7: First test process of LSI by scan test apparatus

S9, S10: second test process of LSI by scan test apparatus

S8, S11: Judgment processing of test results

Patent Document 1 Japanese Patent Application Laid-Open No. 5-119122

The present invention relates to a test method for detecting a delay failure in a large scale integration (LSI) having a scan test function.

2 is a schematic configuration diagram of an LSI having a scan test function.

The LSI includes a combination circuit 1B to be tested and a combination circuit 1A in front of it, and scan flip-flops (hereinafter referred to as "FF" and scan flip-flops) between these combination circuits 1A and 1B. "S-FF" shall mean; to configure the scan chain by _{2B 1, 2B 2, ···,} 2B m) as junction boxes and their _{S-FF (2B 1 ~2B m} ) together.

The S-FF is composed of a selector for selecting a signal from the preceding combination circuit or a scan input signal by the scan permission signal SE, and an FF for outputting the signal selected by the selector while maintaining the timing of the clock signal.

Combining signals output in parallel from the circuit (1A), each of S-FF is given to a first input of the selector _{(2B 1, 2B 2, ···} , 2B m), S-FF (2B 1 ~2B these _The signal output from each FF of _m ) is given in parallel to the input side of the combination circuit 1B. The output side of each FF of S-FF (2B ₁ , 2B ₂ ,..., 2B _{m -1} ) is respectively selected from each selector of S-FF (2B ₂ , 2B ₃ , ..., 2B _m ). It is connected to the 2nd input. The second input of the selector of S-FF 2B ₁ is connected to scan input terminal 3B, and the output side of FF of S-FF 2B _m is connected to scan output terminal 4B.

On the other hand, a signal is given to the input side of the combination circuit 1A in parallel from the S-FFs 2A ₁ , 2A ₂ ,..., 2A _k constituting the scan chain. The second input of the selector of the S-FF 2A ₁ is connected to the scan input terminal 3A, and the output side of the FF of the S-FF 2A _k is connected to the scan output terminal 4A.

Then, combination circuit (1B), the output-side S-FF constituting the scan chain, like the _{(2C 1, 2C 2, ···} , 2C n) is connected, a second selector of the S-FF (2C ₁₎ The input is connected to the scan input terminal 3C, and the output side of the FF of S-FF (2C _n ) is connected to the scan output terminal 4C, respectively. The clock signal CLK supplied from the clock terminal 5 is supplied to the clock terminal of the FF of each S-FF via a clock supply path, and the scan permission signal SE supplied from the terminal 6 is supplied to each S-FF. It is given to the control terminal of the selector.

3 is a signal waveform diagram illustrating operation of a conventional delay test in the LSI of FIG. 2.

Here, the number of input signals and output signals of the combination circuits 1A and 1B is 4, respectively, and test data is supplied to the input side of the combination circuit 1B to be tested, and then a signal of the logical operation result is output to the output side. The following describes a case of testing the delay time until. The clock signal CLK supplied from the clock terminal 5 is delayed by the time α and transmitted to each of the S-FFs 2B as the clock signal CKB, and delayed by the time β to be the respective S signals as the clock signal CKC. It is assumed to be passed to -FF (2C).

First, the scan permission signal SE is set to "H" to switch the selectors of all the S-FFs to the second input side. As a result, each FF of the S-FFs 2A _{1 to} 2A ₄ is cascade-connected to form a shift register from the scan input terminal 3A to the scan output terminal 4A. The signals output from the respective FFs of the S-FFs 2A _{1 to} 2A ₄ are given in parallel to the combination circuit 1A. Similarly, each FF of the S-FFs 2B _{1 to} 2B ₄ is cascaded to form a shift register from the scan input terminal 3B to the scan output terminal 4B, and the S-FF (2B _{1 to} 2B ₄ ) is configured. The signals output from the respective FF's are given in parallel to the combination circuit 1B.

At time t1 in FIG. 3, the scan input signals SIA and SIB to the scan input terminals 3A and 3B are respectively "a4" and "b4" according to predetermined test data TDA and TDB. " a4 "and " b4 " are set to " H " or " L " to give the clock signal CLK in pulse form from the clock terminal 5; As a result, data "a4" and "b4" are input to the S-FFs 2A ₁ and 2B ₁ after the propagation delay in each clock supply path.

Hereinafter, at time t2, t3, and t4, the scan input signal SIA ("a3", "a2", "a1") is given in turn from the scan input terminal 3A and the S-FF (2A) in accordance with the clock signal CLK. _{1 to} 2A ₄ ) in order. Further, scan input signals SIB (" b3 "," b2 "," b1 ") are given in turn from the scan input terminal 3B, and are sequentially shifted to S-FF (2B _{1 to} 2B ₄ ). By the above scan shift operation, the test data TDA; "a1", "a2", "a3", "a4" are held in each FF of the S-FFs 2A _{1 to} 2A ₄ , and the combined circuit 1A is maintained. ) In parallel. The test data TDB is held in each FF of the S-FFs 2B _{1 to} 2B ₄ , and the test data TDB is held in parallel to the combination circuit 1B. The combination circuit 1A performs logic processing based on the test data TDA, and after a predetermined processing time, the resultant signal RDA is output in parallel as an "initialization test pattern". In addition, the combination circuit 1B performs logic processing based on the test data TDB, and the resultant signal RDB1 is output in parallel after the predetermined processing time D. FIG.

At time t5, the scan permission signal SE of the terminal 5 is set to " L " so that the selectors of all the S-FFs are switched to the first input side. This is given to the input side of the FF of the signal _{S-FF (2B 1 ~2B 4} ) outputted from the combination circuit (1A). However, at this time t5, since the clock signal CLK is not given to the clock terminal 5, the contents of the FF of the S-FFs 2A _{1 to} 2A ₄ do not change.

At time t6, the clock signal CLK for the latch (firing) is supplied from the clock terminal 5. Since the clock signal CLK is delayed by the time α and is given to the S-FF 2B _{1 to} 2B ₄ as the clock signal CKB, the signal RDA output from the combination circuit 1A at this point is S-. since FF (2B ₁ ~2B ₄₎ is input to the FF, given substantially simultaneously to a combination circuit (1B) (slightly different from the clock to supply to each _{S-FF (2B 1 ~2B 4} ), the operating time is exactly the same Not). In the combining circuit 1B, logic processing is performed based on the new signal RDA, and after a predetermined processing time D, a signal RDB2 of the new processing result is generated to generate the S-FF (2C _{1 to} 2C ₄ ). It is output to the first input of the selector. In addition, the signal output from the combination circuit 1B during the processing time D becomes negative.

Then, at time t7 when the test delay time T set in advance from time t6, the clock terminal 5 is supplied with a capture (input) clock signal CLK. Since the clock signal CLK is delayed by the time β and is given to the S-FF 2C _{1 to} 2C ₄ as the clock signal CKC, the combination circuit 1B is supplied to the S-FF 2C _{1 to} 2C ₄ at this point. Signal RDB2 (" c1 "," c2 "," c3 "," c4 ") is input. Thus, the scan output signal SOC output from the scan output terminal 4C becomes "c4".

At time t8, the scan permission signal SE returns to " H " and the selectors of all the S-FFs are switched to the second input side, and the scan shift operation state is brought back.

After the time β from the rise of each clock signal CLK at the times t9 to t12, the contents of the FF of the S-FF (2C _{1 to} 2C ₄ ) are sequentially shifted, and the scan output signal SOC from the scan output terminal 4C. Are output in series.

Therefore, the logic processing delay time D of the combination circuit 1B can be tested by checking the scan output signal SOC. That is, if the scan output signal SOC matches the predetermined value (that is, the "test pattern for observation") based on the input data RDA of the combination circuit 1B and the logic circuit conditions, the following equation (1) is established.

α + D <β + T (1)

If the scan output signal SOC does not coincide with the predetermined value, the equation (1) above does not hold, and for example, it is possible to detect that the processing time D is increasing due to manufacturing failure or the like.

4 is an explanatory diagram illustrating a configuration of a delay test of the LSI of FIG. 2.

First, the logic circuit information of the LSI combination circuit to be tested is input to a test pattern generator (for example, a computer having a program for generating test pattern data) for the delay test, and the start point of the test target circuit ( In this case, the S-FF 2B on the input side of the combining circuit 1B and the end point (in this case, the S-FF 2C on the output side of the combining circuit 1B) are specified.

As a result, a test pattern indicating how the signals CLK, SE, SIA, SIB, and SOC of the terminals 5, 6, 3A, 3B, and 4C of the LSI under test change over time by the test pattern generator. Data is created.

Next, the generated test pattern data is read and recorded in the scan test apparatus. The scan test apparatus associates the time of the test pattern data with an address, and stores a memory (RAM) for storing the state (1 or 0) of signals CLK, SE, SIA, SIB, SOC at each address, and read timing setting. A clock generator OSC for generating the clock signal CK for use, an address counter for counting the clock signal CK to generate an address signal ADR for the memory, and a comparison circuit CMP. Then, data sequentially read out from the memory in accordance with the address signal ADR is given as the signals CLK, SE, SIA, and SIB to the terminals 5, 6, 3A, and 3B to which the LSI to be tested is corresponding.

On the other hand, the signal SOC read out from the memory is applied to one input terminal of the comparison circuit, and the scan output signal SOC from the scan output terminal 4C of the LSI, which is the test target, which is given to the other input terminal of the comparison circuit. The result of comparison between these signals SOC is output.

FIG. 5 is a flowchart showing a delay test method of a conventional LSI for detecting delay failure by using the configuration of the delay test of FIG. 4.

In step S1 of Fig. 5, the configuration information of logic circuits such as the combination circuits 1A, 1B, ... in the LSI to be tested is set in the test pattern generator.

In step S2, S-FF of the start point and the end point of the circuit under test is specified. This completes the setting for the test pattern generator.

In step S3, the test pattern generating device generates a signal value, i.e., an initialization test pattern, to which a signal change is transmitted from S-FF at the start point to S-FF at the end point.

In step S4, a signal value, i.e., a test pattern for observation, on the premise of inputting the signal after the signal change is generated to S-FF of the end point.

In step S5, the latch clock signal and the capture clock signal are integrated with the initialization test pattern generated in step S3 and the observation test pattern generated in step S4 to generate test patterns and data for delayed failure test.

In step S6, the test pattern data for a delay failure test is set in a scan test apparatus. In step S7, a test signal is applied from the scan test apparatus to the LSI of the test target at a timing according to the actual delay time and tested.

In step S8, the signal SOC previously generated as the test pattern data is compared with the scan output signal SOC actually output from the LSI to be tested to determine whether there is a delay failure. If it does not match, it passes. If it does not match, there is a failure, so it fails.

Patent Document 1 describes a test pattern generation method of a scan circuit for the purpose of shortening the test time.

However, the delay test method of the LSI has the following problems.

For example, when the delay time β of the clock signal CKC supplied to the S-FF 2C becomes large due to any cause and becomes a condition of + D <β, the combination clock 1B is set by the latch clock signal. The signal after the signal transition enters the S-FF 2C, and the signal after the signal transition of the combination circuit 1B enters the S-FF 2C again by the capture clock signal. For this reason, both the regular product and the defective product in which the delay failure occurs are inputted with the same signal in the capture operation, and the same signal is checked after the scan shift operation, and it is determined that there is no delay failure. For this reason, there was a possibility that a defective product could not be detected and it might be omitted.

An object of the present invention is to provide a LSI test method capable of accurately detecting defective products having a delay failure.

In the present invention, in an LSI having a combination circuit and S-FF formed at its input side and output side, the delay of the combination circuit is tested by the following processing.

That is, this test method is designed to specify the configuration information of the combination circuit, the S-FF of the input side start point and the S-FF of the output end point to be tested, and to transmit a signal change from the start point to the end point specified by the designated process. The first observation is made of an initial value generation process for generating a signal value of the S-FF of the start point as an initialization test pattern, and a signal value when the value after the signal value change of the initialization test pattern is input into the S-FF of the end point. A first observation value generating process generated as a test pattern for a second test; and a second signal value for generating a signal value when a value before a signal value change of the initialization test pattern is input into the S-FF of the endpoint; An observation value generation process, a first delay failure pattern generation process for generating a first delay failure test pattern based on the first observation test pattern, and the second observation In the case where there is no delay failure in the second delay failure pattern generation process of generating a second delay failure test pattern based on the test pattern and the delay failure test of the LSI using the first and second delay failure test patterns. The LSI performs a determination process for determining that it is normal.

(The best mode for carrying out the invention)

In the first observation test pattern, an initializing test pattern is provided to the combination circuit as a latch clock signal, and the output signal of the combination circuit is input to the end point S-FF as a capture clock signal after a predetermined delay time for the test. The signal pattern is obtained when the content of S-FF at the end point is shifted and output. The second observation test pattern provides an initializing test pattern to the combination circuit as the hold clock signal, inputs the output signal of the combination circuit to the S-FF of the end point as the hold clock signal, The signal pattern is obtained when the contents of the S-FF are shifted and output.

The above and other objects and novel features of the present invention will become more fully apparent upon reading the following description of the preferred embodiments in comparison with the accompanying drawings. However, the drawings are for illustration only and do not limit the scope of the present invention.

(Example 1)

1 is a flowchart of a delay test method of an LSI showing an embodiment of the present invention.

This delay test method shows the test procedure for detecting the delay failure of the LSI of FIG. 2 using the configuration of the delay test of FIG. 4, and the same reference numerals are assigned to the steps of performing the same processing as that of FIG.

In step S1 of FIG. 1, logic circuit configuration information such as combination circuits 1A, 1B, ... in the LSI to be tested is set in the test pattern generator.

In step S2, S-FF of the start point and the end point of the circuit under test is specified. This completes the setting for the test pattern generator.

In step S3, the test pattern generating device generates a signal value, i.e., an initialization test pattern, to which a signal change is transmitted from S-FF at the start point to S-FF at the end point.

In step S4, a signal value, i.e., a test pattern for first observation, on the premise that the signal after the signal change is input to the S-FF of the end point is generated. The processing of steps S1 to S4 so far is the same as in the prior art.

Next, in step S4A, a signal value on the premise of inputting the signal before the signal change into the S-FF of the end point, that is, a second test pattern for observation is generated.

In step S5, a first delay test is performed by integrating a clock pattern including a latch clock signal and a capture clock signal into the initialization test pattern generated in step S3 and the first observation test pattern generated in step S4. Create test pattern data.

In step S5A, a second delay test test pattern is incorporated by incorporating a clock pattern including a hold clock signal to be described later into the initialization test pattern generated in step S3 and the second observation test pattern generated in step S4A. Create data

In step S6, the test pattern data for the first delay failure test generated in step S5 is set in the scan test apparatus, and in step S7, the test signal is set from the scan test apparatus to the LSI to be tested at a timing that matches the actual delay time. To test.

In step S8, the signal SOC previously generated as the test pattern data is compared with the scan output signal SOC actually output from the LSI to be tested to determine whether there is a delay failure. If it does not match, there is a failure, so it is rejected. If it matches, the process goes to the next step S9.

In step S9, the test pattern data for the second delay test generated in step S5A is set in the scan test apparatus, and in step S10, the test signal is set from the scan test apparatus to the LSI to be tested at a timing that matches the actual delay time. To test.

In step S11, the signal SOC previously generated as the test pattern data is compared with the scan output signal SOC actually output from the LSI to be tested to determine whether there is a delay failure. If it does not match, it is determined that there is no failure and the result is passed. If it does not match, there is a failure, so it is rejected.

Fig. 6 is a signal waveform diagram showing the operation of the delay test in the embodiment of the present invention, in the delay test method shown in Fig. 1, corresponding to the generation process of the second observation test pattern in step S4A added to the conventional process. It is explanatory drawing of the operation | movement made.

Here, similarly to Fig. 3, in the LSI of Fig. 2, the number of input signals and output signals of the combination circuits 1A and 1B is 4, respectively, and the test data is supplied to the input side of the combination circuit 1B to be tested. The case where the delay time until the signal of the logical operation result is outputted is demonstrated is demonstrated. The clock signal CLK supplied from the clock terminal 5 is delayed by the time α and transmitted to each of the S-FFs 2B as the clock signal CKB, and delayed by the time β to the respective S signals as the clock signal CKC. -FF (2C) to be passed.

First, the scan permission signal SE is set to "H" to switch the selectors of all the S-FFs to the second input side. As a result, each FF of the S-FFs 2A _{1 to} 2A ₄ is cascade-connected to form a shift register from the scan input terminal 3A to the scan output terminal 4A. The signals output from the respective FFs of the S-FFs 2A _{1 to} 2A ₄ are given in parallel to the combination circuit 1A. Similarly, each FF of the S-FF (2B _{1 to} 2B ₄ ) is cascaded to form a shift register from the scan input terminal 3B to the scan output terminal 4B. The shift register of the S-FF (2B _{1 to} 2B ₄ ) is configured. The signal output from each FF is given in parallel to the combination circuit 1B.

At time t21 in Fig. 6, the scan input signals SIA and SIB to the scan input terminals 3A and 3B are set to " a4 " and " b4 &quot;, respectively, in accordance with the predetermined test data TDA and TDB. A pulsed clock signal CLK is supplied from the terminal 5. As a result, data "a4" and "b4" are input to the S-FFs 2A ₁ and 2B ₁ after the propagation delay in each clock supply path.

Hereinafter, at time t22, t23, and t24, the scan input signal SIA ("a3", "a2", "a1") is given in turn from the scan input terminal 3A, and S-FF according to the clock signal CLK. It is shifted in turn in (2A ₁ ~2A _4). Further, scan input signals SIB (" b3 &quot;," b2 &quot;," b1 &quot;) are given in turn from the scan input terminal 3B, and are sequentially shifted to S-FF (2B _{1 to} 2B ₄ ). By the above scan shift operation, the test data TDA; "a1", "a2", "a3", "a4" are held in each FF of the S-FFs 2A _{1 to} 2A ₄ , and the combined circuit 1A is maintained. ) In parallel. The test data TDB is held in each FF of the S-FFs 2B _{1 to} 2B ₄ , and the test data TDB is held in parallel to the combination circuit 1B. The combination circuit 1A performs a logic process based on the test data TDA, and after a predetermined processing time, the resultant signal RDA is output in parallel as an "initialization test pattern". In addition, the combination circuit 1B performs logic processing based on the test data TDB, and the resultant signal RDB1 is output in parallel after the predetermined processing time D. FIG.

At time t25, the scan permission signal SE of the terminal 5 is set to "L" so that the selectors of all the S-FFs are switched to the first input side. This is given to the input side of the FF of the signal _{S-FF (2B 1 ~2B 4} ) outputted from the combination circuit (1A). However, at this time t5, since the clock signal CLK is not given to the clock terminal 5, the contents of the FF of the S-FFs 2A _{1 to} 2A ₄ do not change.

At time t26, the hold (hold) clock signal CLK is supplied from the clock terminal 5. As shown in FIG. Since the clock signal CLK is delayed by the time α and is given to the S-FF 2B _{1 to} 2B ₄ as the clock signal CKB, the signal RDA output from the combination circuit 1A at this point is S-. is input to the FF FF (2B ₁ ~2B _4). In addition, since the clock signal CLK is delayed by the time β and is given to the S-FF 2C _{1 to} 2C ₄ as the clock signal CKC, the signal RDB1 ("c1x) output from the combination circuit 1B at this point in time. "," is c2x '', "c3x", "c4x") is input to the FF in the _{S-FF (2C 1 ~2C 4} ). This shift in the output terminal (SOC) from the output side of the S-FF (2C ₄₎ The output scan output signal SOC becomes “c4x.” The combination circuit 1B starts a logic process based on the signal RDA that has newly entered the FF of the S-FFs 2B _{1 to} 2B ₄ .

At time t27, the scan permission signal SE returns to " H " and the selectors of all the S-FFs are switched to the second input side, and the scan shift operation state is brought back.

After a time β from the rise of each clock signal CLK at the times t28 to t30, the contents of the FF of the S-FF (2C _{1 to} 2C ₄ ) are shifted in sequence, and the scan output signal SOC from the scan output terminal 4C. Are output in series. As a result, the scan output signal SOC output from the scan output terminal 4C becomes the signal before change RDB1 of the combination circuit 1B.

Therefore, the predetermined value (that is, the "second observation test pattern") based on the input data RDA and the logic circuit conditions of the combination circuit 1B, and the scan output signal actually output from the scan output terminal SOC ( By comparing the SOC), it becomes possible to detect an abnormal delay time of the clock supply path or the like.

For example, when the delay time β of the clock signal CKC with respect to the S-FF 2C becomes large and becomes a condition such as α + D <β, the combination circuit 1B is set by the hold (hold) clock signal CLK. After the change of, the output signal RDB2 enters the S-FF 2C. Therefore, the predetermined value and the scan output signal SOC actually output from the scan output terminal SOC do not coincide based on the input data RDA and the logic circuit condition, and it can be determined that there is any delay failure.

As described above, the delay test method of the LSI of the present embodiment uses the hold clock signal in addition to the processing for testing the output signal after the change of the combination circuit under test using the latch and capture clock signals conventionally performed. To test the output signal before the change of the combination circuit under test. Thereby, there is an advantage in that the defective LSI with delayed failure can be detected with high accuracy, and the probability of failing to see the delayed failure and being judged as a defective good can be reduced.

In the conventional method for determining and testing the time T between the latch operation and the capture operation, the detectable delay time is limited due to the limitation of the scan test apparatus (for example, T> 5 ns). For example, α + D The test in which -β was less than or equal to T was not possible, but the treatment added in this example can be performed without being subject to such limitation.

In addition, this invention is not limited to the said Example, A various deformation | transformation is possible. Examples of this modification include the following.

(1) When the combination circuit to be tested in the LSI is ultra-short and there is no combination circuit on its input side, the latch operation data needs to be input in parallel from the external input terminal.

(2) Although the LSI of FIG. 2 has a plurality of scan chains, it is similarly applicable to an LSI having one scan chain.

(3) The configurations of the test pattern generator and the scan test apparatus are not limited to those described.

(4) The order of the processing steps in FIG. 1 is not limited to the order illustrated. What is necessary is just an order which can be judged as passing, when a failure is not found by two tests by a 1st and 2nd delay failure test pattern.

In the LSI test of the present invention, the first test process using the first observation test pattern on the premise of inputting the value after the signal change into the S-FF of the endpoint, and the value before the signal change to the S-FF of the endpoint In the second test process using the second observation test pattern on the premise of inputting, if the delay failure does not exist anywhere, the LSI is determined to be normal. As a result, compared to the test of the LSI using the observation test pattern on the premise of simply inputting the value after the signal change into the S-FF of the end point, a defective LSI having a delay failure is detected with high accuracy, and the delay failure cannot be missed. There is an effect that the probability of determining a defective product as a good product can be reduced.

Claims (2)

In an LSI having a combination circuit and a scan flip-flop formed at an input side and an output side thereof, as a test method of an LSI for testing a delay of the combination circuit, Designation processing for designating the configuration information of the combination circuit and a scan flip-flop at an input start point and a scan flip-flop at an output end point to be tested; An initial value generation process of generating a signal value of a scan flip-flop at the start point as an initialization test pattern so that a signal change is transmitted from the start point to the end point specified in the designation process; A first observation value generation process of generating a signal value when a value after the signal value change of the initialization test pattern is input to the scan flip-flop of the end point as a first observation test pattern; A second observation value generation process of generating a signal value when a value before a signal value change of the initialization test pattern is input to the scan flip-flop of the end point as a second observation test pattern; A first delay failure pattern generation process of generating a first delay failure test pattern based on the first observation test pattern; A second delay failure pattern generation process of generating a second delay failure test pattern based on the second observation test pattern; And And a determination process for determining that the LSI is normal when there is no delay failure in the delay failure test of the LSI using the first and second delay failure test patterns. The method of claim 1, The first observation value generating process applies the initialization test pattern to the combination circuit as a clock signal for a latch and scans the output signal of the combination circuit with a capture clock signal after a predetermined delay time for a test. A signal state when the input to the flip-flop and the content of the scan flip-flop at the end point is shifted and output is generated as the first observation test pattern, The second observation value generating process applies the initialization test pattern to the combination circuit as a hold clock signal, inputs the output signal of the combination circuit to the scan flip-flop at the end point as the hold clock signal, And a signal state at the time of shifting and outputting the contents of the scan flip-flop at the end point as the second observation test pattern.

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