KR20060098432A - Semiconductor device, method of manufacturing same, identification label and information carrier - Google Patents

Abstract

The semiconductor device (100) comprises an integrated circuit (20) and a first and a second contact face (31,33). These are connected with vertical interconnects (32,34) to the integrated circuit (20). This integrated circuit (20) is present in a semiconductor layer of a substrate. This substrate is absent in a non-active area (B). This leads to the fact that on the side faces (101) of the device (100) neither conductive material nor parts of the semiconductor substrate are exposed. On lamination of the device between two metallized foils into an identification label, the risk of short-circuitry due to undesired contact at the side face (101) of the device (100), is prevented thereby.

Description

Semiconductor devices, identification labels, information carriers and methods of manufacturing semiconductor devices {SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SAME, IDENTIFICATION LABEL AND INFORMATION CARRIER}

The present invention relates to a semiconductor device, which device has a first side and a second side opposite,

A substrate comprising a semiconductor layer and an electrical insulation layer, the substrate being on a first side of the device;

An integrated circuit having a plurality of semiconductor devices formed in and / or on the semiconductor layer and interconnected according to a desired pattern in the wiring structure;

A first contact surface present on the first side of the device;

A semiconductor device is provided on a second side of a device and includes a second contact surface connected to a wiring structure.

The invention also relates to a method of manufacturing such a semiconductor device.

The invention further relates to an identification label and an information carrier comprising such a semiconductor device.

Such semiconductor devices are known from WO-A 02/075647. Known devices are integrated circuits with contact surfaces electrically conducting on the opposite side. This integrated circuit-according to the prior art-was formed on a silicon substrate layer having an electrical insulation layer on its surface. This insulating layer is generally a thermal oxide layer. This structure has the advantage of simple assembly in the identification label. : 1st and 2nd side are interchangeable.

A disadvantage of the known device is that it is less suitable for assembly on metal strips. Such metal sprips will be applied to the side as well as the first and second sides of the device. This can lead to leakage currents and parasitic effects in semiconductor devices on the substrate, especially in the high frequency range.

Accordingly, a first object of the invention is to provide a semiconductor device of a type that is less susceptible to parasitic effects during assembly to metal sprips as mentioned at the outset.

This goal can be implemented as follows.

There is an electrically insulating support layer covering the integrated circuit on the second side and extending laterally around the integrated circuit in the inactive area, through which the second contact surface is connected with the interconnect structure. There will be a vertical interconnect.

Partially removed laterally to prevent the semiconductor layer from being present in the inactive region,

The first contact surface is connected to the wiring structure through the vertical connecting line.

The integrated circuit in the inventive device is in fact an encapsulated island, ie at least much of it is electrically isolated except for the vertical connection. Due to these island-like structures and vertical leads, there is no risk that any leads on the semiconductor substrate or sides will come into contact with any metal foil. In this way it is possible to prevent uncontrollable and undesirable effects, which can lead to a decrease in function or even a decrease in production.

The inactive area of the device is the transverse area around the active area where the integrated circuit is formed. Inactive and active regions complement the entire surface of the device. However, it does not exclude the intermediate region between the active and inactive regions. The inactive area is therefore the edge part. As already mentioned, it is an object of the present invention to prevent any short-circuitry from occurring while lamination is implemented.

An advantage of the inventive device is that the thickness of the substrate can be reduced without compromising the stability of the device. In fact, the support layer assumes the support function from the semiconductor substrate. Since the support layer can be freely selected, this can bend the device as a whole or even make it completely flexible.

Another advantage is that as a result of thinning, the device can be completely or significantly transparent. This feature is advantageous in that safety functions are possible.

The advantage of confining the semiconductor layer of the substrate to a particular island is that the individual devices can each easily be separated. It is not necessary for any ceramic material or metal to be cut.

In a suitable embodiment, the vertical connection to the first contact surface is in the inactive region, the first contact surface being formed in the electrically conductive layer. The presence of the first contact surface in the separated layer reduces the resistance from the contact surface to the actual circuit in place of the heavily doped region on the second side of the substrate. Furthermore, the risk of undesirable interactions between the vertical connection lines through the substrate and the neighboring semiconductor elements is reduced.

In a preferred embodiment, the insulating layer is substantially continuous in the transverse direction to be in the inactive region. In particular, this insulating layer extends through the whole of the device from one side to the other side. This continuous presence not only benefits the stability of the device but also serves as an effective barrier in the process, for example as an etch stop. The effectiveness is great in that it can be used for both the process from the first side and the process from the second side. Furthermore, the oxide film or the insulating layer containing an oxide film preferentially has an adhesive force with respect to an organic substance layer.

The semiconductor device of the present invention can be provided by at least two techniques. In the first technique, a single crystal semiconductor substrate is utilized, and components are formed on the second side thereof and a thermal oxide film is provided. While thinning the substrate, the active region of the semiconductor device is protected by a hard mask against etching means (wet or dry). As a result, the device has a mesa on its first side.

In the second technique, a substrate having a buried oxide layer is utilized. A well known example of such a substrate is a silicon-on-insulated (SOI) substrate. The use of SOI substrates can not only bend the resulting device, but can also be completely flexible. This is particularly advantageous for identification labels where the existence of an integrated circuit must be kept confidential first. In this case, the electrical insulation layer is present on the second side of the substrate, and vertical connecting lines are connected therethrough. Instead of or in addition to the oxide layer, which is an electrically insulating layer, a passivation layer may be present, for example a nitride film, in particular a nitride film produced by LPCVD. This layer prevents the diffusion of impurities, including water, from the surrounding environment towards the device after removal of the substrate. Since the base layer of such an SOI substrate is only meant to be supported, it will be apparent to the skilled artisan that it must be removed to obtain the desired flexibility.

In a preferred embodiment, the wiring structure with the first and second via pads is present in the non-active area and the first and second vertical connecting lines are present in the pads, respectively. Since vertical connections are provided outside of the active region in which the semiconductor device is located, chemical contamination and parasitic electrical interactions can be prevented or at least reduced significantly. Moreover, any cracking that occurs as a result of pressure differences or differences in thermal expansion, which is actually present in multilayer thin films in which a large number of soft thin films are laminated, is more easily prevented if vertical leads are formed outside the active area. In particular, the second via pad has a large size compared to other patterns in integrated circuits. As a result of the thickness of the support layer and the etching step through the support layer, for example, it may be about 10 × 10 mitrometers or more.

It is highly desirable that via pads be formed over an electrically insulating layer that is part of the substrate. This form is advantageous for stability. In a more preferred embodiment, the via pad and the vertical connection line comprise a material with good ductility, such as aluminum. The electrical insulation layer preferentially comprises an oxide.

The support layer preferably comprises an organic material. Such materials may be chosen to be photosensitive. Furthermore, it can have a thickness in the range of 5 to 20 microns to provide the required support but nevertheless not so badly flexible. It may also have a low dielectric constant. This limits the parasitic capacitance between the first and second contact surfaces. Conversely, it may be desirable for the dielectric constant to be modified to increase. The resulting parasitic capacitor can be used as a tuning capacitor which is particularly suitable for combination with dipole antennas.

In another preferred embodiment, the support layer is also present on the first side of the device. The device is thus enclosed by such a support layer on both sides. This has a significant advantage in terms of bending properties. The device is known to be more sensitive to compressive stress than to elastic stress. Compressive stress can cause micro cracks in the semiconductor layer and / or interconnect structure. By also supplying a support layer to the first side, the compressive stress can be relaxed in this support layer. As will be apparent, the support layer must also have sufficient elasticity.

The inventive device may suitably be integrated in an identification label further comprising an antenna for wireless communication. Identification Labels Used in Logistics or Products in the Safety Field Next such identification labels may be safety documents or documents containing such documents, for example, banknotes, passports or other tickets. As is well known in the art, it appears desirable to attach an integrated circuit in a banknote to a security tread present in the banknote. Security tread can be used as a dipole antenna for any modulation required. In view of the ease of assembly and its flexibility, the inventive device fits very well for this purpose. Furthermore, the parasitic capacitor between the first and second contact surfaces can be designed to function as a tuning capacitor for the desired frequency.

On the other hand, the inventive device can be integrated in other devices, including information transfer media such as DVDs, CDs, or smart cards.

The coupling between the inventive device and the antenna is capacitively in that, for example, it is not only DC coupled with anisotropically conducting glue, but also the contact surface forms the electrode of the capacitor together with the antenna. All may be implemented. This may be an advantage in that the glue is provided in the semiconductor device prior to assembly. Particularly suitable glues are those in which the adhesion increases when heat is applied.

A second object of the invention is to provide a method of manufacturing the semiconductor device of the invention in a more stable manner.

This purpose is

In a wiring structure comprising a substrate having a semiconductor layer and an electrically insulating layer, the first and second via pads being substantially in the outer region transversely in the activation region, a plurality of interconnections formed in the activation region and interconnected according to a desired pattern. Providing an integrated circuit having a semiconductor device;

Applying a support layer of electrically insulating material over the second side and providing a contact window corresponding to the second via pad to the support layer;

Applying an electrical conductor material to a desired pattern over a second side, and connecting a second contact surface and a second vertical connection line between the contact surface and the second via pad;

Attaching a carrier with removable attachment means on the second side of the substrate;

Thinning the substrate from the first side such that the insulating layer of the substrate is exposed at least in the inactive region surrounded by the side shell of the activation region;

Forming a first contact surface on the first side, the first contact surface being connected to the first via pad at least through a first vertical connection line extending through the insulating layer;

The semiconductor device thus obtained is obtained by a method comprising the step of removing from the carrier.

This method according to the invention results in a semiconductor device similar to that known in EP-A 1,256,983, but has the obvious advantage in that it has contact on both the back and front surfaces.

It is particularly preferable to use substrates in the form of SOI. In this case, the insulating layer is embedded in the substrate. The substrate includes a base layer and a semiconductor layer, wherein the bottom layer is removed in a thinning process, and the semiconductor device is formed in and on the surface of the semiconductor layer.

The first vertical lead may be provided as part of the integrated circuit or after completion of the thinning process. This first vertical lead is preferably provided before the process, for example as part of an integrated circuit. This is advantageous in that none of the described method steps require high resolution.

Such low resolution patterning can be done in an assembly shop, which is generally cheaper than in a semiconductor wafer factory. If desired, a patterned support layer may also be provided before delivery of the device to the assembly plant.

As is well known in the art, it is more advantageous for a plurality of semiconductor devices to be provided in one run. In order to improve the removal of the device from the carrier, it is preferred that the support layer is removed at the edge of the wafer and an adhesive is provided instead.

In this and other aspects of the method, the semiconductor device and the identification label of the present invention will be further described with reference to the drawings.

1 to 7 show cross-sectional views of several steps in a first embodiment of the method.

8 shows a schematic cross-sectional view of a semiconductor device in accordance with the first embodiment.

9-14 show cross-sectional views of several steps in a second embodiment of the method.

15 shows a schematic cross-sectional view of a semiconductor device in accordance with the second embodiment.

16 is a detailed view of FIG. 15.

17 shows a schematic cross-sectional view of the integration of a semiconductor device in an identification label.

The drawings are not drawn to actual dimensions, and like reference numerals refer to like or similar parts.

1 to 7 relate to a first embodiment of a method of manufacturing a semiconductor device according to the invention. The resulting device is shown in FIG.

In the first method of the invention, the substrate 10 in which the insulating layer 11 is embedded is utilized. Buried layer 11 is typically an oxide layer, but preferably also includes a semiconductor layer of semiconductor material, typically grown epitaxially, and a nitride film for improving the chemical protection of integrated circuit 20 provided thereon. There is a bottom layer on the opposite side of the buried layer 11. In this case, the semiconductor material of both the bottom layer and the semiconductor layer is silicon. The integrated circuit 20 includes a plurality of semiconductor elements (not shown) in the active region. The devices are interconnected according to the desired pattern in the wiring structure (not specifically indicated). The structure includes a first via pad 21 and a second via pad 22, the pads 21 and 22 being in region (B) which is substantially external in the transverse direction of the activation region. The via pad is preferably formed of an Al layer from the viewpoint of ductility. But Cu, Ni. Ag or conductive paste may also be used as a substitute.

2 shows the result of applying the supporting layer 12 which is an electrical insulator to the second side 2. In this case, polyimide with a thickness of 10 to 20 um is typically utilized. Prior to applying polyimide, for example by spin coating, a primer layer has been provided to clean the surface and improve adhesion. After application of the polyimide, it is first heated to 125 ° C. and then to 200 ° C. The photoresist is then applied and developed after exposure to a suitable light source. Development includes structuring the polyimide layer to create a contact window 13 exposed to the second via pad 22. The polyimide support layer 12 is also removed at the edge region C of the substrate, which is typically a 6 inch wafer. Removal of the support layer 13 in the edge region of the substrate has a beneficial effect on yield.

3 shows the result after the electrically conductive layer is formed on the second side 2 of the substrate 10. The electrically conductive layer is applied to a pattern comprising a second contact surface 31 and a second vertical connecting line 32 between the contact surface 31 and the second via pad 22. Preferably the electrically conductive layer comprises Al. This, combined with the use of Al as the second via pad 22, provides a good electrical connection and gives the label the flexibility needed to withstand any bending or force of the foil during lamination of the device.

4 shows the substrate 1 after being attached to the carrier 40 with removable attachment means 41. In this case this means 41 is an adhesive layer and can be removed upon irradiation by UV-radiation. Therefore, the carrier 40 is transparent, and in this example, it is a glass layer. The oxide layer is preferably applied over the support layer, the second contact surface 31 and the connecting line 32. An advantage with this is the yield improvement too. If desired, this layer can be provided according to the desired pattern. The edge region C thus serves as a lead layer. As a result, in the edge region C, the adhesive force between the adhesive 41 and the support layer 12 is good, and in the other regions, the adhesive force is considerably weak.

5 shows the result after the substrate 10 is thinned from the first side. This thinning is generally obtained by polishing and subsequent etching with KOH. Thinning continues until the bottom layer of substrate 10 is removed. The buried layer 11 serves as an etch stop layer here.

6 shows the result after patterning the embedded oxide layer to form the contact window 14.

FIG. 7 shows the result when the metal layer is further applied to form the first vertical connecting line 34 and the first contact surface 33. The added metal layer comprises for example Al or Cu. In the case of Cu, the buried layer may be applied with a diffusion barrier to prevent any contamination of the semiconductor layer. After removal of the carrier 40 the individual device 100 can be separated.

8 shows the invention device 100 in the first embodiment. The device 100 includes a first contact surface 33 and a second contact surface 31 as well as an integrated circuit 20. The integrated circuit has vertical leads 32 and 34 for forming a connection with the contact surfaces 31 and 33. The device 100 has an active area (A) and an inactive area (B). This is supported by the support layer 12. The semiconductor layer of the substrate 1 is present only in the active region. In this case, the remaining portions of the substrate are only the epitaxially grown semiconductor layer and the electrically insulating layer 11 in the active region. Since no part of the semiconductor layer and the bottom layer are present in the inactive region, any unwanted electrical contact is prevented from being formed through the side surface 101 of the device 100. The support layer 12 here typically has a thickness of about 5-15 um, preferably 10 um, and the contact surfaces 31, 33 have a thickness of 0.2-1.5 um, preferably 1.0 um.

9-14 show a second embodiment of this method invention. This method includes the same number of steps as the steps in the first method. However, the main difference is the substrate 10. In this example, the substrate is monocrystalline or polycrystalline silicon without any buried oxide film. The oxide layer 11 is present on the second surface of the substrate 10 and used simultaneously as the gate oxide layer of the semiconductor element in the integrated circuit 20. The semiconductor device is formed by known methods on the substrate 10, ie by implanting selected materials in the required concentration. The implant also forms a well that extends through the portion of the substrate 10 towards the first side 1. On top of this well an oxide layer 11 is patterned and an electrical connection is made. This includes a first connecting line 34 to the first contact surface provided at a later stage of the process. In addition to the connecting line 34, a first via pad 21 and a second via pad 22 are formed. These via pads 21 and 22 are located outside of the activation area A and are not necessarily required but may be partly in the inactive area B.

10 shows the result of applying, curing, and patterning the preferred support layer 13 in a preferred manner to remove the support layer from the lateral area C and to form a contact window for the second via pad 22. Shows.

FIG. 11 shows the result of applying the electrical conductor in the desired pattern on top of the support layer 12 on the second side and thus forming a vertical connecting line 32 connected to the second contact surface 31 and the second contact pad 22. Shows.

12 shows the result of the structure being attached to the carrier 40 by an adhesive 41.

FIG. 13 shows the result of the etching mask 33 being applied after the substrate 10 is thinned from the first side 1. The etch mask consists of an electrical conductor and will function substantially as the first contact surface. Here, contact to the first contact pad 21 is formed through the well through the substrate 10, which is part of the vertical connection line 34. This is shown in more detail in FIG. 16, which is a vertical connection 34 formed by the well 34B and the metal trace 34A through the substrate 10, the integrated circuit element 20 and the substrate 10. Shows.

14 shows the result after the substrate 10 has been etched from the first side, so that the mesa 50 is formed by this method. Mesa 50 further defines inactive region B, which is outside of mesa, and no semiconductor substrate 10 is present. Via 34 may be external to mesa 50. In this case, vias 34 are formed in such a way that after the mesas are formed, an electrically conductive layer is provided on the first side 1 of the substrate according to the desired pattern.

FIG. 15 shows a semiconductor device 100 having a resultant active area A and an inactive area B. As shown in FIG. In this case, it should be noted that there is an extra area between the inactive area B and the active area A. FIG. The device 100 includes first and second contact surfaces 31, 33 and vertical leads 32, 34 for connecting the contact surfaces 31, 33 to the integrated circuit 20.

17 shows a method of integrating the semiconductor device 100 of the invention into a label 200. The label 200 is produced by laminating the first foil 211 and the second foil 212. The foil is provided at the roll 300 and the laminating process is implemented via the wheel 310. The foils 211, 212 each have a plurality of conductive patterns 201, 202, which can act as antennas, for example a dipole antenna. In this method, the semiconductor device 100 is provided between foils. An adhesive may be present on semiconductor device 100 or foils 201 and 202 to enhance adhesion. The semiconductor device 100 is provided without a special direction on the foil. Since there is no semiconductor substrate 10 in the inactive region, it is connected to both of the first and second contact surfaces of the device by electrical contact with one of the conductive patterns 201 and 202 or substantially parasitic electrostatic due to interaction through the semiconductor substrate. There is no risk of capacity. Patterns in foils 201 and 202 may further be designed to be a security tread.

Another advantage of the inventive device is that the active area here is protected against force during lamination to the label. During this lamination, the greatest force is applied to the metal area with the vertical connection line. However, it is outside of the active area A, and any force is caused further in the support layer. This support layer is based on the free surface towards the side of the device and can thus relax such forces. The V-shaped second vertical connection also appears to reduce the pressure effect during lamination.

In summary, the semiconductor device 100 is composed of an integrated circuit 20 and first and second contact surfaces 31 and 33. These are connected to the integrated circuit by vertical connectors 32 and 34. This integrated circuit resides in the semiconductor layer of the substrate. This substrate is not present in the inactive region. This causes the fact that no part of the conductive material or semiconductor substrate is exposed at the side 101 of the device 100. During the lamination of the device with an identification label between two metal foils, the risk of a short circuit due to unwanted contact at the side 101 of the circuit device 100 is thus avoided.

Claims (12)

A semiconductor device having a first side and a second side opposite thereto, A substrate comprising a semiconductor layer and an electrical insulation layer, the substrate being on a first side of the device, An integrated circuit having a plurality of semiconductor elements defined in and / or above the semiconductor layer and interconnected according to a desired pattern of wiring structure; A first contact surface present on the first side of the device, A second contact surface present on said second side of said device and connected to said wiring structure, There is an electrically insulating support layer covering the integrated circuit on the second side and extending laterally around the integrated circuit in an inactive region, through which the vertical connection line is provided to connect the second contact surface and the wiring structure. Let's The semiconductor layer of the substrate is partially removed laterally so as not to be present in the inactive region, The first contact surface is connected to the wiring structure through a vertical connection line Semiconductor device. The method of claim 1, The vertical connecting line to the first contact surface defined in the electrically conductive layer is present in the inactive region. Semiconductor device. The method according to claim 1 or 2, The electrically insulating layer is substantially continuous in the transverse direction and provided to the inactive region. Semiconductor device. The method of claim 1, The wiring structure includes first and second via pads, The via pads are in the inactive region, and the first and second vertical leads are respectively present in the pads. Semiconductor device. The method of claim 4, wherein The via pad is provided over the electrically insulating layer that is part of the substrate. Semiconductor device. The method according to claim 4 or 5, The second via pad and the second vertical connection line include a ductile material. Semiconductor device. The method of claim 1, The support layer comprises an organic material Semiconductor device. A semiconductor device according to any one of claims 1 to 7, and comprising an antenna for wireless transmission An identification label. A semiconductor device according to any one of claims 1 to 7 An information carrier. As a semiconductor device manufacturing method, Providing a semiconductor layer and an electrically insulating layer on the substrate, wherein an integrated circuit having a plurality of semiconductor elements is defined in the active region, the semiconductor elements being interconnected according to a desired pattern in a wiring structure, the wiring structure being the first and the second; A second via pad, the via pad being in a region substantially external to the transverse direction of the active region; Applying a support layer of an electrically insulating material on the second side, and providing a contact window to the support layer corresponding to the second via pad; Applying an electrical conductor material in a desired pattern on the second side, together with providing a second contact surface and a second vertical connection line between the contact surface and the second via pad, Attaching a carrier with removable attachment means over the second side of the substrate; Thinning the substrate from the first side such that the insulating layer of the substrate is exposed in at least some non-active regions lateral outwardly around the activation region; Forming a first contact surface on the first side, the first contact surface being connected to the first via pad through at least a first vertical connection line extending through the insulating layer; Removing the semiconductor device thus obtained from the carrier. Semiconductor device manufacturing method. The method of claim 10, An oxide layer is embedded in the semiconductor substrate, The substrate further includes a base layer and an active layer, wherein the bottom layer is removed in the thinning step, and the semiconductor device is defined on the surface of the active region. Semiconductor device manufacturing method. The method of claim 10, The first vertical connection line is provided as part of the integrated circuit Semiconductor device manufacturing method.

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