KR20060016061A - Apparatus and method for coding/decoding block low density parity check code with variable block length - Google Patents

Abstract

According to the present invention, a parity check matrix of a block low density parity check (LDPC) code includes an information part corresponding to an information word, a first parity part and a second parity part corresponding to parity, and an error correction performance. A method of generating the parity check matrix for improving the parity check, the code rate applied when the information word is encoded into the block LDPC code and the code word length of the block LDPC code can be supported at the code rate. A first process of determining a size of a first parity check matrix so as to correspond to a length of a first codeword, a second process of dividing the first parity check matrix having the determined size into blocks having a preset number of blocks; The data is divided into blocks corresponding to the information part, blocks corresponding to the first parity part, and blocks corresponding to the second parity part. And permutation matrices in predetermined blocks among the blocks classified as the first parity part, and permutation in the form of a full lower triangle to predetermined blocks among the blocks classified as the second parity part. A fourth process of arranging the matrices, and a step of arranging the permutation matrices such that the minimum cycle length on the factor graph of the block LDPC code becomes a preset first cycle length to blocks classified as the information part, and the weight is non-uniform. It includes five steps.

Variable-length block LDPC code, code rate, permutation matrix, identity matrix, minimum cycle

Description

Apparatus and method for block low density parity check code encoding / decoding having a variable block length {APPARATUS AND METHOD FOR CODING / DECODING BLOCK LOW DENSITY PARITY CHECK CODE WITH VARIABLE BLOCK LENGTH}             

1 is a view schematically showing a transceiver structure of a general communication system

2 illustrates a parity check matrix of a general (8, 2, 4) LDPC code.

3 is a diagram illustrating a factor graph of the (8, 2, 4) LDPC code of FIG.

4 schematically illustrates a parity check matrix of a general block LDPC code.

FIG. 5 shows a permutation matrix P of FIG. 4.

6 is a diagram schematically illustrating a cycle structure of a block LDPC code in which a parity check matrix is composed of four partial matrices.

7 is a diagram illustrating a parity check matrix having a form similar to that of a full lower triangular matrix.

FIG. 8 is a diagram of dividing the parity check matrix of FIG. 7 into six partial blocks.

FIG. 9 shows the partial matrix of the parity check matrix of FIG. 7 as the transpose matrix of the partial matrix B of FIG. 8, the partial matrix E, the partial matrix T, and the inverse of the partial matrix T;                 

10 is a flowchart illustrating a process of generating a parity check matrix of a block LDPC code according to an embodiment of the present invention.

11 illustrates a parity check matrix of a variable length block LDPC code according to a first embodiment of the present invention.

12 illustrates a parity check matrix of a variable length block LDPC code according to a second embodiment of the present invention.

13 illustrates a parity check matrix of a variable length block LDPC code according to a third embodiment of the present invention.

14 illustrates a parity check matrix of a variable length block LDPC code according to a fourth embodiment of the present invention.

15 is a flowchart illustrating a process of encoding a variable length block LDPC code according to the first to fourth embodiments of the present invention.

16 is a block diagram showing an internal structure of a coding apparatus of a variable length block LDPC code for performing a function in embodiments of the present invention.

17 is a diagram illustrating an internal structure of a decoding apparatus of a block LDPC code for performing a function in embodiments of the present invention.

18 illustrates a parity check matrix of a variable length block LDPC code according to a fifth embodiment of the present invention.

19 illustrates a parity check matrix of a variable length block LDPC code according to a sixth embodiment of the present invention.                 

20 illustrates a parity check matrix of a variable length block LDPC code according to a seventh embodiment of the present invention.

21 illustrates a parity check matrix of a variable length block LDPC code according to an eighth embodiment of the present invention.

22 illustrates a parity check matrix of a variable length block LDPC code according to a ninth embodiment of the present invention.

23 is a diagram illustrating a parity check matrix of a variable length block LDPC code according to a tenth embodiment of the present invention.

24 illustrates a parity check matrix of a variable length block LDPC code according to an eleventh embodiment of the present invention.

25 illustrates a parity check matrix of a variable length block LDPC code according to a twelfth embodiment of the present invention.

26 illustrates a parity check matrix of a variable length block LDPC code according to a thirteenth embodiment of the present invention.

27 illustrates a parity check matrix of a variable length block LDPC code according to a fourteenth embodiment of the present invention.

28 illustrates a parity check matrix of a variable length block LDPC code according to a fifteenth embodiment of the present invention.

The present invention relates to a mobile communication system, and more particularly, to an apparatus and method for encoding / decoding a block low density parity check code having a variable block length.

 The most fundamental problem in communication is how efficiently and reliably data can be transmitted over a channel. In the next generation multimedia mobile communication system, which is being actively researched recently, a channel communication technique suitable for the system is used as a high speed communication system capable of processing and transmitting various information such as video and wireless data beyond the initial voice-oriented service is required. It is essential to increase the efficiency of the system.

When transmitting data, inevitable errors due to noise, interference, and fading occur depending on the channel conditions, resulting in loss of information. In general, in order to reduce such information loss, various error-control techniques are used according to the characteristics of the channel to increase the reliability of the system. The most basic of these error control techniques is the use of error-correcting codes.

A basic block diagram of a communication system for encoding and decoding using the error correction code or the like will be described with reference to FIG. 1.

1 is a diagram schematically illustrating a transceiver structure of a general communication system.                         

Referring to FIG. 1, first, a message u to be transmitted from a transmitter is encoded by an encoding method preset by an encoder 101 before being transmitted through a channel. In addition, the encoded symbol c encoded by the encoder 101 is modulated by a modulation scheme preset in the modulator 103, and the modulated signal s is transmitted to the receiver through the channel 105. .

이며, 상기 송신기측에서 송신한 신호 u를 수신기측에서 오류 없이 복원하기 위하여 보다 성능이 우수한 채널 부호화기 및 복호화기가 요구되고 있다. 특히, 상기 채널이 무선 채널일 경우 채널에 의한 오류는 보다 심각하게 고려되어야 한다. 상기 수신기측의 복호화기(109)는 상기 채널을 통해 수신된 데이터를 통해 송신 메시지의 추정치(estimate)를 알아낸다.The signal r received at the receiver side becomes a distorted signal in which various noises are mixed with the signal s transmitted from the transmitter side according to channel conditions. The received signal r is demodulated in a manner corresponding to the modulation scheme applied by the modulator 101 on the transmitter side through a demodulator 107, and the demodulated signal x is decoded in a decoder 109. The decoding is performed in a manner corresponding to the encoding scheme applied by the encoder 101 on the transmitter side. The signal decoded by the decoder 109 is

In order to recover the signal u transmitted from the transmitter side without error at the receiver side, a channel encoder and a decoder having better performance are required. In particular, if the channel is a wireless channel, errors due to the channel should be considered more seriously. The decoder 109 on the receiver side finds an estimate of the transmission message through the data received on the channel.

With the rapid development of mobile communication systems, there is a demand for developing a technology capable of transmitting a large amount of data approaching the capacity of a wired network in a wireless network. As a high-speed mass communication system capable of processing and transmitting a variety of information such as video and wireless data beyond voice-oriented services is required, improving system transmission efficiency by using an appropriate channel coding method is required. It becomes an essential element for improvement. However, due to the characteristics of the mobile communication system, the mobile communication system inevitably generates an error due to noise, interference, fading, etc. according to channel conditions when transmitting data. Loss of information data due to error occurs.

In order to reduce information data loss due to such an error, the reliability of the mobile communication system can be improved by using various error-control techniques according to the characteristics of the channel. The most commonly used error control technique among the error control techniques is a technique using an error-correcting code. Representative codes of the error correction code include a turbo code, a low density parity check (LDPC) code, and the like.

The turbo code is known to have a superior performance gain in high-speed data transmission, compared to a convolutional code used mainly for error correction. The turbo code effectively corrects errors due to noise generated in a transmission channel and transmits data. It has the advantage of increasing the reliability of. In addition, the LDPC code may be decoded using an iterative decoding algorithm based on a sum-product algorithm on a factor (hereinafter, referred to as a 'factor') graph. By using a decoding method using an iterative decoding algorithm based on the sum product algorithm, the decoder of the LDPC code not only has a lower complexity than the decoder of the turbo code but also facilitates the implementation of a parallel processing decoder.

Shannon's channel coding theorem, on the other hand, says that reliable communication is possible only at data rates that do not exceed the capacity of the channel. In Shannon's channel coding theory, however, there was no specific method for channel coding and decoding that could use the channel's capacity limit. Random codes with very large block sizes show performance close to the channel capacity limit in Shannon's channel coding theory, but in terms of computation when applying maximum a posteriori (MLAP) or maximum likelihood (ML) decoding There was a huge load that was not possible.

을 사용하여 비트 에러 레이트(BER: Bit Error Rate)

에서 Shannon의 채널 부호화의 채널 용량 한계에서 단지 0.04[dB] 정도의 차이를 가지는 성능을 나타낸다. 또한,

인 갈로아 필드(Galois Field, 이하 'GF'라 칭하기로 한다), 즉 GF(q)에서 정의된 LDPC 부호는 복호화에 있어서 복잡도가 증가하긴 하지만 이진(binary) 부호에 비해 훨씬 더 우수한 성능을 보인다. 그러나, 아직 반복 복호화 알고리즘의 성공적인 복호화에 대한 만족스런 이론적인 설명이 이루어지지 않고 있다.The turbo code was proposed in 1993 by Berrou, Glavieux, and Thitimajshima, and has an excellent performance approaching the channel capacity limit of Shannon's channel coding theory. Due to the proposal of the turbo code, studies on iterative decoding and graph representation of the code have been actively conducted. At this point, the LDPC code proposed by Gallager in 1962 was rediscovered. In addition, a cycle exists on the factor graph of the turbo code and the LDPC code, and it is well known that iterative decoding on the factor graph of the LDPC code in which the cycle exists is suboptimal. LDPC code has also been experimentally proven to have excellent performance through iterative decoding. The best performing LDPC code known to date is block size

Bit Error Rate (BER)

Shows the performance of only 0.04 [dB] difference in channel capacity limit of Shannon's channel coding. Also,

LDPC codes defined in Galois Fields (hereinafter referred to as'GF's), ie, GF ( q ), perform much better than binary codes, although they increase complexity in decoding. . However, a satisfactory theoretical explanation for successful decoding of an iterative decoding algorithm has not been made yet.

In addition, the LDPC code is a code proposed by Gallager, and a parity check matrix in which most elements have a value of 0, and very few elements other than the elements having the value of 0 have a value of 1. matrix). For example, the (N, j, k) LDPC code is a linear block code having a block size of N. Each element has j values of 1 and each row. A sparse structure consisting of elements having k values of 1 per (row), and all elements except 0 having values of 1 are elements having a value of 0. It is defined by the parity check matrix of.

As described above, an LDPC code having a constant weight of j in each parity check matrix and having a constant weight of k in the parity check matrix is called a regular LDPC code. In contrast, an LDPC code in which the weight of each column and the weight of each row in the parity check matrix is not constant is called an irregular LDPC code. In general, it is known that the performance of the non-uniform LDPC code is superior to that of the uniform LDPC code. However, in the case of the non-uniform LDPC code, since the weight of each column and the weight of each row in the parity check matrix are not constant, the weight of each column and the weight of each row in the parity check matrix must be properly adjusted to ensure excellent performance. .

Next, the parity check matrix of the (N, j, k) LDPC code, for example, the (8, 2, 4) LDPC code, will be described with reference to FIG. 2.

2 is a diagram illustrating a parity check matrix of a general (8, 2, 4) LDPC code.

Referring to FIG. 2, first, the parity check matrix H of the (8, 2, 4) LDPC code is composed of eight columns and four rows, and the weight of each column is equal to two, and the weight of each row is Uniform to 4 Thus, since the weight of each column in the parity check matrix is uniform with the weight of each row, the (8, 2, 4) LDPC code shown in FIG. 2 becomes a uniform LDPC code.

In FIG. 2, the parity check matrix of the (8, 2, 4) LDPC code has been described. Next, a factor graph of the (8, 2, 4) LDPC code described with reference to FIG. 2 will be described with reference to FIG. 3. do.                         

3 is a diagram illustrating a factor graph of the (8, 2, 4) LDPC code of FIG.

Referring to FIG. 3, the factor graph of the (8, 2, 4) LDPC code includes eight variable nodes, that is, x1 (211), x2 (213), x3 (215), It consists of x4 217, x5 219, x6 221, x7 223, x8 225, and four check nodes 227, 229, 231, 233. If there is an element having a weight, that is, a value of 1 at the point where the i th column and the j th row of the parity check matrix of the (8, 2, 4) LDPC code intersect, a branch between the variable node xi and the j th check node ( branch is created.

As described above, since the parity check matrix of the LDPC code has a very small weight, it can be decoded through iterative decoding even in a block code having a relatively long size, and the block size of the block code continues to increase. As shown in the figure, the performance is in the form of a turbo code approaching Shannon's channel capacity limit. In addition, MacKay and Neal have already demonstrated that the iterative decoding process of the LDPC code using the flow transfer method has a performance almost close to the iterative decoding process of the turbo code.

Meanwhile, in order to generate a high performance LDPC code, several conditions must be satisfied. The above conditions are described below.

(1) The cycle on the factor graph of the LDPC code must be considered.

The cycle represents a loop formed by an edge connecting a variable node and a check node in a factor graph of an LDPC code, and the length of the cycle is defined as the number of edges constituting the loop. The long length of the cycle indicates that the number of edges connecting the variable nodes and the check nodes constituting the loop in the factor graph of the LDPC code is large. On the contrary, the short length of the cycle means that The factor graph indicates that the number of edges connecting the variable nodes and the check nodes constituting the loop is small.

The longer the cycle on the factor graph of the LDPC code is generated, the better the performance of the LDPC code is. This is because when a long cycle on the factor graph of the LDPC code is generated long, performance degradation such as an error floor generated when there are many short length cycles on the factor graph of the LDPC code does not occur.

(2) Consideration should be given to efficient coding of LDPC codes.

The LDPC code has a higher coding complexity than a convolutional code or a turbo code due to the characteristics of the LDPC code. In order to reduce the coding complexity of the LDPC code, a repeat accumulate code (RA) code or the like has been proposed, but the repeated accumulator code also has a limitation in reducing the coding complexity of the LDPC code. Therefore, efficient coding of LDPC codes must be considered.

(3) The order distribution on the factor graph of the LDPC code should be considered.

In general, a non-uniform LDPC code performs better than a uniform LDPC code because the degree on the factor graph of the non-uniform LDPC code has various orders. Here, the order represents the number of edges connected to each node, that is, variable nodes and check nodes, on the factor graph of the LDPC code. In addition, the order distribution on the factor graph of the LDPC code indicates how many nodes among the nodes have a particular order. Richardson et al. Have already demonstrated that the performance of LDPC codes with a particular order distribution is superior.

Next, a parity check matrix of a block LDPC code will be described with reference to FIG. 4.

4 is a diagram schematically illustrating a parity check matrix of a general block LDPC code.

크기를 가지는 순열 행렬을 나타내며, 상기 순열 행렬 P의 위첨자 a_ij는

혹은 a_ij = ∞를 가진다. 또한, 상기 i는 해당 순열 행렬이 상기 패리티 검사 행렬의 다수의 부분 블록들중 i번째 행에 위치함을 나타내며, j는 해당 순열 행렬이 상기 패리티 검사 행렬의 다수의 부분 블록들중 j번째 열에 위치함을 나타낸다. 즉,

는 상기 다수의 부분 블록들로 구성된 패리티 검사 행렬의 i번째 행과 j번째 열이 교차하는 지점의 부분 블록에 존재하는 순열 행렬을 나타낸다.Before explaining FIG. 4, first, the block LDPC code is a new LDPC code considering not only efficient coding but also efficient storage and performance improvement of the parity check matrix. The block LDPC code is extended by generalizing a structure of a uniform LDPC code. One concept is the LDPC code. Referring to FIG. 4, the parity check matrix of the block LDPC code divides an entire parity check matrix into a plurality of partial blocks and associates a permutation matrix to each of the partial blocks. Has P shown in FIG. 4 is

Represents a permutation matrix having a magnitude, and the superscript a _ij of the permutation matrix P is

Or a _ij = ∞. In addition, i indicates that the permutation matrix is located in the i th row of the plurality of partial blocks of the parity check matrix, j is the permutation matrix located in the j th column of the plurality of partial blocks of the parity check matrix. It is displayed. In other words,

Denotes a permutation matrix present in the partial block of the point where the i-th row and the j-th column of the parity check matrix composed of the plurality of partial blocks intersect.

Next, the permutation matrix will be described with reference to FIG. 5.

FIG. 5 is a diagram illustrating a permutation matrix P of FIG. 4.

크기를 가지는 정사각 행렬로서, 상기 순열 행렬 P는 상기 순열 행렬 P를 구성하는 N_s개의 행들 각각의 웨이트가 1이고, 상기 순열 행렬 P를 구성하는 N_s개의 행들 각각의 웨이트 역시 1인 행렬을 나타낸다.As shown in FIG. 5, the permutation matrix P is

As a square matrix having a size, and a permutation matrix P is a permutation and matrix P with a weight of each of N _s of rows constituting a is 1, N _s of rows, each of the weights is also one of the matrix constituting the permutation matrix P .

를 나타내며, 상기 순열 행렬 P의 위첨자 a_ij가 ∞일 때, 즉 순열 행렬 P^∞는 영(zero) 행렬 나타낸다.Meanwhile, in FIG. 4, when the superscript a _ij of the permutation matrix is 0, that is, the permutation matrix P ⁰ is an identity matrix.

When the superscript a _ij of the permutation matrix P is ∞, that is, the permutation matrix P ^∞ represents a zero matrix.

이고, 전체 열의 개수가

이므로 (단,

), 상기 블록 LDPC 부호의 전체 패리티 검사 행렬이 최대 랭크(full rank)를 가지는 경우 상기 부분 블록들의 크기에 상관없이 부호화율(coding rate)은 하기 수학식 1과 같이 나타낼 수 있다.In FIG. 4, the total parity check matrix of the block LDPC code has the total number of rows.

, The total number of columns

(But,

In the case where the full parity check matrix of the block LDPC code has a maximum rank, a coding rate may be expressed by Equation 1 regardless of the size of the partial blocks.

일 경우, 상기 부분 블록들 각각에 대응하는 순열 행렬들 각각은 영 행렬이 아님을 나타내며, 부분 블록들 각각에 대응하는 순열 행렬들 각각의 각 열의 웨이트는 p, 각 행의 웨이트는 q인 균일 LDPC 부호가 된다. 여기서, 상기 부분 블록들에 대응하는 순열 행렬을 '부분 행렬'이라 칭하기로 한다. On the other hand, for all i and j

In this case, each of the permutation matrices corresponding to each of the partial blocks is not a zero matrix, and the weight of each column of each of the permutation matrices corresponding to each of the partial blocks is p and the weight of each row is q. Sign. Here, the permutation matrix corresponding to the partial blocks will be referred to as a 'partial matrix'.

In addition, since the p-1 dependent rows exist in the entire parity check matrix, a coding rate has a larger value than the coding rate calculated in Equation (1). In the block LDPC code, when the weight position of the first row of each of the partial matrices constituting the entire parity check matrix is determined, the weight position of the remaining N _s -1 rows is determined, thereby storing information of the entire parity check matrix. In order to reduce the size of the memory, the amount of memory required is reduced to 1 / N _s .

On the other hand, as described above, the cycle on the factor graph of the LDPC code indicates a loop formed by the edge connecting the variable node and the check node in the factor graph of the LDPC code of the parity check matrix, and the length of the cycle constitutes the loop. It is defined as the number of edges. The long length of the cycle indicates that the number of edges connecting the variable node and the check node constituting the loop in the factor graph of the LDPC code is large. The longer the length of the cycle on the factor graph of the LDPC code is, the better the performance of the LDPC code is. On the contrary, the more short cycles exist on the factor graph of the LDPC code, the lower the error correction capability of the LDPC code is. That is, when there are many cycles of short length on the factor graph of the LDPC code, the information returned from one node belonging to the short cycle is returned to itself again after a small number of iterations. As the number of times increases, the information keeps coming back to the user, so the information is not updated well, and thus the error correction ability is degraded.

Next, a cycle structure characteristic of a block LDPC code will be described with reference to FIG. 6.

6 is a diagram schematically illustrating a cycle structure of a block LDPC code in which a parity check matrix is composed of four partial matrices.

Before describing FIG. 6, the block LDPC code is an LDPC code considering not only efficient encoding but also efficient storage and performance improvement of a parity check matrix. The block LDPC code is an LDPC code having a generalized and extended structure of a uniform LDPC code. The parity check matrix of the block LDPC code illustrated in FIG. 6 is composed of four blocks, and an oblique line indicates a position where elements having a value of 1 exist, and all parts other than the oblique line part have a value of 0. Indicates the location of elements with. In addition, P represents the same permutation matrix as the permutation matrix described with reference to FIG. 5.

In order to analyze the cycle structure of the block LDPC code illustrated in FIG. 6, the element having a value of 1 located in the i th row of the partial matrix P ^a is determined based on the element, and has a value of 1 located in the i th row. The element will be referred to as '0-point'. Here, the partial matrix represents a matrix corresponding to the partial block. Then, the 0-point is located in the i + a th column of the partial matrix P ^a .

An element having a value of 1 in the partial matrix P ^b located in the same row as the zero point is referred to as a '1-point'. For the same reason as the zero point, the one-point is located in the i + b th column of the partial matrix P ^b .

Next, an element having a value of 1 in the partial matrix P ^{c positioned} in the same column as the 1-point will be referred to as a '2-point'. Since the partial matrix P ^c is a matrix obtained by shifting each column of the identity matrix I to the right by modulo N _s , a 2-point is i + b-c-th row of the partial matrix P ^c . It is located at.

In addition, an element having a value of 1 in the partial matrix P ^{d positioned} in the same row as the 2-point will be referred to as a '3-point'. The 3-point is located in the i + b-c + d-th column of the partial matrix P ^d .

Finally, an element having a value of 1 in the partial matrix P ^a located in the same column as the 3-point will be referred to as a '4-point'. The 4-point is located at the i + b-c + d-a th row in the partial matrix P ^a .

In the cycle structure of the LDPC code shown in FIG. 6, if there is a cycle of length 4, the 0-point and 4-point are the same positions. That is, the relationship shown in Equation 2 is established between the 0-point and the 4-point.

And, rearranging Equation 2 can be expressed as Equation 3 below.

의 관계가 성립하게 되고, 하기 수학식 4와 같은 관계가 성립하게 된다.As a result, when the relationship as in Equation 3 is established, a cycle of length 4 is generated. In general, when the 0-point and the 4p-point become equal for the first time,

Relationship is established, and the following equation (4) is established.

In other words, assuming that p is a positive integer having a minimum value among positive integers satisfying Equation 4 for a, b, c, and d, the cycle of the block LDPC code as shown in FIG. In the structure, a cycle of length 4p is the cycle having the minimum length.

인 경우

이 성립하면, p = N_s가 되고, 따라서 길이가 4N_s인 사이클이 최소 길이를 가지는 사이클이 되는 것이다.As a result, as described above

If

If this holds, p = N _s , and thus, a cycle having a length of 4N _s becomes a cycle having a minimum length.

Meanwhile, the Richardson-Urbanke method will be used as the coding method of the block LDPC code. Since the Richardson-Urbanke method is used as an encoding method, the shape of the parity check matrix has a form similar to that of a full lower triangular matrix, thereby minimizing coding complexity.

Next, a parity check matrix having a form similar to that of a full lower triangular matrix will be described with reference to FIG. 7.

FIG. 7 illustrates a parity check matrix having a form similar to that of a full lower triangular matrix.

혹은 a_ij = ∞를 가진다. 상기 정보 파트의 순열 행렬 P의 위첨자 a_ij가 0일 경우, 즉 P⁰는 항등 행렬

를 나타내며, 상기 순열 행렬 P의 위첨자 a_ij가 ∞일 때, 즉 순열 행렬 P^∞는 영 행렬 나타낸다. 또한, p와 q는 상기 패리티 검사 행렬에서 상기 정보 파트에 해당하는 부분 블록들의 행과 열의 개수를 나타낸다. 또한, 상기 패리티 파트의 순열 행렬 P의 위첨자 a_i, x, y 역시 순열 행렬 P의 지수를 나타내며, 다만 설명의 편의상 정보 파트와의 구분을 위해 상이하게 설정하였을 뿐이다. 즉, 상기 도 7에서

내지

역시 순열 행렬들이며, 상기 패리티 파트의 대각(diagonal) 부분에 위치하는 부분 행렬들에 순차적으로 인덱스(index)를 부여한 것이다. 또한, 상기 도 7에서 P^x와 P^y 역시 순열 행렬들이며, 설명의 편의상 임의의 인덱스를 부여한 것이다. 상기 도 7에 도시되어 있는 바와 같은 패리티 검사 행렬을 가지는 블록 LDPC 부호의 블록 크기를 N이라고 가정하면, 상기 블록 LDPC 부호의 부호화 복잡도는 상기 블록 크기 N에 대해서 선형적으로 증가한다(0(N)). In the parity check matrix illustrated in FIG. 7, the parity part is out of the shape of the full lower triangular matrix as compared to the parity check matrix having the full lower triangular matrix. In FIG. 7, the superscript a _ij of the permutation matrix P of the information part is

Or a _ij = ∞. If the superscript a _ij of the permutation matrix P of the information part is 0, that is, P ⁰ is an identity matrix

When the superscript a _ij of the permutation matrix P is ∞, that is, the permutation matrix P ^∞ represents a zero matrix. In addition, p and q represent the number of rows and columns of partial blocks corresponding to the information part in the parity check matrix. In addition, the superscripts a _i , x, and y of the permutation matrix P of the parity part also represent exponents of the permutation matrix P, but are merely set differently from the information part for convenience of description. That is, in FIG.

To

Also, they are permutation matrices, and indexes are sequentially assigned to partial matrices positioned in a diagonal portion of the parity part. In FIG. 7, P ^x and P ^{y are} also permutation matrices, which are given an arbitrary index for convenience of description. Assuming that the block size of the block LDPC code having the parity check matrix as shown in FIG. 7 is N, the coding complexity of the block LDPC code increases linearly with respect to the block size N (0 (N)). ).

On the other hand, the biggest problem of the LDPC code having a parity check matrix as shown in FIG. 7 is that when the size of the partial block is N _s , N _s checks having a degree of 1 are always on the factor graph of the block LDPC code. Nodes are created. In this case, the order 1 check nodes do not affect the performance improvement due to the iterative decoding, and thus, a standard non-uniform LDPC code such as the Richardson-Urbanke method does not include the order 1 check node. Therefore, it is assumed that the parity check matrix as shown in FIG. 7 is a basic parity check matrix in order to design the parity check matrix so as to enable efficient encoding without including the check node of order 1. The selection of the partial matrix in the parity check matrix composed of the partial matrices as shown in FIG. 7 is a very important factor in improving the performance of the block LDPC code, and therefore, finding an appropriate selection criterion of the partial matrix is also a very important factor. .

Next, a method of designing a parity check matrix of the block LDPC code based on the configuration of the block LDPC code described above will be described.

In order to facilitate the method of designing the parity check matrix of the block LDPC code and the coding method of the block LDPC code, the parity check matrix as shown in FIG. 8 is represented by six partial matrices as shown in FIG. 9. It is assumed that the form consisting of.

8 is a diagram illustrating the parity check matrix of FIG. 7 divided into six partial blocks.

Referring to FIG. 8, the parity check matrix of the block LDPC code illustrated in FIG. 7 is a partial block of an information part (s), a first parity part (p ₁ ), and a second parity part (p ₂ ). Split into Here, the information part (s) represents a part of the parity check matrix that is mapped to an actual information word in the process of encoding a block LDPC code like the information part described with reference to FIG. 7, but the description is merely used for convenience of description. . In addition, the first parity part p ₁ and the second parity part p ₂ are parts of the parity check matrix mapped to actual parity in the process of encoding the block LDPC code as in the parity part described with reference to FIG. 7. The parity part is divided into two parts.

The partial blocks of the information part s, that is, the partial matrices corresponding to the partial block A 802 and the partial block C 804 are A and C, partial blocks of the first parity part p ₁ , That is, the partial matrices corresponding to the partial block B 806 and the partial block D 808 are B and D, and the partial blocks of the second parity part p ₂ , that is, the partial block T 810 and the partial block E ( The partial matrices corresponding to 812 are T and E. In FIG. 8, the parity check matrix is illustrated as being divided into seven partial blocks. However, O is not a separate partial block, but the partial matrix T corresponding to the partial block T 810 has a completely lower triangular shape. It should be noted that only the area where the O matrix is arranged around the diagonal line is marked as 0. A process of simplifying an encoding method by using the partial matrices of the information part (s), the first parity part (p ₁ ), and the second parity part (p ₂ ) will be described with reference to FIG. 10. The description will be omitted.

Next, the partial matrices of FIG. 8 will be described with reference to FIG. 9.

9 is a diagram illustrating a partial matrix of the parity check matrix of FIG. 7 as a transpose matrix of the partial matrix B of FIG. 8, a partial matrix E, a partial matrix T, and an inverse matrix of the partial matrix T.

는

를 나타낸다. 또한, 상기 도 9에서 상기 순열 행렬

는 항등 행렬이 될 수도 있음은 물론이다. 이는 상기에서 설명한 바와 같이 상기 순열 행렬의 지수, 즉

이 0이 될 경우에는 상기 순열 행렬

이 항등 행렬이 되기 때문이며, 또한 상기 순열 행렬의 지수, 즉

이 미리 설정된 값만큼 증가할 경우에는 상기 순열 행렬이 상기 증가한 설정값에 해당하는 만큼 다시 순환 쉬프트되어 결과적으로 상기 순열 행렬

이 항등 행렬이 되기 때문이다.Referring to FIG. 9, the partial matrix B ^T represents a transpose matrix of the partial matrix B, and the partial matrix T ⁻¹ represents an inverse matrix of the partial matrix T. In addition, in FIG.

Is

Indicates. In addition, the permutation matrix in FIG.

Of course, may be an identity matrix. This is the exponent of the permutation matrix as described above, i.e.

Is 0, the permutation matrix

This is because it becomes an identity matrix, and the exponent of the permutation matrix,

When the permutation matrix is increased by a predetermined value, the permutation matrix is cyclically shifted again by the corresponding increase of the set value, and as a result, the permutation matrix

This is because it becomes an identity matrix.

Next, a parity check matrix design process of the block LDPC code will be described with reference to FIG. 10.

10 is a flowchart illustrating a process of generating a parity check matrix of a general block LDPC code.

이 된다. 또한, 상기 도 10에 도시되어 있는 블록 LDPC 부호의 패리티 검사 행렬 생성 과정은 최초에 통신 시스템의 시스템 상황에 맞게 생성되고, 이후에는 상기 생성되어 있는 패리티 검사 행렬을 이용하는 것이므로, 실질적으로 상기 도 10의 패리티 검사 행렬 생성 과정은 1번만 수행되면 된다. Before describing FIG. 10, in order to generate a block LDPC code, a codeword size and a code rate of a block LDPC code to be generated are determined, and a size of a parity check matrix is corresponding to the determined codeword size and a code rate. You must decide. Assuming that the codeword size of the block LDPC code is N and the code rate is R, the size of the parity check matrix is

Becomes In addition, since the parity check matrix generation process of the block LDPC code shown in FIG. 10 is first generated in accordance with the system situation of the communication system, the generated parity check matrix is subsequently used. The parity check matrix generation process only needs to be performed once.

의 패리티 검사 행렬을 가로 축으로 p개의 블록들로 분할하고, 세로 축으로 q개의 블록들로 분할하여 총

개의 블록들로 분할한 후 1013단계로 진행한다. 여기서, 상기 블록들 각각의 크기는

이므로 상기 패리티 검사 행렬은

개의 행들과

개의 열들로 구성된다. 상기 1013단계에서 상기 제어기는 상기

개의 블록들로 분할한 패리티 검사 행렬을 정보 파트(s)와 패리티 파트, 즉 제1패리티 파트(p₁)와 제2패리티 파트(p₂)로 분류하고 1015단계 및 1021단계로 진행한다. Referring to FIG. 10, first, the controller is the size in step 1011.

The parity check matrix is divided into p blocks on the horizontal axis and q blocks on the vertical axis.

After dividing into four blocks, the process proceeds to step 1013. Here, the size of each of the blocks is

Since the parity check matrix is

Rows and

It consists of four columns. The controller in step 1013

The parity check matrix divided into four blocks is classified into an information part s and a parity part, that is, a first parity part p ₁ and a second parity part p ₂ , and the process proceeds to steps 1015 and 1021.

을 결정하고 1019단계로 진행한다. 여기서, 상기 순열 행렬

을 결정할 때는 상기 정보 파트(s) 뿐만 아니라 상기 제1패리티 파트(p₁)와 제2패리티 파트(p₂)의 블록 사이클 역시 고려해서 결정해야만 한다. In step 1015, the controller replaces the information part (s) with a nonzero block, that is, a nonzero matrix and a zero block, that is, a zero matrix, in accordance with an order distribution that ensures excellent performance of the block LDPC code. Decide and proceed to step 1017. Here, since the order distribution for ensuring the excellent performance of the block LDPC code is as described above, a detailed description thereof will be omitted. In step 1017, the controller determines that the minimum cycle length of the block cycle is as described above in the non-zero matrix portion among the blocks having the lower order among the blocks determined according to the order distribution ensuring the excellent performance of the block LDPC code. Permutation matrix to be maximum

Determine and proceed to step 1019. Where the permutation matrix

The decision must be made in consideration of not only the information part s but also the block cycles of the first parity part p ₁ and the second parity part p ₂ .

을 결정하고 종료한다. 여기서, 상기 높은 차수를 가지는 블록들중 0 행렬이 아닌 부분에 적용할 순열 행렬

을 결정할 때 역시 블록 사이클의 최소 사이클 크기가 최대가 되도록 순열 행렬

을 결정해야만 하고, 또한 상기 정보 파트(s) 뿐만 아니라 상기 제1패리티 파트(p₁)와 제2패리티 파트(p₂)의 블록 사이클 역시 고려해서 결정해야만 한다. 상기와 같이 패리티 검사 행렬의 정보 파트(s)에 순열 행렬

을 배열한 형태가 도 7에 도시되어 있다.In step 1019, the controller randomly permutes a non-zero matrix of blocks having a high degree among blocks determined according to an order distribution that ensures excellent performance of the block LDPC code.

Determine and exit. Here, the permutation matrix to be applied to the portion other than the zero matrix of the high order blocks

The permutation matrix so that the minimum cycle size of the block cycle is also maximum when

And the block cycles of the first parity part p ₁ and the second parity part p ₂ as well as the information part s. The permutation matrix in the information part (s) of the parity check matrix as described above.

Arranged form is shown in FIG.

을 입력하고 1025단계로 진행한다. 여기서, 상기 부분 행렬 B를 구성하는 부분 블록들중 2개의 부분 블록들에 0이 아닌 순열 행렬 P^y와

를 입력하는 구조는 이미 도 9에서 설명한 바가 있다.On the other hand, in step 1021, the controller divides the parity part, that is, the first parity part p ₁ and the second parity part p ₂ into four partial matrices, namely, partial matrix B, partial matrix T, and partial. After dividing the matrix D and the partial matrix E, the process proceeds to step 1023. In step 1023, the controller determines a non-zero permutation matrix P ^y from two partial blocks of the partial blocks constituting the partial matrix B.

Enter and proceed to step 1025. Here, the non-zero permutation matrix P ^y and two of the partial blocks constituting the partial matrix B and

The structure for inputting has already been described with reference to FIG. 9.

을 입력하고 1027단계로 진행한다. 여기서, 상기 부분 행렬 T의 대각 부분 블록들에는 항등 행렬 I를 입력하고, 상기 부분 행렬 T의 대각 성분들 아래의 (i, i+1)번째 부분 블록들에는 임의의 순열 행렬

을 입력하는 구조는 이미 도 9에서 설명한 바가 있다.In step 1025, the controller inputs an identity matrix I to diagonal partial blocks of the partial matrix T, and random permutation matrix to the (i, i + 1) th partial blocks below the diagonal components of the partial matrix T.

Enter and proceed to step 1027. Here, an identity matrix I is input to diagonal partial blocks of the partial matrix T, and an arbitrary permutation matrix is included in the (i, i + 1) th partial blocks below the diagonal components of the partial matrix T.

The structure for inputting has already been described with reference to FIG. 9.

를 입력하고 1029단계로 진행한다. 상기 1029단계에서 상기 제어기는 상기 부분 행렬 E에는 마지막 부분 블록에만

를 입력하고 종료한다. 여기서, 상기 부분 행렬 E를 구성하는 부분 블록들중 마지막 부분 블록에 2개의

를 입력하는 구조는 이미 도 9에서 설명한 바가 있다.In step 1027, the controller performs a permutation matrix on the partial matrix D.

And proceed to step 1029. In step 1029, the controller selects only the last partial block in the partial matrix E.

And exit. Here, two of the partial blocks constituting the partial matrix E are located in the last partial block.

The structure for inputting has already been described with reference to FIG. 9.

As described above, the LDPC code is known to have a good performance gain in high-speed data transmission together with the tab code, and has an advantage of effectively correcting an error due to noise generated in a transmission channel, thereby increasing reliability of data transmission. However, the LDPC code has a disadvantage in terms of coding rate. That is, since the LDPC code has a relatively high coding rate, the LDPC code is not free in terms of coding rate. Most of the LDPC codes currently proposed have a code rate of 1/2, and only a part has a code rate of 1/3. As such, the limitations in terms of coding rate result in a fatal effect on high-speed large data capacity transmission. Of course, in order to implement a relatively low coding rate, a method such as density evolution may be used to obtain an order distribution indicating an optimal performance, but an LDPC code having an order distribution indicating the optimal performance may be obtained. This is difficult due to various constraints such as the cycle structure on the factor graph and the hardware implementation.

Accordingly, an object of the present invention is to provide an apparatus and method for encoding / decoding an LDPC code having a variable block length in a mobile communication system.

Another object of the present invention is to provide an apparatus and method for encoding / decoding an LDPC code having a variable block length with a minimum coding complexity in a mobile communication system.

The method of the present invention for achieving the above objects; A parity check matrix of a block low density parity check (LDPC) code is composed of an information part corresponding to an information word, a first parity part and a second parity part corresponding to parity, and improve error correction performance. A method of generating the parity check matrix for the first code, comprising: a code rate applied when the information word is encoded into the block LDPC code and a codeword length of the block LDPC code can be supported at the code rate A first process of determining a size of a first parity check matrix so as to correspond to a length, a second process of dividing the first parity check matrix of the determined size into a predetermined number of blocks; A third classification into blocks corresponding to the part, blocks corresponding to the first parity part, and blocks corresponding to the second parity part And permutation matrices in predetermined blocks among the blocks classified into the first parity part, and permutation matrices in a completely lower triangular shape in the predetermined blocks among the blocks classified into the second parity part. A fourth process and a fifth process of arranging the permutation matrices such that the minimum cycle length on the factor graph of the block LDPC code becomes a preset first cycle length and blocks are non-uniform in weight classified into the information parts. It is characterized by.

Another method of the present invention for achieving the above objects is; A method for decoding a block low density parity check (LDPC) code, the method comprising: generating the parity check matrix including an information part corresponding to an information word and a first parity part and a second parity part corresponding to parity. Determining a deinterleaving scheme and an interleaving scheme corresponding to the parity check matrix, detecting probability values of a received signal, subtracting a signal generated during a previous decoding from probability values of the received signal, and performing a first signal Generating a signal; deinterleaving the first signal by inputting the first signal; detecting a probability value by inputting the deinterleaved signal; and detecting the probability values using the deinterleaved signal. Subtracting the interleaved signal to generate a second signal, and interleaving the second signal by the interleaving method And repeatedly decoding the interleaved signal.

The apparatus of the present invention for achieving the above objects; In the decoding device of a block low density parity check (LDPC) code, the parity includes an information part corresponding to an information word, a first parity part corresponding to a parity, and a second parity part according to a predetermined control. Variable node decoder that detects and outputs the probability values of the received signal by connecting variable nodes corresponding to the weights of the columns constituting the test matrix, and subtracts the signal generated during the previous decoding from the signal output from the variable node decoder. A deinterleaver for inputting a first adder, a signal output from the first adder and deinterleaving the deinterleaving method according to the parity check matrix, and outputting the deinterleaver, and rows forming the parity check matrix according to a predetermined control; Check nodes are connected to the corresponding weights and output from the deinterleaver. A parity check matrix, a check node decoder for detecting and outputting probability values of a signal, a second adder subtracting a signal output from the deinterleaver from a signal output from the check node decoder, and a signal output from the second adder An interleaver for interleaving in the interleaving scheme set according to the interleaving scheme, and outputting the parity check matrix to the variable node decoder and the first adder, and controlling the deinterleaving scheme and the interleaving scheme according to the parity check matrix. Characterized by including.

Hereinafter, with reference to the accompanying drawings in accordance with the present invention will be described in detail. It should be noted that in the following description, only parts necessary for understanding the operation according to the present invention will be described, and descriptions of other parts will be omitted so as not to distract from the gist of the present invention.

The present invention encodes a block Low Density Parity Check (LDPC) code having a variable block length (hereinafter referred to as an LDPC) code (hereinafter referred to as a variable length block LDPC code). An apparatus and method for coding and decoding are provided. That is, in the present invention, the length of the minimum cycle on the factor (hereinafter, referred to as 'factor') graph of the block LDPC code is maximum, and the complexity for encoding the block LDPC code is minimum, An apparatus and method for encoding and decoding a variable length block LDPC code that supports a variety of block lengths while having an optimal distribution of 1 on a factor graph of the block LDPC code.

In particular, the next generation mobile communication system has been developed in the form of a packet service communication system, and the packet service communication system is a system for transmitting burst packet data to a plurality of mobile stations. It has been designed for large data transfers. In particular, a hybrid automatic retransmission request (HARQ) scheme and an adaptive modulation and coding (AMC) scheme will be referred to as 'AMC' in order to increase the data transmission amount. Various schemes have been proposed, and since the HARQ scheme and the AMC scheme support variable coding rates, the necessity for block LDPC codes having various block lengths is highlighted.

The design of the variable length block LDPC code is implemented through the design of a parity check matrix as in the case of designing a general LDPC code. However, in order to provide a variable length block LDPC code with one codec in a mobile communication system, that is, to provide a block LDPC code having various block lengths, a block LDPC code having a different block length may be represented in the parity check matrix. It must be of a type that contains a parity check matrix. Next, a parity check matrix of a block LDPC code that provides a variable block length will be described.

First, a block LDPC code having a minimum length required by the system is designed for a set coding rate to be designed. In the parity check matrix, a block LDPC code having a long block length is generated while increasing N _s , the size of a partial matrix. Here, the partial matrix is a permutation matrix corresponding to each of the partial blocks when the parity check matrix is divided into a plurality of partial blocks as described in the prior art portion of the present invention. matrix). On the other hand, if the size of the partial matrix N _s is increased, the cycle structure is changed. Therefore, a short block LDPC code is first designed, and then a long block LDPC code is designed to be extended. Assuming the case, the exponent of the permutation matrix of the parity check matrix is selected such that the cycle is maximum.

For example, when the partial block size N _s = 2 of the basic block LDPC code, when the basic block LDPC code is to be extended to a block LDPC code having N _s = 4 of twice the length, the partial matrix of the permutation matrix has an index of 0 Is increased from N _s = 2 to N _s = 4, you can choose a value of 0 or 2. Here, one of the two values must be selected to maximize the cycle. Likewise, N _s = 2 the block LDPC code index of 1 in a partial matrix may select the value of N _s = N _s = 4 when increased from 21, or 3.

As described above, when the block LDPC code is designed while increasing the N _s value using the basic block LDPC code, the block LDPC code having the maximum performance for each block length can be designed. In addition, since any one block LDPC code of the various lengths of the block LDPC codes can be defined as a basic block LDPC code, there is a gain in terms of memory efficiency. Next, a method of generating a parity check matrix of the variable length block LDPC code will be described. In the present invention, the parity check matrix of the variable length block LDPC code is proposed in four forms corresponding to the coding rate, and the coding rates considered in the present invention are 1/2, 2/3, 3/4, and 5/6. .

On the other hand, the code rate is a parity check matrix designed in the present invention with reference to Figure 15 before explaining the parity check matrix of the variable length block LDPC code according to 1/2, 2/3, 3/4, 5/6 A process of encoding a variable length block LDPC code using the following description will be described.

15 is a flowchart illustrating a process of encoding a variable length block LDPC code according to the first to eighth embodiments of the present invention.

)를 입력받고 1513단계 및 1515단계로 진행한다. 여기서, 상기 블록 LDPC 부호로 부호화하기 위해 입력받은 정보어 벡터(

)의 길이는 k라고 가정하기로 한다. 상기 1513단계에서 상기 제어기는 상기 입력받은 정보어 벡터(

)와 패리티 검사 행렬의 부분 행렬 A를 행렬 곱셈한 후(

) 1517단계로 진행한다. 여기서, 상기 부분 행렬 A에 존재하는 1의 값을 가지는 엘리먼트들의 개수는 0의 값을 가지는 엘리먼트들의 개수에 비해서 매우 적으므로 상기 정보어 벡터(

)와 패리티 검사 행렬의 부분 행렬 A의 행렬 곱셈은 비교적 적은 횟수의 합곱(sum-product) 연산만 으로도 가능하게 된다. 또한, 상기 부분 행렬 A에서 1의 값을 가지는 엘리먼트들의 위치는 0이 아닌 블록의 위치와 그 블록의 순열 행렬의 지수승으로 나타낼 수 있으므로 임의의 패리티 검사 행렬에 비하여 매우 간단한 연산만으로도 행렬 곱셈을 수행할 수 있다. 또한, 상기 1515단계에서 상기 제어기는 상기 패리티 검사 행렬의 부분 행렬 C와 상기 정보어 벡터(

)의 행렬 곱셈을 수행하고(

) 1519단계로 진행한다. Before describing FIG. 15, it is assumed that the parity check matrix of the variable length block LDPC code is formed of six partial matrices as described with reference to FIG. 8. Referring to FIG. 15, a controller (not shown) first includes an information word vector for encoding the variable length block LDPC code in operation 1511.

) And proceed to step 1513 and 1515. Here, the information word vector received for encoding with the block LDPC code (

) Is assumed to be k. In step 1513, the controller selects the received information word vector (

) And the matrix matrix of the parity check matrix

Proceed to step 1517. Here, since the number of elements having a value of 1 in the partial matrix A is very small compared to the number of elements having a value of 0, the information word vector (

Matrix multiplication of the parity check matrix and the partial matrix A of the parity check matrix is possible only with a relatively small number of sum-product operations. In addition, since the position of elements having a value of 1 in the partial matrix A can be represented by the position of a nonzero block and the exponential power of the permutation matrix of the block, matrix multiplication is performed by a very simple operation compared to any parity check matrix. can do. In operation 1515, the controller determines that the partial matrix C of the parity check matrix and the information word vector (

Matrix multiplication of ()

Proceed to step 1519.

)와 패리티 검사 행렬의 부분 행렬 A의 행렬 곱셈 결과와 행렬 ET^-1의 행렬 곱셈을 수행하고(

) 1519단계로 진행한다. 여기서, 상기에서 설명한 바와 같이 상기 행렬 ET^-1의 1의 값을 가지는 엘리먼트들의 개수는 매우 적기 때문에 블록의 순열 행렬의 지수승만 알게되면 상기 행렬 곱셈을 용이하게 수행할 수 있다. 상기 1519단계에서 상기 제어기는 상기

와

를 가산하여 제1패리티 벡터(

)를 계산한 후(

) 1821단계로 진행한다. 여기서, 가산 연산은 배타적 가산(exclusive OR) 연산으로 동일한 비트가 가산될 때는 0이 되고 상이한 비트가 가산될 때는 1이 된다. 결국, 상기 1519단계까지의 과정은 제1패리티 벡터(

)를 계산하기 위한 과정인 것이다. On the other hand, in step 1517 the controller is the information word vector (

) And the matrix multiplication of the parity check matrix submatrix A and the matrix ET ^-1 (

Proceed to step 1519. As described above, since the number of elements having a value of 1 of the matrix ET ^-1 is very small, the matrix multiplication can be easily performed when only the exponential power of the permutation matrix of the block is known. The controller in step 1519

Wow

By adding the first parity vector (

After calculating

Proceed to step 1821. Here, the addition operation is an exclusive OR operation, which is 0 when the same bit is added and 1 when different bits are added. As a result, the process up to step 1519 may include a first parity vector (

) Is to calculate

)를 곱셈한 후

를 가산한 후 1523단계로 진행한다. 여기서, 상기 정보어 벡터(

)와 제1패리티 벡터(

)를 알면, 제2패리티 벡터(

)를 구하기 위해 상기 패리티 검사 행렬의 부분 행렬 T의 역행렬 T^-1을 행렬 곱해야한다. 따라서, 상기 1523단계에서 상기 제어기는 상기 제2패리티 벡터(

)를 구하기 위해서 상기 1521단계에서 계산한 벡터에 상기 부분 행렬 T의 역행렬 T^-1을 곱한 후(

) 1525단계로 진행한다. 상기에서 설명한 바와 같이 부호화하고자 하는 블록 LDPC 부호의 정보어 벡터(

)만을 알면 제1패리티 벡터(

)와, 제2패리티 벡터(

)를 구할수 있고, 결과적으로 부호어 벡터 모두를 얻을 수 있는 것이다. 그리고, 상기 제어기는 1525단계에서 상기 정보어 벡터(

)와, 제1패리티 벡터(

)와, 제2패리티 벡터(

)로 생성된 부호어 벡터(

)를 생성하여 전송하고 종료한다. In step 1521, the controller determines that the partial matrix B of the parity check matrix and the first parity vector (

) Then multiply

After adding, proceed to step 1523. Here, the information word vector (

) And the first parity vector (

), The second parity vector (

) To be the inverse matrix T ^-1 of a partial matrix T of the parity check matrix must be multiplied to obtain the matrix. Accordingly, in step 1523, the controller determines the second parity vector (

Multiplying the vector calculated in step 1521 by the inverse T- ¹ of the partial matrix T

Proceed to step 1525. As described above, the information word vector of the block LDPC code to be encoded

) Only the first parity vector (

) And the second parity vector (

), And as a result, we can get all the codeword vectors. In operation 1525, the controller determines the information vector (

) And the first parity vector (

) And the second parity vector (

Codeword vector generated by

Create, send and exit.

Next, an internal structure of a coding apparatus of a variable length block LDPC code for performing functions in the first to eighth embodiments of the present invention will be described with reference to FIG.

16 is a block diagram illustrating an internal structure of an apparatus for encoding a variable length block LDPC code for performing a function in embodiments of the present invention.

Referring to FIG. 16, the apparatus of encoding a variable length block LDPC code includes a matrix A multiplier 1611, a matrix C multiplier 1613, a matrix ET ⁻¹ multiplier 1615, an adder 1617, and a matrix. B multiplier 1619, adder 1621, matrix ET- ¹ multiplier 1623, and switches 1625, 1627, 1629.

)가 입력되고, 상기 입력된 길이 k의 정보어 벡터(

)는 상기 스위치(1625)와, 행렬 A 곱셈기(1611)와, 행렬 C 곱셈기(1613)로 입력된다. 상기 행렬 A 곱셈기(1611)는 상기 정보어 벡터(

)와 전체 패리티 검사 행렬의 부분 행렬 A를 곱한 후 행렬 ET^-1 곱셈기(1615)와 상기 가산기(1621)로 출력한다. 또한, 상기 행렬 C 곱셈기(1613)는 상기 정보어 벡터(

)와 전체 패리티 검사 행렬의 부분 행렬 C를 곱한 후 상기 가산기(1617)로 출력한다. 상기 행렬 ET^-1 곱셈기(1615)는 상기 행렬 A 곱셈기(1611)에서 출력한 신호에 전체 패리티 검사 행렬의 부분 행렬 ET^-1를 곱한 후 상기 가산기(1617)로 출력한다. First, an information word vector of length k to be encoded into an input signal, that is, a variable length block LDPC code (

) Is input, and the information word vector of the input length k (

) Is input to the switch 1625, the matrix A multiplier 1611, and the matrix C multiplier 1613. The matrix A multiplier 1611 uses the information vector (

) Is multiplied by the partial matrix A of the entire parity check matrix, and then output to the matrix ET ^-1 multiplier 1615 and the adder 1621. In addition, the matrix C multiplier (1613) is the information word vector (

) Is multiplied by the partial matrix C of the parity check matrix and output to the adder 1617. The matrix ET ^-1 multiplier 1615 multiplies the signal output from the matrix A multiplier 1611 by the partial matrix ET ^-1 of the entire parity check matrix and outputs the multiplier 1617 to the adder 1617.

를 출력한다. 여기서, 상기

연산은 동일한 비트가 연산되면 0이 되고, 상이한 비트가 연산되면 1이 되는 배타적 논리합 연산을 나타낸다. 결국, 상기 가산기(1617)에서 출력하는 신호가 제1패리티 벡터(

)가 되는 것이다. The adder 1617 inputs and adds the signal output from the matrix ET ^-1 multiplier 1615 and the signal output from the matrix C multiplier 1613, and then adds the signal to the matrix B multiplier 1619 and the switch 1627. Output Here, the adder 1617 performs an exclusive OR operation for each bit. For example, when a vector of length 3 x = (x ₁ , x ₂ , x ₃ ) and a vector of length y = (y ₁ , y ₂ , y ₃ ) are input to the adder 1617, the adder ( 1617) performs an exclusive OR on the vector of length 3, x = (x ₁ , x ₂ , x ₃ ) and the length of vector y = (y ₁ , y ₂ , y ₃ ).

Outputs Where

An operation represents an exclusive OR operation, which is 0 when the same bit is operated on, and 1 when different bits are operated on. As a result, the signal output from the adder 1617 becomes the first parity vector (

)

)를 입력하여 상기 전체 패리티 검사 행렬의 부분 행렬 B를 곱한 후 상기 가산기(1621)로 출력한다. 상기 가산기(1621)는 상기 행렬 B 곱셈기(1619)에서 출력한 신호와 상기 행렬 A 곱셈기(1611)에서 출력한 신호를 가산한 후 상기 행렬 ET^-1 곱셈기(1623)로 출력한다. 여기서, 상기 가산기(1621)는 상기 가산기(1617)에서 설명한 바와 같이 상기 행렬 B 곱셈기(1619)에서 출력한 신호와 상기 행렬 A 곱셈기(1611)에서 출력한 신호를 배타적 논리합 연산한 후 상기 행렬 ET^-1 곱셈기(1623)로 출력하는 것이다.In addition, the matrix B multiplier 1619 outputs a signal output from the adder 1617, that is, a first parity vector (

) Is multiplied by the partial matrix B of the entire parity check matrix and output to the adder 1621. The adder 1621 adds the signal output from the matrix B multiplier 1619 and the signal output from the matrix A multiplier 1611 and outputs the result to the matrix ET ^-1 multiplier 1623. Here, the adder 1621 performs an exclusive OR on the signal output from the matrix B multiplier 1619 and the signal output from the matrix A multiplier 1611 as described in the adder 1617, and then performs the matrix ET ^{−. It} is output to the ¹ multiplier (1623).

)가 되는 것이다. 한편, 상기 스위치들(1625, 1627, 1629) 각각은 자신이 전송하는 시점에서만 스위칭 온(switching on)되어 해당 신호를 전송하도록 한다. 즉, 상기 정보어 벡터(

)가 전송되는 시점에서는 상기 스위치(1625)가 스위칭 온되고, 상기 제1패리티 벡터(

)가 전송되는 시점에서는 상기 스위치(1627)가 스위칭 온되고, 상기 제2패리티 벡터(

)가 전송되는 시점에서는 상기 스위치(1629)가 스위칭 온되는 것이다.The matrix ET ^-1 multiplier 1623 multiplies the signal output from the adder 1621 by the matrix ET ^-1 and outputs the result to the switch 1629. Here, the output of the matrix ET ^-1 multiplier 1623 eventually results in a second parity vector (

) On the other hand, each of the switches 1625, 1627, 1629 are switched on only at the time of their transmission to transmit the corresponding signal. That is, the information word vector (

Is transmitted, the switch 1625 is switched on and the first parity vector (

Is transmitted, the switch 1627 is switched on and the second parity vector (

Is transmitted, the switch 1629 is switched on.

In the above, a method of generating a variable length block LDPC code considering efficient encoding has been described. As described above, the variable length block LDPC code is excellent in memory efficiency for storing information related to the parity check matrix according to the structural characteristics of the variable length block LDPC code, and by appropriately selecting a partial matrix from the parity check matrix. Efficient coding becomes possible. However, as the parity check matrix is generated on a block basis, randomness is reduced, and the reduction of the irregularity may cause degradation of the performance of the block LDPC code. That is, as described above, since the nonuniform block LDPC code has better performance than the uniform block LDPC code, it is very important to select the partial matrix from the entire parity check matrix when designing the block LDPC code.

Next, a concrete generation method of the variable length block LDPC code at the code rate 1/2 will be described with reference to FIG. 11.

11 is a diagram illustrating a parity check matrix of a variable length block LDPC code according to the first embodiment of the present invention.

Before describing FIG. 11, the first embodiment of the present invention proposes a parity check matrix of a variable length block LDPC code when the coding rate is 1/2. Referring to FIG. 11, when the N _s value, which is the size of the partial matrix, is assumed to be 4, 8, 12, 16, 20, 24, 32, 36, and 40, the parity check matrix as shown in FIG. Block LDPC codes having lengths of 96, 192, 288, 384, 480, 576, 672, 768, 864, and 960 can be generated. A value written in each of the blocks, ie, partial matrices, illustrated in FIG. 11 represents an exponent value of a permutation matrix. Accordingly, when a modulo operation of an N _s value corresponding to the size of the partial matrix is modulated to an index value of the permutation matrix, a permutation matrix index value of a parity check matrix of a block LDPC code having the N _s value may be obtained. . Here, when the index of the permutation matrix is modulo operation with the N _s value, and the result value is 0, the permutation matrix becomes an identity matrix.

Next, a specific generation method of the variable length block LDPC code at the code rate 2/3 will be described with reference to FIG. 12.

12 is a diagram illustrating a parity check matrix of a variable length block LDPC code according to a second embodiment of the present invention.

12, the second embodiment of the present invention proposes a parity check matrix of a variable length block LDPC code when the coding rate is 2/3. Referring to FIG. 12, when assuming that N _s , the size of the partial matrix, is 8,16, a block LDPC code having a length of 288 and 576 is generated using a parity check matrix as shown in FIG. 12. Can be. A value written in each of the blocks, ie, partial matrices, illustrated in FIG. 12 represents an exponent value of a permutation matrix. Accordingly, when the N _s value corresponding to the size of the partial matrix is modulated by the index value of the permutation matrix, the permutation matrix index value of the parity check matrix of the block LDPC code having the N _s value can be obtained. Here, when the index of the permutation matrix is modulo operation with the N _s value, and the result value is 0, the permutation matrix becomes an identity matrix.

Next, a specific generation method of the variable length block LDPC code when the code rate is 3/4 will be described with reference to FIG. 13.

13 is a diagram illustrating a parity check matrix of a variable length block LDPC code according to a third embodiment of the present invention.

Before describing FIG. 13, the third embodiment of the present invention proposes a parity check matrix of a variable length block LDPC code when a coding rate is 3/4. Referring to FIG. 13, if it is assumed that the value of N _s , which is the size of the partial matrix, is 3, 6, 9, 12, 15, or 18, the length 96, using the parity check matrix as shown in FIG. Variable length block LDPC codes of 192, 288, 384, 480, and 576 may be generated. A value written in each of the blocks illustrated in FIG. 13, that is, partial matrixes, indicates an exponent value of a permutation matrix. Accordingly, when the N _s value corresponding to the size of the partial matrix is modulated by the index value of the permutation matrix, the permutation matrix index value of the parity check matrix of the block LDPC code having the N _s value can be obtained. Here, when the index of the permutation matrix is modulo operation with the N _s value, and the result value is 0, the permutation matrix becomes an identity matrix.

Next, a specific generation method of the variable length block LDPC code when the code rate is 5/6 will be described with reference to FIG. 14.

14 illustrates a parity check matrix of a variable length block LDPC code according to a fourth embodiment of the present invention.

Before describing FIG. 14, the fourth embodiment of the present invention proposes a parity check matrix of a variable length block LDPC code when a coding rate is 5/6. Referring to FIG. 14, first, when assuming that N _s values of the partial matrix are 8 and 16, a block LDPC code having lengths 288 and 576 may be generated using a parity check matrix as shown in FIG. 14. Can be. A value written in each of the blocks, ie, partial matrices, illustrated in FIG. 14 represents an exponent value of a permutation matrix. Accordingly, when the N _s value corresponding to the size of the partial matrix is modulated by the index value of the permutation matrix, the permutation matrix index value of the parity check matrix of the block LDPC code having the N _s value can be obtained. Here, when the index of the permutation matrix is modulo operation with the N _s value, and the result value is 0, the permutation matrix becomes an identity matrix.

Next, a specific generation method of the variable length block LDPC code at the code rate 1/2 will be described with reference to FIG. 18.

18 is a diagram illustrating a parity check matrix of a variable length block LDPC code according to a fifth embodiment of the present invention.

Before describing FIG. 18, the first embodiment of the present invention proposes a parity check matrix of a variable length block LDPC code when the coding rate is 1/2. Referring to FIG. 18, a block LDPC code having a length of 48N _s may be generated according to an N _s value of the size of the partial matrix using the illustrated parity check matrix. A value written in each of the partial blocks, i.e., partial matrices, illustrated in FIG. 18 represents an exponent value of a permutation matrix. Accordingly, when the N _s value corresponding to the size of the partial matrix is modulated by the index value of the permutation matrix, the permutation matrix index value of the parity check matrix of the block LDPC code having the N _s value can be obtained. Here, when the index of the permutation matrix is modulo operation with the N _s value, and the result value is 0, the permutation matrix becomes an identity matrix.

Next, with reference to FIG. 19, a concrete generation method of the variable length block LDPC code when the code rate is 2/3 will be described.

19 illustrates a parity check matrix of a variable length block LDPC code according to a sixth embodiment of the present invention.

Before describing FIG. 19, the sixth embodiment of the present invention proposes a parity check matrix of a variable length block LDPC code when a coding rate is 2/3. Referring to FIG. 19, a block LDPC code having a length of 48N _s may be generated according to an N _s value of the size of the partial matrix using the illustrated parity check matrix. The values written in each of the blocks, ie, partial matrices, illustrated in FIG. 19 represent exponent values of the permutation matrix. Accordingly, when the N _s value corresponding to the size of the partial matrix is modulated by the index value of the permutation matrix, the permutation matrix index value of the parity check matrix of the block LDPC code having the N _s value can be obtained. Here, when the index of the permutation matrix is modulo operation with the N _s value, and the result value is 0, the permutation matrix becomes an identity matrix.

Next, a specific generation method of the variable length block LDPC code when the code rate is 3/4 will be described with reference to FIG. 20.

20 illustrates a parity check matrix of a variable length block LDPC code according to a seventh embodiment of the present invention.                     

20, the seventh embodiment of the present invention proposes a parity check matrix of a variable length block LDPC code when a coding rate is 3/4. Referring to FIG. 20, a block LDPC code having a length of 48N _s may be generated according to an N _s value of the size of the partial matrix using the illustrated parity check matrix. A value written in each of the partial blocks, i.e., partial matrixes, illustrated in FIG. 20 represents an exponent value of a permutation matrix. Accordingly, when the N _s value corresponding to the size of the partial matrix is modulated by the index value of the permutation matrix, the permutation matrix index value of the parity check matrix of the block LDPC code having the N _s value can be obtained. Here, when the index of the permutation matrix is modulo operation with the N _s value, and the result value is 0, the permutation matrix becomes an identity matrix.

Next, a specific generation method of the variable length block LDPC code when the code rate is 3/4 will be described with reference to FIG. 21.

21 is a diagram illustrating a parity check matrix of a variable length block LDPC code according to an eighth embodiment of the present invention.

Before describing FIG. 21, the eighth embodiment of the present invention proposes a parity check matrix of a variable length block LDPC code when the coding rate is 3/4. Referring to FIG. 21, a block LDPC code having a length of 48N _s may be generated according to an N _s value of the size of the partial matrix using the illustrated parity check matrix. A value written in each of the blocks, ie, partial matrices, illustrated in FIG. 21 represents an exponent value of a permutation matrix. Accordingly, when the N _s value corresponding to the size of the partial matrix is modulated by the index value of the permutation matrix, the permutation matrix index value of the parity check matrix of the block LDPC code having the N _s value can be obtained. Here, when the index of the permutation matrix is modulo operation with the N _s value, and the result value is 0, the permutation matrix becomes an identity matrix.

Next, a specific generation method of the variable length block LDPC code at the code rate 1/2 will be described with reference to FIG. 22.

22 is a diagram illustrating a parity check matrix of a variable length block LDPC code according to a ninth embodiment of the present invention.

Before describing FIG. 22, the ninth embodiment of the present invention proposes a parity check matrix of a variable length block LDPC code when a coding rate is 1/2. Referring to FIG. 22, a block LDPC code having a length of 24N _s may be generated according to an N _s value of the size of the partial matrix using the illustrated parity check matrix. A value written in each of the blocks illustrated in FIG. 22, that is, the partial matrices represents an exponent value of the permutation matrix. Accordingly, when the N _s value corresponding to the size of the partial matrix is modulated by the index value of the permutation matrix, the permutation matrix index value of the parity check matrix of the block LDPC code having the N _s value can be obtained. Here, when the index of the permutation matrix is modulo operation with the N _s value, and the result value is 0, the permutation matrix becomes an identity matrix.

Next, a specific generation method of the variable length block LDPC code at the code rate 1/2 will be described with reference to FIG. 23.

23 is a diagram illustrating a parity check matrix of a variable length block LDPC code according to a tenth embodiment of the present invention.

Before describing FIG. 23, the tenth embodiment of the present invention proposes a parity check matrix of a variable length block LDPC code when a coding rate is 1/2. Referring to FIG. 23, a block LDPC code having a length of 24N _s may be generated according to an N _s value of the size of the partial matrix using the illustrated parity check matrix. A value written in each of the blocks illustrated in FIG. 23, that is, the partial matrices represents an exponent value of the permutation matrix. Accordingly, when the N _s value corresponding to the size of the partial matrix is modulated by the index value of the permutation matrix, the permutation matrix index value of the parity check matrix of the block LDPC code having the N _s value can be obtained. Here, when the index of the permutation matrix is modulo operation with the N _s value, and the result value is 0, the permutation matrix becomes an identity matrix.

Next, a specific generation method of the variable length block LDPC code at the code rate 2/3 will be described with reference to FIG. 24.

24 is a diagram illustrating a parity check matrix of a variable length block LDPC code according to an eleventh embodiment of the present invention.                     

Before describing FIG. 24, the eleventh embodiment of the present invention proposes a parity check matrix of a variable length block LDPC code when a coding rate is 2/3. Referring to FIG. 24, a block LDPC code having a length of 24N _s may be generated according to an N _s value of the size of the partial matrix using the illustrated parity check matrix. The values written in each of the blocks illustrated in FIG. 24, that is, the partial matrices, represent exponent values of the permutation matrix. Accordingly, when the N _s value corresponding to the size of the partial matrix is modulated by the index value of the permutation matrix, the permutation matrix index value of the parity check matrix of the block LDPC code having the N _s value can be obtained. Here, when the index of the permutation matrix is modulo operation with the N _s value, and the result value is 0, the permutation matrix becomes an identity matrix.

Next, a method of generating a variable length block LDPC code at a code rate of 2/3 will be described with reference to FIG. 25.

25 is a diagram illustrating a parity check matrix of a variable length block LDPC code according to a twelfth embodiment of the present invention.

25, a twelfth embodiment of the present invention proposes a parity check matrix of a variable length block LDPC code when a coding rate is 2/3. Referring to FIG. 25, a block LDPC code having a length of 24N _s may be generated according to an N _s value of the size of the partial matrix using the illustrated parity check matrix. A value written in each of the blocks illustrated in FIG. 25, that is, the partial matrices represents an exponent value of the permutation matrix. Accordingly, when the N _s value corresponding to the size of the partial matrix is modulated by the index value of the permutation matrix, the permutation matrix index value of the parity check matrix of the block LDPC code having the N _s value can be obtained. Here, when the index of the permutation matrix is modulo operation with the N _s value, and the result value is 0, the permutation matrix becomes an identity matrix.

Next, a specific generation method of the variable length block LDPC code when the coding rate is 1/2 will be described with reference to FIG. 26.

26 is a diagram illustrating a parity check matrix of a variable length block LDPC code according to a thirteenth embodiment of the present invention.

Before describing FIG. 26, the thirteenth embodiment of the present invention proposes a parity check matrix of a variable length block LDPC code when a coding rate is 1/2. Referring to FIG. 26, a block LDPC code having a length of 24N _s may be generated according to an N _s value of the size of the partial matrix using the illustrated parity check matrix. The values written in each of the blocks illustrated in FIG. 26, that is, partial matrixes, represent exponent values of the permutation matrix. Accordingly, when the N _s value corresponding to the size of the partial matrix is modulated by the index value of the permutation matrix, the permutation matrix index value of the parity check matrix of the block LDPC code having the N _s value can be obtained. Here, when the index of the permutation matrix is modulo operation with the N _s value, and the result value is 0, the permutation matrix becomes an identity matrix.

Next, a specific generation method of the variable length block LDPC code at the code rate 1/2 will be described with reference to FIG. 27.

27 illustrates a parity check matrix of a variable length block LDPC code according to a fourteenth embodiment of the present invention.

27, a fourteenth embodiment of the present invention proposes a parity check matrix of a variable length block LDPC code when a coding rate is 1/2. Referring to FIG. 27, a block LDPC code having a length of 24N _s may be generated according to an N _s value of the size of the partial matrix using the illustrated parity check matrix. The values written in each of the blocks illustrated in FIG. 27, that is, partial matrixes, represent exponent values of the permutation matrix. Accordingly, when the N _s value corresponding to the size of the partial matrix is modulated by the index value of the permutation matrix, the permutation matrix index value of the parity check matrix of the block LDPC code having the N _s value can be obtained. Here, when the index of the permutation matrix is modulo operation with the N _s value, and the result value is 0, the permutation matrix becomes an identity matrix.

Next, a specific generation method of the variable length block LDPC code when the code rate is 2/3 will be described with reference to FIG. 28.

28 illustrates a parity check matrix of a variable length block LDPC code according to a fifteenth embodiment of the present invention.                     

28, the fifteenth embodiment of the present invention proposes a parity check matrix of a variable length block LDPC code when a code rate is 2/3. Referring to FIG. 28, a block LDPC code having a length of 24N _s may be generated according to an N _s value of a size of a partial block using the illustrated parity check matrix. The values written in each of the partial blocks, that is, the partial matrices illustrated in FIG. 28, represent exponent values of the permutation matrix. Accordingly, when the N _s value corresponding to the size of the partial matrix is modulated by the index value of the permutation matrix, the permutation matrix index value of the parity check matrix of the block LDPC code having the N _s value can be obtained. Here, when the index of the permutation matrix is modulo operation with the N _s value, and the result value is 0, the permutation matrix becomes an identity matrix.

Meanwhile, all codes of the LDPC code sequence can be decoded by a sum-product algorithm on a factor graph. The decoding method of the LDPC code can be largely classified into a bidirectional transfer method and a flow transfer method. When the decoding operation is performed by the bidirectional transfer method, a node processor per check node is present so that the complexity of the decoder becomes complicated in proportion to the number of check nodes, but all nodes are updated at the same time. The decoding speed is very fast.

In contrast, the flow transfer method has a single node processor, which updates information by passing through nodes on all factor graphs. Therefore, the complexity of the decoder is simplified, but as the size of the parity check matrix increases, that is, as the number of nodes increases, the decoding speed becomes slow. However, when a parity check matrix is generated in units of blocks, such as a variable length block LDPC code having various block lengths corresponding to the code rate proposed by the present invention, as many nodes as the number of blocks constituting the parity check matrix are decoded. The processor reduces the complexity of the decoder rather than the bidirectional delivery scheme, and can implement a decoder having a faster decoding speed than the flow transfer scheme.

Next, an internal structure of a decoding apparatus for decoding a variable length block LDPC code using a parity check matrix according to embodiments of the present invention will be described with reference to FIG. 17.

Referring to FIG. 17, the apparatus for decoding a variable length block LDPC code includes a block controller 1710, a variable node part 1700, an adder 1715, and a de-interleaver ( 1717, an interleaver 1725, a controller 1721, a memory 1723, an adder 1725, an inspection node part 1750, and a hard determiner 1729. The variable node part 1700 includes a variable node decoder 1711 and switches 1713 and 1714, and the check node part 1750 includes a check node decoder 1727.

First, a received signal received through a wireless channel is input to the block controller 1710. The block controller 1710 determines the block size of the received signal, and if there is a punctured information word portion in the encoding apparatus corresponding to the decoding apparatus, the block controller 1710 inserts 0 into the punctured information word portion to determine the total block size. After the control is adjusted, the variable node decoder 1711 is output.

The variable node decoder 1711 inputs a signal output from the block controller 1710, calculates probability values of the signal output from the block controller 1710, updates the calculated probability values, and then switches the switch ( 1713 and the switch 1714. Here, the variable node decoder 1711 connects variable nodes corresponding to a parity check matrix preset in the decoding apparatus of the nonuniform block LDPC code, and inputs as many as 1 input values connected to the variable nodes. An update operation with an output value is performed. The number of 1s connected to each of the variable nodes is equal to the weight of each of the columns constituting the parity check matrix. Therefore, the internal operation of the variable node decoder 1711 is different according to the weight of each column constituting the parity check matrix. The switch 1714 is switched on except for when the switch 1713 is switched on, that is, only when the switch 1713 is switched off, and outputs a signal output from the block controller 1710 to the adder ( 1715).

The adder 1715 inputs the signal output from the variable node decoder 1711 and the output signal of the interleaver 1917 during a previous iteration decoding process, and the variable node decoder 1711 The output signal of the interleaver 1719 in the previous iterative decoding process is subtracted from the output signal and then output to the deinterleaver 1917. Here, of course, when the decoding process is the first decoding process, the output signal of the interleaver 1719 should be regarded as 0.

The deinterleaver 1725 receives the signal output from the adder 1715 and de-interleaves the signal according to a preset setting method, and then the adder 1725 and the check node decoder 1727. Will output Here, the internal structure of the deinterleaver 1917 has a structure corresponding to the parity check matrix, for the reason that the deinterleaver 1917 corresponds to the position of elements having a value of 1 in the parity check matrix. This is because the output value with respect to the input value of the interleaver 1917 is different.

The adder 1725 receives an output signal of the check node decoder 1727 and an output signal of the deinterleaver 1725 in a previous iterative decoding process, and adds the check node decoder in the previous iterative decoding process ( The output signal of the deinterleaver 1917 is subtracted from the output signal of 1727 and then output to the interleaver 1917. The check node decoder 1725 connects check nodes according to a parity check matrix preset in the decoding apparatus of the block LDPC code, and has an input value and an output value equal to 1 connected to the check nodes. Update operation is performed. The number of 1s connected to each of the check nodes is equal to the weight of each of the rows constituting the parity check matrix. Therefore, the internal operation of the check node decoder 1725 is different according to the weight of each of the rows constituting the parity check matrix.

Here, the interleaver 1725 interleaves the signal output from the adder 1725 in a preset manner according to the control of the controller 1721, and then adds the adder 1715 and the variable node decoder ( 1711). Herein, the controller 1721 reads information related to the interleaving scheme stored in the memory 1723 to control the interleaving scheme of the interleaver 1719. In addition, when the decoding process is the first decoding process, the output signal of the deinterleaver 1917 should be regarded as 0.

By repeatedly performing the above processes, a reliable decoding is performed without error. After performing the repeated decoding corresponding to a preset number of preset repetitions, the switch 1713 performs the variable node decoder 1711 and the adder. After switching off the signal 1715, the signal output from the variable node decoder 1711 is switched on between the variable node decoder 1711 and the hard determiner 1729. 1729). The hard determiner 1729 inputs the signal output from the variable node decoder 1711 to make a hard decision, and then outputs the hard decision result. The output value of the hard determiner 1729 is finally decoded. Will be.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

 As described above, the present invention has the advantage of improving system performance by maximizing error correction capability by proposing a variable length block LDPC code having a maximum minimum cycle length in a mobile communication system. In addition, the present invention has the advantage of minimizing the coding complexity of the variable length block LDPC code by generating an efficient parity check matrix. In addition, the coding complexity of the variable length block LDPC code is made proportional to the block length, thereby enabling efficient encoding. In particular, the present invention has an advantage of minimizing hardware complexity by enabling generation of block LDPC codes having various block lengths while being applicable to various coding rates.

Claims (55)

A parity check matrix of a block low density parity check (LDPC) code is composed of an information part corresponding to an information word, a first parity part and a second parity part corresponding to parity, and improve error correction performance. In the method for generating the parity check matrix for: A size of a first parity check matrix such that a code rate applied when the information word is encoded into the block LDPC code and a codeword length of the block LDPC code correspond to a preset first codeword length supported by the code rate The first process of determining A second process of dividing the first parity check matrix of the determined size into blocks of a preset number; A third process of classifying the blocks into blocks corresponding to the information part, blocks corresponding to the first parity part, and blocks corresponding to the second parity part; A fourth arrangement in which the permutation matrices are arranged in predetermined blocks among the blocks classified as the first parity part, and the permutation matrices in a completely lower triangular shape in the predetermined blocks among the blocks classified as the second parity part. Process, And a fifth process of arranging the permutation matrices such that the minimum cycle length on the factor graph of the block LDPC code becomes a preset first cycle length to blocks classified as the information part, and the weight is non-uniform. The method. The method of claim 1, A sixth process of generating a first parity check matrix and determining a size of a second parity check matrix such that the information word corresponds to the coding rate and the length of the second codeword set in advance to the length of the block LDPC code; and, A seventh process of dividing the second parity check matrix of the determined size into blocks of the predetermined number; An eighth process of classifying the blocks divided in the seventh process into blocks corresponding to the information part, blocks corresponding to the first parity part, and blocks corresponding to the second parity part; Arranged in predetermined blocks among blocks classified as the first parity part in the eighth process and arranged in the predetermined blocks among blocks classified as the first parity part of the first parity check matrix in the fourth process. Permutation matrices having exponents obtained by modulating the exponents of the permutation matrices by the size of the block. The ninth process of arranging the matrices, In the eighth step, the minimum cycle length on the factor graph of the block LDPC code becomes the preset second cycle length to the blocks classified as the information part, and is classified as the information part of the first parity check matrix such that the weight is nonuniform. And a tenth step of generating the second parity check matrix by arranging the permutation matrices having an exponent of the exponential permutation matrices arranged in the divided blocks by the size of the block. Way. The method of claim 1, The permutation matrices arranged in the full lower triangular form in the fourth process are identity matrices. The method of claim 2, The permutation matrices arranged in the full lower triangular form in the ninth process are identity matrices. The method of claim 1, The first parity check matrix is expressed as shown in Table 1 below when the coding rate is 1/2.

Numbers in Table 1 represent the exponent of the permutation matrix, I is an index indicating that the exponent of the permutation matrix is zero. The method of claim 1, The first parity check matrix is expressed as shown in Table 2 below when the coding rate is 2/3.

Numbers in Table 2 represent the exponent of the permutation matrix, I is an index indicating that the exponent of the permutation matrix is zero. The method of claim 1, The first parity check matrix is expressed as shown in Table 3 below when the coding rate is 3/4.

Numbers in Table 3 indicate the exponent of the permutation matrix, I is an index indicating that the exponent of the permutation matrix is zero. The method of claim 1, The first parity check matrix is expressed as shown in Table 4 below when the coding rate is 5/6.

Numbers in Table 4 represent the exponent of the permutation matrix, I is an index indicating that the exponent of the permutation matrix is zero. The method of claim 1, The first parity check matrix is expressed as shown in Table 5 below when the coding rate is 1/2.

Numbers in Table 5 represent the exponent of the permutation matrix, I is an index indicating that the exponent of the permutation matrix is zero. The method of claim 1, The first parity check matrix is expressed as shown in Table 6 below when the coding rate is 2/3.

Numbers in Table 6 represent the exponent of the permutation matrix, I is an index indicating that the exponent of the permutation matrix is zero. The method of claim 1, The first parity check matrix is expressed as shown in Table 7 below when the coding rate is 3/4.

Numbers in Table 7 represent the exponent of the permutation matrix, I is an index indicating that the exponent of the permutation matrix is zero. The method of claim 1, The first parity check matrix is expressed as shown in Table 8 when the coding rate is 3/4.

Numbers in Table 8 represent the exponent of the permutation matrix, I is an index indicating that the exponent of the permutation matrix is zero. The method of claim 1, The first parity check matrix is expressed as shown in Table 9 below when the coding rate is 1/2.

Numbers in Table 9 represent the exponent of the permutation matrix, I is an index indicating that the exponent of the permutation matrix is zero. The method of claim 1, The first parity check matrix is expressed as shown in Table 10 below when the coding rate is 1/2.

In Table 10, the numbers represent exponents of the permutation matrix, and I is an index representing that the exponent of the permutation matrix is zero. The method of claim 1, The first parity check matrix is expressed as shown in Table 11 below when the coding rate is 2/3.

In Table 11, the numbers represent the exponents of the permutation matrix, and I is the index indicating that the exponent of the permutation matrix is zero. The method of claim 1, The first parity check matrix is expressed as in Table 12 when the coding rate is 2/3.

Numbers in Table 12 represent the exponent of the permutation matrix, I is an index indicating that the exponent of the permutation matrix is zero. The method of claim 1, The first parity check matrix is expressed as shown in Table 13 below when the coding rate is 1/2.

In Table 13, the numbers represent the exponents of the permutation matrix, and I is the index indicating that the exponent of the permutation matrix is zero. The method of claim 1, The first parity check matrix is expressed as shown in Table 14 below when the coding rate is 1/2.

In Table 14, the numbers represent the exponents of the permutation matrix, and I is the index indicating that the exponent of the permutation matrix is zero. The method of claim 1, The first parity check matrix is expressed as shown in Table 15 below when the coding rate is 2/3.

In Table 15, the numbers represent exponents of the permutation matrix, and I is an index indicating that the exponent of the permutation matrix is zero. In the decoding device of a block low density parity check (LDPC) code, A received signal by connecting variable nodes corresponding to weights of columns of the parity check matrix including an information part corresponding to an information word and a first parity part and a second parity part corresponding to parity according to a predetermined control. A variable node decoder for detecting and outputting probability values of A first adder for subtracting and outputting a signal generated during the previous decoding from the signal output from the variable node decoder; A deinterleaver for inputting the signal output from the first adder to deinterleave and output the deinterleaving method according to the parity check matrix; A check node decoder configured to detect and output probability values of a signal output from the deinterleaver by connecting check nodes according to weights of the rows constituting the parity check matrix according to a predetermined control; A second adder for subtracting the signal output from the deinterleaver from the signal output from the check node decoder; An interleaver for interleaving the signal output from the second adder in an interleaving scheme set corresponding to the parity check matrix and outputting the interleaved signal to the variable node decoder and the first adder; And a controller for generating the parity check matrix and controlling the deinterleaving scheme and the interleaving scheme according to the parity check matrix. The method of claim 20, The controller determines a size of a parity check matrix to correspond to a coding rate and a codeword length applied when the information word is encoded into the block LDPC code, and converts the parity check matrix having the determined size into a predetermined number of blocks. And dividing the blocks into blocks corresponding to the information part, blocks corresponding to the first parity part, blocks corresponding to the second parity part, and classified into the first parity part. Arrange the permutation matrices in predetermined blocks of the blocks, arrange the permutation matrices in a completely lower triangular form into predetermined blocks among the blocks classified as the second parity part, and then block classified into the information part. The permutation matrix such that the minimum cycle length on the factor graph of the block LDPC code becomes a preset cycle length, and the weight is nonuniform. And the parity check matrix is generated by arranging the data. The method of claim 21, And said permutation matrices arranged in a perfect lower triangular form are identity matrices. The method of claim 21, The parity check matrix is expressed as shown in Table 16 below when the coding rate is 1/2.

In Table 16, the numbers represent the exponents of the permutation matrix, and I is the index indicating that the exponent of the permutation matrix is zero. The method of claim 21, The first parity check matrix is expressed as shown in Table 17 below when the coding rate is 2/3.

In Table 17, numbers represent exponents of the permutation matrix, and I is an index representing that the exponent of the permutation matrix is zero. The method of claim 21, The parity check matrix is expressed as shown in Table 18 when the coding rate is 3/4.

In Table 18, the numbers represent the exponents of the permutation matrix, and I is the index indicating that the exponent of the permutation matrix is zero. The method of claim 21, The first parity check matrix is expressed as shown in Table 19 below when the coding rate is 5/6.

Numbers in Table 19 represent the exponent of the permutation matrix, I is an index indicating that the exponent of the permutation matrix is zero. The method of claim 21, And the first parity check matrix is expressed as shown in Table 20 below when the coding rate is 1/2.

The numbers in Table 20 represent exponents of the permutation matrix, and I is an index indicating that the exponent of the permutation matrix is zero. The method of claim 21, The first parity check matrix is expressed as shown in Table 21 when the coding rate is 2/3.

Numbers in Table 21 indicate the exponent of the permutation matrix, I is an index indicating that the exponent of the permutation matrix is zero. The method of claim 21, The first parity check matrix is expressed as shown in Table 22 below when the coding rate is 3/4.

In Table 22, the numbers represent the exponents of the permutation matrix, and I is the index indicating that the exponent of the permutation matrix is zero. The method of claim 21, The first parity check matrix is expressed as shown in Table 23 below when the coding rate is 3/4.

In Table 23, the numbers represent the exponents of the permutation matrix, and I is the index indicating that the exponent of the permutation matrix is zero. The method of claim 21, The first parity check matrix is expressed as shown in Table 24 below when the coding rate is 1/2.

In Table 24, the numbers represent the exponents of the permutation matrix, and I is the index indicating that the exponent of the permutation matrix is zero. The method of claim 21, The first parity check matrix is expressed as shown in Table 25 below when the coding rate is 1/2.

The numbers in Table 25 represent exponents of the permutation matrix, and I is an index indicating that the exponent of the permutation matrix is zero. The method of claim 21, The first parity check matrix is expressed as shown in Table 26 below when the coding rate is 2/3.

In Table 26, the numbers represent the exponents of the permutation matrix, and I is the index indicating that the exponent of the permutation matrix is zero. The method of claim 21, The first parity check matrix is expressed as shown in Table 27 below when the coding rate is 2/3.

In Table 27, the numbers represent the exponents of the permutation matrix, and I is the index indicating that the exponent of the permutation matrix is zero. The method of claim 21, And the first parity check matrix is expressed as shown in Table 28 below when the coding rate is 1/2.

In Table 28, the numbers represent the exponents of the permutation matrix, and I is the index indicating that the exponent of the permutation matrix is zero. The method of claim 21, The first parity check matrix is expressed as shown in Table 29 below when the coding rate is 1/2.

In Table 29, the numbers represent the exponents of the permutation matrix, and I is the index representing that the exponent of the permutation matrix is zero. The method of claim 21, The first parity check matrix is expressed as shown in Table 30 below when the coding rate is 2/3.

Numbers in Table 30 indicate the exponent of the permutation matrix, I is an index indicating that the exponent of the permutation matrix is zero. In the decoding method of a block low density parity check (LDPC) code, Generating the parity check matrix including an information part corresponding to an information word, a first parity part and a second parity part corresponding to a parity, and determining a deinterleaving method and an interleaving method according to the parity check matrix. and, Detecting probability values of the received signal; Generating a first signal by subtracting a signal generated at a previous decoding from probability values of the received signal; Inputting the first signal to deinterleave the deinterleaving method; Detecting probability values by inputting the deinterleaved signal; Generating a second signal by subtracting the deinterleaved signal from probability values of the deinterleaved signal; And interleaving the second signal by the interleaving method, and repeatedly decoding the interleaved signal. The method of claim 38, Generating the parity check matrix; Determining a size of the parity check matrix to correspond to a coding rate and a codeword length applied when the information word is encoded into the block LDPC code; Dividing the parity check matrix of the determined size into blocks having a preset number; Classifying the blocks into blocks corresponding to the information part, blocks corresponding to the first parity part, and blocks corresponding to the second parity part; Arranging permutation matrices in predetermined blocks among the blocks classified as the first parity part, and arranging permutation matrices in a completely lower triangular shape among predetermined blocks among the blocks classified as the second parity part; , And arranging the permutation matrices such that the minimum cycle length on the factor graph of the block LDPC code becomes a preset cycle length to blocks classified as the information part, and the weight is non-uniform. The method of claim 39, And wherein the permutation matrices arranged in a perfect lower triangular form are identity matrices. The method of claim 38, The parity check matrix is expressed as shown in Table 31 below when the coding rate is 1/2.

In Table 31, the numbers represent the exponents of the permutation matrix, and I is the index indicating that the exponent of the permutation matrix is zero. The method of claim 38, The first parity check matrix is expressed as shown in Table 32 below when the coding rate is 2/3.

In Table 32, the numbers represent the exponents of the permutation matrix, and I is the index indicating that the exponent of the permutation matrix is zero. The method of claim 38, The parity check matrix is expressed as in Table 33 when the coding rate is 3/4.

In Table 33, the numbers represent the exponents of the permutation matrix, and I is the index indicating that the exponent of the permutation matrix is zero. The method of claim 38, The first parity check matrix is expressed as shown in Table 34 below when the coding rate is 5/6.

In Table 34, the numbers represent the exponents of the permutation matrix, and I is the index indicating that the exponent of the permutation matrix is zero. The method of claim 38, The first parity check matrix is expressed as shown in Table 35 below when the coding rate is 1/2.

In Table 35, the numbers represent the exponents of the permutation matrix, and I is the index indicating that the exponent of the permutation matrix is zero. The method of claim 38, The first parity check matrix is expressed as shown in Table 36 below when the coding rate is 2/3.

In Table 36, the numbers represent the exponents of the permutation matrix, and I is the index indicating that the exponent of the permutation matrix is zero. The method of claim 38, The first parity check matrix is expressed as shown in Table 37 below when the coding rate is 3/4.

In Table 37, numbers represent exponents of the permutation matrix, and I is an index indicating that the exponent of the permutation matrix is zero. The method of claim 38, The first parity check matrix is expressed as shown in Table 38 below when the coding rate is 3/4.

In Table 38, the numbers represent the exponents of the permutation matrix, and I is the index representing that the exponent of the permutation matrix is zero. The method of claim 38, The first parity check matrix is expressed as shown in Table 39 below when the coding rate is 1/2.

In Table 39, the numbers represent the exponents of the permutation matrix, and I is the index indicating that the exponent of the permutation matrix is zero. The method of claim 38, The first parity check matrix is expressed as shown in Table 40 below when the coding rate is 1/2.

In Table 40, the numbers represent the exponents of the permutation matrix, and I is the index indicating that the exponent of the permutation matrix is zero. The method of claim 38, The first parity check matrix is expressed as shown in Table 41 below when the coding rate is 2/3.

In Table 41, the numbers represent the exponents of the permutation matrix, and I is the index indicating that the exponent of the permutation matrix is zero. The method of claim 38, The first parity check matrix is expressed as shown in Table 42 below when the coding rate is 2/3.

In Table 42, the numbers represent the exponents of the permutation matrix, and I is the index indicating that the exponent of the permutation matrix is zero. The method of claim 38, The first parity check matrix is expressed as shown in Table 43 below when the coding rate is 1/2.

In Table 43, the numbers represent the exponents of the permutation matrix, and I is the index indicating that the exponent of the permutation matrix is zero. The method of claim 38, The first parity check matrix is expressed as shown in Table 44 below when the coding rate is 1/2.

In Table 44, the numbers represent the exponents of the permutation matrix, and I is the index indicating that the exponent of the permutation matrix is zero. The method of claim 38, The first parity check matrix is expressed as shown in Table 45 below when the coding rate is 2/3.

In Table 45, the numbers represent the exponents of the permutation matrix, and I is the index indicating that the exponent of the permutation matrix is zero.

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