KR20060008039A - Method for forming gate of semiconductor device - Google Patents
Method for forming gate of semiconductor device Download PDFInfo
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- KR20060008039A KR20060008039A KR1020040057693A KR20040057693A KR20060008039A KR 20060008039 A KR20060008039 A KR 20060008039A KR 1020040057693 A KR1020040057693 A KR 1020040057693A KR 20040057693 A KR20040057693 A KR 20040057693A KR 20060008039 A KR20060008039 A KR 20060008039A
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 150000004767 nitrides Chemical class 0.000 claims abstract description 29
- 230000002401 inhibitory effect Effects 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000004140 cleaning Methods 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 238000002955 isolation Methods 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 238000000231 atomic layer deposition Methods 0.000 claims description 11
- 239000011259 mixed solution Substances 0.000 claims description 4
- 239000000243 solution Substances 0.000 claims description 4
- 229910003818 SiH2Cl2 Inorganic materials 0.000 claims description 3
- 229910003902 SiCl 4 Inorganic materials 0.000 claims description 2
- 239000007789 gas Substances 0.000 description 10
- 239000010410 layer Substances 0.000 description 9
- 239000000463 material Substances 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 238000011109 contamination Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000009036 growth inhibition Effects 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910003910 SiCl4 Inorganic materials 0.000 description 1
- 229910003980 SiCl6 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
- H01L21/02507—Alternating layers, e.g. superlattice
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
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Abstract
본 발명은 게이트 산화막의 특성을 향상시킬 수 있는 반도체 소자의 게이트 형성방법을 개시한다. 개시된 본 발명은, 소자분리막이 구비된 반도체 기판을 제공하는 단계; 상기 반도체 기판의 표면을 1차 세정하는 단계; 상기 1차 세정된 반도체 기판 상에 게이트 산화막을 형성하는 단계; 상기 게이트 산화막의 표면을 2차 세정하는 단계; 상기 기판 결과물을 NH3 분위기로 열처리하는 단계; 상기 2차 세정된 산화막 상에 자연산화막 성장 억제용 질화막을 증착하는 단계; 상기 자연산화막 성장 억제용 질화막 상에 게이트 도전막을 증착하는 단계; 및 상기 게이트 도전막과 자연산화막 성장 억제용 질화막 및 게이트 산화막을 패터닝하는 단계를 포함한다.The present invention discloses a gate forming method of a semiconductor device capable of improving the characteristics of the gate oxide film. Disclosed is a semiconductor device having a device isolation film; First cleaning the surface of the semiconductor substrate; Forming a gate oxide film on the first cleaned semiconductor substrate; Second cleaning the surface of the gate oxide film; Heat treating the substrate resultant with NH 3 atmosphere; Depositing a nitride film for inhibiting growth of a native oxide film on the second cleaned oxide film; Depositing a gate conductive film on the nitride film for inhibiting growth of the natural oxide film; And patterning the gate conductive layer, the nitride layer for inhibiting the growth of the native oxide layer, and the gate oxide layer.
Description
도 1 내지 도 4는 본 발명의 실시예에 따른 반도체 소자의 게이트 형성방법을 설명하기 위한 도면.1 to 4 are diagrams for explaining a gate forming method of a semiconductor device according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
21 : 반도체 기판 22 : 소자분리막21
23 : 게이트 산화막 24 : 질화막23
25 : 게이트 도전막25: gate conductive film
본 발명은 반도체 소자의 게이트 형성방법에 관한 것으로, 보다 상세하게는, 게이트 산화막의 특성을 향상시킬 수 있는 반도체 소자의 게이트 형성방법에 관한 것이다.The present invention relates to a method for forming a gate of a semiconductor device, and more particularly, to a method for forming a gate of a semiconductor device capable of improving the characteristics of a gate oxide film.
최근 소자의 크기가 감소함에 따라 게이트 산화막의 두께가 점점 얇아지면서, 게이트 산화막 상에 형성된 자연산화막이 소자의 전기적 특성에 큰 영향을 미치게 되었다. 자연산화막은 소자에 전기적인 페일(fail)과 문턱전압 변동을 발생시 켜 수율을 떨어뜨리고, 이물질 오염으로 소자의 특성을 저하시킨다. 따라서, 이러한 문제들을 해결하기 위해 자연산화막의 성장을 억제할 수 있는 반도체 소자의 제조방법이 요구된다.Recently, as the size of the device is reduced, the thickness of the gate oxide film becomes thinner and thin, the natural oxide film formed on the gate oxide film has a great influence on the electrical characteristics of the device. The natural oxide film causes electrical fail and threshold voltage fluctuations in the device to reduce the yield, and deteriorates the characteristics of the device due to foreign material contamination. Therefore, in order to solve these problems, a method of manufacturing a semiconductor device capable of suppressing the growth of a natural oxide film is required.
이하에서는, 종래 반도체 소자의 게이트 형성방법을 간략하게 설명하도록 한다.Hereinafter, a gate forming method of a conventional semiconductor device will be briefly described.
먼저, 소자분리막이 구비된 반도체 기판 상에 게이트 산화막을 형성한다. 상기 게이트 산화막 형성공정을 위한 재료로서 SiO2를 사용하며, 퍼니스를 이용한 방법 또는 ALD를 이용한 방법으로 게이트 산화막을 형성시킨다. First, a gate oxide film is formed on a semiconductor substrate provided with an isolation layer. SiO 2 is used as a material for the gate oxide film forming process, and a gate oxide film is formed by a furnace method or an ALD method.
그런 다음, 파티클 측정과 두께측정을 하는데, 이때, 기판이 대기중에 노출되어 게이트 산화막 상에 자연산화막이 성장한다. Then, particle measurement and thickness measurement are performed. At this time, the substrate is exposed to the air so that a natural oxide film is grown on the gate oxide film.
계속해서, 자연산화막을 포함한 게이트 산화막 상에 게이트 도전막을 증착하고, 이들을 패터닝하여 최종적으로 게이트를 형성한다.Subsequently, a gate conductive film is deposited on the gate oxide film including the natural oxide film, and these are patterned to finally form a gate.
상기에서, 게이트 산화막의 두께를 33Å으로 유지하고 자연산화막의 성장을 억제해야 하는데, 이를 위해서는, 게이트 산화막을 형성시킨 후 시간지연없이 후속 공정인 게이트 폴리실리콘 증착공정을 진행해야 한다. 그러나, 게이트 산화막 형성 후 파티클 측정 및 두께 측정을 하는데 최소한 20분 이상의 시간이 지연되므로 자연산화막이 성장하여 소자의 균일도를 저하시키므로 문턱전압 변동이 증가한다. 또한, 게이트 산화막과 자연산화막 사이에 이물질 오염이 발생하여 모바일 차아지(mobile charge) 밀도가 증가한다. 이로 인해 계면의 트랩 차아지가 많이 형성되어 전기적 두께가 증가함으로써, 문턱전압을 증가시킨다. In the above, the thickness of the gate oxide film should be maintained at 33 Å and the growth of the natural oxide film should be suppressed. For this purpose, the gate polysilicon deposition process should be performed without forming a gate oxide film without delay. However, since a time delay of at least 20 minutes is delayed for particle measurement and thickness measurement after the gate oxide film is formed, the natural oxide film grows and degrades the device uniformity, thereby increasing the threshold voltage variation. In addition, foreign matter contamination occurs between the gate oxide layer and the natural oxide layer, thereby increasing the mobile charge density. As a result, many trap charges at the interface are formed to increase the electrical thickness, thereby increasing the threshold voltage.
한편, 반도체 소자의 집적도 증가에 따라 게이트 산화막의 두께가 33Å 이하로 얇아지면서, 표면 채널 타입의 PMOS 게이트 트랜지스터의 게이트 전극 도핑시 게이트 산화막이 붕소(B) 확산을 억제하기 어려워지며, 게이트 산화막의 핀 홀(pin hole)과 같은 결함이 생길 수 있다. 또한, 게이트 산화막이 극단적으로 얇아지면서 파울러-노르다임(Fowler-Nordheim) 터널링 메커니즘에 의한 전류 이외에 터널링보다 낮은 전기장에서도 산화막의 포비든(forbidden) 에너지 밴드를 뚫고서 직접적으로 게이트 전극까지 전자가 이동하는 다이렉트(direct) 터널링 전류 현상이 발생하는데, 이러한 문제들을 제어하기 위해서 단일층으로 만들어진 게이트 산화막의 한계에 대한 대책이 필요하다.On the other hand, as the thickness of the semiconductor device increases, the thickness of the gate oxide film becomes less than 33 GPa, which makes it difficult to suppress the boron (B) diffusion during the gate electrode doping of the surface channel type PMOS gate transistor. Defects such as pin holes can occur. In addition, as the gate oxide becomes extremely thin, in addition to the current caused by the Fowler-Nordheim tunneling mechanism, the electron moves directly to the gate electrode through the forbidden energy band of the oxide even in an electric field lower than the tunneling. A direct tunneling current phenomenon occurs, and countermeasures against the limitation of a single layer gate oxide film are needed to control these problems.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 게이트 산화막의 특성을 향상시킬 수 있는 반도체 소자의 게이트 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a gate of a semiconductor device capable of improving the characteristics of the gate oxide film, which is devised to solve the above problems.
상기와 같은 목적을 달성하기 위하여, 본 발명은, 소자분리막이 구비된 반도체 기판을 제공하는 단계; 상기 반도체 기판의 표면을 1차 세정하는 단계; 상기 1차 세정된 반도체 기판 상에 게이트 산화막을 형성하는 단계; 상기 게이트 산화막의 표면을 2차 세정하는 단계; 상기 기판 결과물을 NH3 분위기로 열처리하는 단계; 상기 2차 세정된 산화막 상에 자연산화막 성장 억제용 질화막을 증착하는 단계; 상기 자연산화막 성장 억제용 질화막 상에 게이트 도전막을 증착하는 단계; 및 상기 게이트 도전막과 자연산화막 성장 억제용 질화막 및 게이트 산화막을 패터닝하는 단계를 포함하는 반도체 소자의 게이트 형성방법을 제공한다.In order to achieve the above object, the present invention provides a semiconductor substrate provided with a device isolation film; First cleaning the surface of the semiconductor substrate; Forming a gate oxide film on the first cleaned semiconductor substrate; Second cleaning the surface of the gate oxide film; Heat treating the substrate resultant with NH 3 atmosphere; Depositing a nitride film for inhibiting growth of a native oxide film on the second cleaned oxide film; Depositing a gate conductive film on the nitride film for inhibiting growth of the natural oxide film; And patterning the gate conductive film, the nitride film for inhibiting the growth of the native oxide film, and the gate oxide film.
여기서, 상기 1차 및 2차 세정은 50:1 HF 용액으로 60∼75초 동안 수행한 후, NH4OH:H2O2:H2O=1:4:20인 혼합용액으로 9∼11분 동안 수행하는 방식으로 진행한다.Here, the first and second cleaning is performed for 60 to 75 seconds with a 50: 1 HF solution, followed by 9 to 11 minutes with a mixed solution of NH 4 OH: H 2 O 2: H 2 O = 1: 4: 20. do.
그리고, 상기 자연산화막 성장 억제용 질화막은 10∼40Å의 두께로 증착하며, 버티컬(vertical) 퍼니스를 이용한 방법 또는 ALD(atomic layer deposition) 방법으로 증착한다.In addition, the nitride film for growth inhibition of the native oxide film is deposited to a thickness of 10 to 40 kPa, and is deposited by a method using a vertical furnace or an atomic layer deposition (ALD) method.
또한, 상기 버티컬 퍼니스를 이용한 방법은 600∼800℃의 온도 및 0.3∼0.4torr 압력의 버티컬 퍼니스에 50∼100sccm의 N2 가스와 500∼900sccm의 NH3 가스 및 50∼90sccm의 SiH2Cl2 가스를 플로우시켜 자연산화막 성장 억제용 질화막을 증착하며, ALD 방법은 25∼450℃의 온도의 챔버 내에 NH3 가스와 SiCl4 또는 SiCl6 가스를 이용하여 자연산화막 성장 억제용 질화막을 증착한다.In addition, the method using the vertical furnace is a natural oxide film by flowing 50-100sccm N2 gas, 500-900sccm NH3 gas and 50-90sccm SiH2Cl2 gas in a vertical furnace at a temperature of 600 ~ 800 ℃ and 0.3 ~ 0.4torr pressure A growth inhibiting nitride film is deposited, and the ALD method deposits a natural oxide film growth inhibiting nitride film using NH3 gas and SiCl4 or SiCl6 gas in a chamber at a temperature of 25 to 450 ° C.
(실시예)(Example)
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 4는 본 발명의 실시예에 따른 반도체 소자의 게이트 형성방법을 설명하기 위한 단면도이다.1 to 4 are cross-sectional views illustrating a gate forming method of a semiconductor device in accordance with an embodiment of the present invention.
도 1을 참조하면, 소자분리막(22)이 구비된 반도체 기판(21)의 표면을 1차 세정한다. 상기 1차 세정은 50:1 HF 용액으로 60∼75초 동안 수행한 후, NH4OH:H2O2:H2O=1:4:20인 혼합용액으로 9∼11분 동안 수행하는 방식으로 진행한다. 그런 다음, 1차 세정된 반도체 기판 상에 게이트 산화막(23)을 형성한다. 여기서, 상기 게이트 산화막(23) 형성공정을 위한 재료로서 SiO2를 사용하며, 퍼니스를 이용한 방법 또는 ALD를 이용한 방법으로 게이트 산화막(23)을 형성시킨다. Referring to FIG. 1, the surface of the
도 2를 참조하면, 상기 게이트 산화막의 표면을 2차 세정한다. 이때, 상기 2차 세정은 50:1 HF 용액으로 60∼75초 동안 수행한 후, NH4OH:H2O2:H2O=1:4:20인 혼합용액으로 9∼11분 동안 수행하는 방식으로 진행한다. 그런 다음, 2차 세정을 마친 기판을 NH3 분위기에서 열처리하여 질소성분이 실리콘 산화막에 침투되어 실리콘 질화막(미도시)을 성장시킨다. 상기 질화막은 실리콘 산화막의 경계영역에서 실리콘 댕글링 본드와 결합하여 수소와 대체시킨 구조로 산화막의 성장을 억제시킨다. Referring to FIG. 2, the surface of the gate oxide film is secondarily cleaned. At this time, the secondary washing is performed for 60 to 75 seconds with a 50: 1 HF solution, followed by 9 to 11 minutes with a mixed solution of NH 4 OH: H 2 O 2: H 2 O = 1: 4: 20. Then, the substrate after the secondary cleaning is heat-treated in an NH 3 atmosphere to allow nitrogen to penetrate the silicon oxide film to grow a silicon nitride film (not shown). The nitride film is bonded to the silicon dangling bond in the boundary region of the silicon oxide film and replaced with hydrogen to inhibit the growth of the oxide film.
계속해서, 상기 질화막 상에 자연산화막 성장 억제용 질화막(24)을 증착한다. 상기 자연산화막 성장 억제용 질화막은 10∼40Å의 두께로 증착하며, 버티컬(vertical) 퍼니스를 이용한 방법 또는 ALD(atomic layer deposition) 방법으로 증착한다. Subsequently, a nitride film for inhibiting natural oxide film growth is deposited on the nitride film. The nitride film for growth inhibition of the natural oxide film is deposited to a thickness of 10 to 40 kPa, and is deposited by a method using a vertical furnace or an atomic layer deposition (ALD) method.
여기서, 상기 버티컬 퍼니스를 이용한 방법은 600∼800℃의 온도 및 0.3∼0.4torr 압력의 버티컬 퍼니스에 50∼100sccm의 N2 가스와 500∼900sccm의 NH3 가스 및 50∼90sccm의 SiH2Cl2 가스를 플로우시켜 자연산화막 성장 억제용 질화막을 증착한다. 이때, 상기 NH3는 SiH2Cl2와 반응하여 질화막(Si3N4)을 형성한다. Here, the method using the vertical furnace flows a natural oxide film by flowing 50-100 sccm N2 gas, 500-900 sccm NH3 gas and 50-90 sccm SiH2Cl2 gas in a vertical furnace at a temperature of 600-800 ° C. and 0.3-0.4torr pressure. A growth inhibiting nitride film is deposited. In this case, the NH 3 reacts with SiH 2 Cl 2 to form a nitride film (Si 3 N 4).
상기 ALD 방법은 25∼450℃의 온도의 챔버 내에 NH3 가스와 SiCl4 또는 SiCl6 가스를 이용하여 자연산화막 성장 억제용 질화막(24)을 증착한다.The ALD method deposits a
도 2c를 참조하면, 자연산화막 성장 억제용 질화막(24) 상에 게이트 도전막(25)을 증착한다. 여기서, 상기 게이트 도전막으로는 예컨대, 도핑된 폴리실리콘막과 텅스텐 실리사이드 적층막을 이용한다. 또한, 상기 도전막 상에 하드마스크 질화막을 형성한다.Referring to FIG. 2C, a gate
도 2d를 참조하면, 상기 게이트 도전막(25)과 자연산화막 성장 억제용 질화막(24) 및 게이트 산화막(23)을 패터닝하여 본 발명에 따른 게이트를 형성한다.Referring to FIG. 2D, the gate
상기한 바와 같이, 본 발명은 게이트 산화막을 형성한 직후 상기 게이트 산화막 상에 질화막을 형성시켜줌으로써, 게이트 산화막이 공기중의 산소에 노출되어 자연산화막이 성장하는 것을 억제할 수 있다. 자연산화막의 성장을 억제함으로써, 게이트 산화막을 균일한 두께로 유지하여 워드라인의 누설전류를 줄일 수 있으며, 웨이퍼내 균일한 문턱전압을 갖는 소자를 제조할 수 있다. As described above, in the present invention, by forming a nitride film on the gate oxide film immediately after the gate oxide film is formed, it is possible to suppress the growth of the natural oxide film by exposing the gate oxide film to oxygen in the air. By suppressing the growth of the native oxide film, the gate oxide film can be maintained at a uniform thickness to reduce the leakage current of the word line, and a device having a uniform threshold voltage in the wafer can be manufactured.
이상에서와 같이, 본 발명은 게이트 산화막 상에 질화막을 형성시켜줌으로서, 자연산화막의 성장을 억제하여 웨이퍼 전체적으로 균일도를 향상시킬 수 있다.As described above, according to the present invention, by forming a nitride film on the gate oxide film, the growth of the natural oxide film can be suppressed to improve the uniformity of the entire wafer.
그리고, 균일도를 향상시킴으로써 문턱전압 변동을 감소시킬 수 있다.And, by improving the uniformity, it is possible to reduce the threshold voltage fluctuation.
또한, 자연산화막이 성장할 때 발생하는 게이트 산화막의 이물질 오염을 방지하여 소자특성 및 수율을 향상시킬 수 있다.In addition, it is possible to prevent foreign material contamination of the gate oxide film generated when the natural oxide film is grown, thereby improving device characteristics and yield.
기타, 본 발명은 그 요지가 일탈하지 않는 범위 내에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
Claims (6)
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| KR20210030326A (en) * | 2018-02-28 | 2021-03-17 | 가부시키가이샤 코쿠사이 엘렉트릭 | Method of manufacturing semiconductor device, method of substrate processing, substrate processing apparatus, and program |
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| KR20210114913A (en) * | 2018-02-28 | 2021-09-24 | 가부시키가이샤 코쿠사이 엘렉트릭 | Method of manufacturing semiconductor device, method of substrate processing, substrate processing apparatus, and program |
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