KR20050112573A - Apparatus for detecting trouble and plasma display panel therewith - Google Patents

Abstract

An object of the present invention is to detect a failure part of a plasma display panel, and to achieve this object,

A fault detection apparatus for detecting a fault unit using a test pattern in a plasma display panel driven with a plurality of units, the fault detection apparatus comprising: a test pattern generation control unit outputting a control signal to designate a unit in which the test pattern will occur; A test pattern generator which generates a test pattern in a unit designated by a control signal; It provides a failure detection device and a plasma display panel having the same, characterized in that it comprises a failure detection unit for receiving a test pattern to compare with a reference test pattern, determine whether there is an abnormality and detect a failure unit,

In the test mode, the test pattern generation control unit automatically designates the unit in which the test pattern is to be generated sequentially, and in the user mode, designates a unit in which the test pattern is to be generated by the user's selection. Provided are a failure detecting apparatus and a plasma display panel having the same.

Description

Apparatus for detecting trouble and plasma display panel therewith}

The present invention relates to a plasma display panel, and more particularly, to a failure detection apparatus and a plasma display panel having the same.

1 is a view showing the structure of a conventional three-electrode surface discharge plasma display panel.

Referring to FIG. 1, between the front and rear glass substrates 100 and 106 of a conventional surface discharge plasma display panel 1, the address electrode lines A ₁ ,. A ₂ , ..., A _m ), Dielectric layers 102 and 110, Y electrode lines Y ₁ , ..., Y _n , X electrode lines X ₁ , ..., X _n , fluorescent layer 112, barrier rib 114, and As a protective layer, the magnesium monoxide (MgO) layer 104 is provided, for example.

Address electrode lines A ₁ , A ₂ , ..., A _m ) is formed in a predetermined pattern on the front side of the rear glass substrate 106. The lower dielectric layer 110 includes the address electrode lines A ₁ ,. A ₂ , ..., A _m ) is applied to the front. In front of the lower dielectric layer 110, barrier ribs 114 may include address electrode lines A ₁ ,. A ₂ , ..., A _m ) is formed in a direction parallel to. The partition walls 114 function to partition a predetermined area of each display cell and to prevent optical interference between each display cell. The fluorescent layer 112 is formed between the partition walls 114.

The X electrode lines X ₁ ,..., X _n and the Y electrode lines Y ₁ , ..., Y _n are the address electrode lines A ₁ ,. A ₂ , ..., A _m ) is formed in a predetermined pattern on the back of the front glass substrate 100 to be orthogonal to each other. Each intersection sets a corresponding display cell. Each X electrode line (X ₁ , ..., X _n ) and each Y electrode line (Y ₁ , ..., Y _n ) are transparent electrode lines (X _na ) made of a transparent conductive material such as indium tin oxide (ITO). , Y _na ) and metal electrode lines X _nb and Y _nb for increasing conductivity may be formed. The front dielectric layer 102 is formed by applying the entire surface to the rear of the X electrode lines (X ₁ ,..., X _n ) and the Y electrode lines (Y ₁ ,..., Y _n ). A protective layer 104 for protecting the panel 1 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying a front surface to the back of the front dielectric layer 102. The plasma forming gas is sealed in the discharge space 108.

A driving scheme generally applied to such a plasma display panel is a method in which initialization, address, and display holding steps are sequentially performed in a unit sub-field. In the initialization step, the state of charge of the display cells to be driven becomes uniform. In the address step, the charge state of display cells to be selected and the charge state of display cells not to be selected are set. In the display holding step, the charge state of the display cells to be selected is set. In the display holding step, display discharge is performed in the display cells to be selected. At this time, a plasma is formed from the plasma forming gas of the display cells performing display discharge, and the fluorescent layer 112 of the display cells is excited by ultraviolet radiation from the plasma to generate light.

2 illustrates a general driving device of the plasma display panel of FIG. 1.

Referring to the drawings, a typical driving apparatus of the plasma display panel 1 includes an image processor 200, a controller 202, an address driver 206, an X driver 208, and a Y driver. The image processing unit 200 converts an external analog image signal into a digital signal to convert an internal image signal, for example, 8 bits of red (R), green (G), and blue (B) image data, a clock signal, vertical and Generate horizontal sync signals. The address driver 206 processes the address signal SA among the driving control signals SA, SY, and SX from the controller 202 to generate a display data signal, and generates the display data signal into the address electrode lines. To apply. The X driver 208 processes the X driving control signal SX among the driving control signals SA, SY, and SX from the controller 202 and applies the X driving control signal SX to the X electrode lines. The Y driving unit 204 processes the Y driving control signal SY among the driving control signals SA, SY, and SX from the control unit 202 and applies it to the Y electrode lines.

As a driving method of the plasma display panel 1 having the above-described structure, an address-display separation driving method mainly used is disclosed in US Pat. No. 5,541,618.

FIG. 3 illustrates a conventional address-display separation driving method for Y electrode lines as an example of the plasma display panel driving method of FIG. 1.

Referring to the drawings, a unit frame may be divided into a predetermined number, for example, eight subfields SF1, ..., SF8 to realize time division gray scale display. Further, each subfield SF1, ... SF8 is divided into a reset section (not shown), an address section A1, ..., A8, and a sustain discharge section S1, ..., S8. .

In each address section A1, ..., A8, a display data signal is applied to the address electrode lines and scan pulses corresponding to each of the Y electrode lines Y1, ..., Yn are sequentially applied.

In each sustain discharge section S1, ..., S8, pulses for display discharge alternately in the Y electrode lines Y1, ..., Yn and the X electrode lines X1, ..., Xn. Is applied to cause display discharge in discharge cells in which wall charges are formed in the address periods A1, ..., A8.

The luminance of the plasma display panel is proportional to the number of sustain discharge pulses in the sustain discharge sections S1, ..., S8 occupied in the unit frame. When one frame forming one image is represented by eight subfields and 256 gradations, each subfield is kept different at a ratio of 1, 2, 4, 8, 16, 32, 64, and 128 in turn. The number of pulses can be assigned. In order to obtain luminance of 133 gradations, cells may be addressed and sustained and discharged during the subfield 1 period, the subfield 3 period, and the subfield 8 period.

The number of sustain discharges allocated to each subfield may be variably determined according to weights of the subfields according to the APC (Automatic Power Control) step. The number of sustain discharges allocated to each subfield can be variously modified in consideration of gamma characteristics and panel characteristics. For example, the gray level assigned to subfield 4 may be lowered from 8 to 6, and the gray level assigned to subfield 6 may be increased from 32 to 34. In addition, the number of subfields forming one frame can be variously modified according to design specifications.

FIG. 4 is a timing diagram illustrating an example of a driving signal of the panel shown in FIG. 1. The address electrode A and the sustain electrode in one subfield SF in the ADS (Address Display Separation) driving method of the AC PDP are shown in FIG. X) and drive signals applied to the scan electrodes Y1 to Yn. Referring to FIG. 4, one subfield SF includes a reset period PR, an address period PA, and a sustain discharge period PS.

The reset period PR applies a reset pulse to all of the scan lines of all groups and forcibly performs a write discharge, thereby initializing the wall charge states of all cells. The reset period PR is carried out before entering the address period PA, which is carried out over the entire screen, thus making it possible to create a fairly even and evenly distributed wall charge arrangement. The cells initialized by the reset period PR have similar wall charge conditions inside the cells. The address period PA is performed after the reset period PR is performed. At this time, in the address period PA, the bias voltage Ve is applied to the sustain electrode X, and the scan electrodes Y1 to Yn and the address electrodes A1 to Am are simultaneously turned on at the cell positions to be displayed. Select the cell. After the address period PA is performed, the sustain pulse Vs is alternately applied to the sustain electrodes X and the scan electrodes Y1 to Yn to perform the sustain discharge period PS. During the sustain discharge period PS, a low level voltage VG is applied to the address electrodes A1-Am. In PDP, the brightness is adjusted by the number of sustain discharge pulses. If the number of sustain discharge pulses in one subfield or one TV field is large, the luminance increases.

Conventionally, when a problem occurs in a plasma display panel, the cause of the problem has been found through visual inspection and waveform inspection of ICs or circuit elements around a suspected place. This has to find the cause of the problem by a number of trial and error, which takes a lot of time and money.

SUMMARY OF THE INVENTION An object of the present invention is to provide a failure detection apparatus for detecting a failure using a test pattern and a plasma display panel having the same, by solving the above problems.

In order to achieve the above object, the present invention provides a fault detection apparatus for detecting a fault unit using a test pattern in a plasma display panel which is driven with a plurality of units, and designates a unit for generating a test pattern. A test pattern generation controller for outputting a control signal; A test pattern generator which generates a test pattern in a unit designated by a control signal; A failure detection apparatus for a plasma display panel, comprising: a failure detection unit for receiving a test pattern, comparing the result with a reference test pattern, and determining whether there is an abnormality and detecting a failure unit.

According to another aspect of the present invention, in the test mode, the test pattern generation control unit may automatically designate sequentially the units in which the test pattern will be generated.

According to another feature of the present invention, in the user mode, the test pattern generation controller may designate a unit in which the test pattern is to be generated by the user's selection.

The present invention also provides a plasma display panel provided with the failure detection device, in order to achieve the above object.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

5 is a simplified block diagram of a failure detection apparatus for detecting a failure using a test pattern.

Referring to FIG. 5, in a plasma display panel driven with a plurality of units, the failure detection apparatus 300 outputs a control signal for specifying a unit in which a test pattern is to be generated. And a test pattern generator 501, 503, 509 for generating the test pattern and a failure detector 515 for detecting the failure unit by receiving the test pattern.

 The test pattern generation control unit 519 receives a user mode signal for designating the test pattern generating unit or a test mode signal for automatically designating the test pattern generating unit sequentially. According to the user mode signal or the test mode signal, the test generation controller 519 designates each unit including the test pattern generators 501, 503, and 509 and outputs a control signal to generate a test pattern.

The test pattern generator is provided in each unit. The test pattern generator provided in each unit generates different test patterns by control signals of the test pattern generator. The generated test pattern is included in an output signal generated by a predetermined unit and output. The output signal of the predetermined unit is changed into a new output signal through the subsequent unit. Therefore, the final unit outputs the final output signal including the generated test pattern.

The failure detector receives a final output signal including the generated test pattern from the last unit. Only the test pattern generated in the received final output signal is recognized and compared with the reference test pattern to determine whether there is an abnormality, and a failure unit is detected. A method of detecting a failure unit will be described in detail with reference to FIGS. 6 and 7.

FIG. 6 is a flowchart for describing an operation in a test mode of the failure detection apparatus illustrated in FIG. 5. Looking at the operation of the failure detection device in the test mode,

First, it is determined whether the test mode is the user selection signal (S601). If not in test mode, it runs in user mode.

Next, in the test mode, units in which the test pattern is to be generated are automatically designated sequentially (S603). This is performed by the test pattern generation controller 519. The test mode designates units to generate test patterns one at a time, and then, after detecting an abnormality, sequentially designates units to generate other patterns. Preferably, for efficient fault detection, it is preferable to designate the last unit first in the flow of the signal to determine whether there is an abnormality, and then determine whether there is an abnormality by sequentially designating units in the direction of the first unit.

Next, the test pattern is generated (S605). This is performed by the test pattern generators 501, 503, 509. The test patterns generated and output in each unit are different test patterns, and fault detection can be easily performed therefrom.

Next, the test pattern is received (S607). This is performed by the failure detector 515. The output signal including the test pattern is received by the failure detection unit 515 through several units.

Next, an abnormality of the received test pattern is examined (S609). This is performed by the failure detector 515. Examine whether there is any abnormality in the test pattern of the received output signal by comparing with the reference test pattern.

If abnormal, it is determined that at least one unit abnormality among the units after the test pattern is generated (S611). If a strange test pattern is received, it may be determined that the unit has failed since the test pattern occurred, and there may be a plurality of failed units.

If it is not abnormal, the unit after the generation of the test pattern determines that no unit has a failure (S613).

It is determined whether the failure unit can be detected (S615). Through the steps S609 to S613 it is determined whether the failure unit can be detected. For example, if a test pattern is generated in the final unit and a test pattern is received by the failure detection unit, and a strange test pattern is received through comparison with the reference test pattern, the final unit can immediately detect that a failure. However, it is not possible to determine whether the units fail before the final unit. On the other hand, if it is determined that there is no abnormality as a result of receiving the test pattern generated in the final unit, the final unit may determine that it is not a failure. However, it is not possible to determine whether units fail before the final unit.

If the failure unit cannot be detected, steps S603 to S615 are repeated to detect the failure unit. At this time, the designation of the unit in which the test pattern is generated is preferably specified sequentially from the last unit to the first unit according to the flow of the signal. It is also preferable to designate sequentially from the initial unit direction to the final unit direction. Therefore, all test patterns can be generated sequentially, and each can be received to detect a failure unit. The unit in which the failure is detected may be displayed on the panel using an OSD (On Screen Display).

FIG. 7 is a flowchart for describing an operation in a user mode of the failure detecting apparatus illustrated in FIG. 5.

First, it is determined whether the user mode (S701). If not in the user mode, the steps shown in FIG. 6 are performed as the test mode.

Next, it is determined whether or not there is a user input by the user's operation (S703). Since the user mode is performed by the user's operation, the standby mode is executed until the user inputs.

Next, a unit for generating a test pattern is designated by the user's selection (S705). The test pattern generation controller 519 designates a unit in which the test pattern is to be generated by the user's selection signal. The user may select one unit or simultaneously select two or more units. In addition, the unit may be selected again after performing all the steps illustrated in FIG. 7.

Steps S707 to S717 to be performed next are the same as steps S605 to S615 shown in FIG.

If the detection of the failure unit is not possible, steps S703 to S717 are repeated to detect the failure unit. The unit in which a failure is detected can also be displayed on the panel using the OSD.

8 is a failure detection device for detecting a failure in an image processing device that is a component of a plasma display panel as an embodiment of the present invention.

Since the image signal is processed by the image processor 200, a failure detection device that detects a failure unit using a test pattern is particularly preferably applied to the image processor 200.

Referring to the drawings, the image processor 200 includes a switch 801, an ADC (Analoge to digital converter, 803), a scaler 805, an enhancer (811), a low voltage differential signal (LVDS), It is roughly composed of a video decoder 807 and a doubler 809.

The switch 801 receives a DTV, a PC, and a DVI signal. The ADC 803 converts an analog video signal into a digital video signal and outputs it as an RGB signal. The video decoder 807 receives the Video, Svideo, and DVD signals, decodes the encoded signal, and outputs the YUV signal. The doubler 809 deinterlaces the interlaced signal. The scaler 805 receives signals from the ADC 803 and the doubler 809, outputs RGB 24 bits, adjusts the resolution, and performs image correction. The enhancer 811 increases the RGB 24-bit signal and outputs the RGB 30-bit signal, corrects edges of the image, and emphasizes color. The LVDS 813 transforms the received RGB 30bit signal to be input to the logic controller 202 and outputs the modified RGB 30bit signal.

 The video decoder 807, the doubler 809, and the scaler 805 have a test pattern generation function, and have test pattern generators 501, 503, 509, respectively. The test pattern generation control unit 519 operates by the test mode signal or the user mode signal, and the unit in which the test pattern is to be generated is designated by the test pattern generation control unit 519. It is preferable to designate only one unit to detect the abnormality, and it is preferable to generate the test pattern sequentially. Therefore, first, a test pattern is generated at the scaler 805. An output signal is input to the fault detection unit 515 to detect the presence of an abnormality. If there is a problem, the scaler 805 is detected as a failure unit. If there is no abnormality, it is determined that the scaler 805 is not a failure unit. Next, a test pattern is generated in the doubler 809. The output signal is input again to the fault detection unit 515 to detect the presence of an abnormality. If there is no error, it is determined that both the doubler 809 and the scaler 805 are not faulty units. If there is a problem, at least one of the doubler 809 and the scaler 805 is determined to be a failure, and the determination of the failure unit is determined through a test pattern generated in the scaler 805. Next, a test pattern is generated at the video decoder 807. The output signal is input again to the fault detection unit 515 to detect the presence of an abnormality. If there is no error, it is determined that both the doubler 809, the scaler 805, and the video decoder 807 are not faulty units. If there is a problem, at least one of the doubler 809, the scaler 805, and the video decoder 807 is determined to be a failure, and the failure unit determination may be performed through a test pattern generated by the scaler 805 and the doubler 809. Is determined. On the other hand, it is also preferable to generate the test pattern sequentially from the video decoder 807.

9 is a simplified block diagram of a plasma display panel equipped with a failure detection apparatus of the present invention.

A plasma display panel including an image processor 200, a logic controller 202, a driver 207, and a panel 1 may further include a failure detection device 300 that detects a failure using a test pattern. In particular, the failure detection apparatus 300 is useful in the image processor 200. Of course, the logic controller 202 may also be used for fault detection of a unit in the logic controller 202.

According to the present invention as described above, the following effects can be obtained.

The test pattern generation function in the unit can be used to easily detect a faulty unit, thereby saving time and money in detecting and repairing the faulty unit.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a view showing the structure of a conventional three-electrode surface discharge plasma display panel.

FIG. 2 shows a typical driving apparatus of the plasma display panel shown in FIG. 1.

FIG. 3 illustrates a conventional address-display separation driving method for Y electrode lines as an example of the plasma display panel driving method of FIG. 1.

FIG. 4 is a timing diagram for explaining an example of a drive signal of the panel shown in FIG. 1.

5 is a simplified block diagram of a failure detection apparatus for detecting a failure using a test pattern.

FIG. 6 is a flowchart for describing an operation in a test mode of the failure detection apparatus illustrated in FIG. 5.

FIG. 7 is a flowchart for describing an operation in a user mode of the failure detecting apparatus illustrated in FIG. 5.

8 is a failure detection device for detecting a failure in an image processing device that is a component of a plasma display panel as an embodiment of the present invention.

9 is a simplified block diagram of a plasma display panel equipped with a failure detection apparatus of the present invention.

Explanation of symbols on main parts of drawing

300 ... fault detection device

501, 503, 509 ... Test pattern generator 1, 2, n

515 Fault detection unit

519 Test Pattern Generation Control Unit

Claims (4)

In the fault detection apparatus for detecting a fault unit by using a test pattern in a plasma display panel driven with a plurality of units, A test pattern generation controller configured to output a control signal to designate a unit in which the test pattern will occur; A test pattern generator which generates the test pattern in a unit designated by the control signal; And a failure detection unit which receives the test pattern, compares it with a reference test pattern, determines whether there is an abnormality, and detects a failure unit. The method of claim 1, wherein the test pattern generation control unit In the test mode, the failure detection apparatus of the plasma display panel, characterized in that for automatically specifying the unit in which the test pattern will occur. The method of claim 1, wherein the test pattern generation control unit In the user mode, the failure detection apparatus of the plasma display panel, characterized in that the unit for generating the test pattern is designated by the user's selection.  A plasma display panel comprising the failure detection device according to any one of claims 1 to 3.