KR20050094402A - Integrated circuit diagnosing method, system, and program product - Google Patents

Abstract

The invention provides a method, system (12), and program product for diagnosing an integrated circuit. In particular, the invention captures one or more images for each relevant circuit layer of the integrated circuit (S2). Based on the image(s), a component netlist is generated (S3, S305, S315). Further, a logic netlist is generated (S4) by applying hierarchical composition rules to the component netlist. The component netlist and/or logic netlist can be compared to a reference netlist to diagnose the integrated circuit. The invention can further generate a schematic (50) based on the component netlist or logic netlist in which components are arranged according to port, power, and/or component pin connection information determined from the netlist. Further, the schematic can be displayed in a manner that wiring connections are selectively displayed to assist a user in intelligently arranging the circuit components.

Description

Integrated circuit diagnostic methods, systems, and program products {INTEGRATED CIRCUIT DIAGNOSING METHOD, SYSTEM, AND PROGRAM PRODUCT}

The present invention generally relates to diagnostics of integrated circuits.

Often, integrated circuits are netlisted and / or connected to recover lost netlists or schematics, determine whether an integrated circuit violates intellectual property, or analyze the performance or failure of an integrated circuit. Reverse engineering is required. The connection diagram is a visual representation of the circuit, but the netlist is a document representation of all the elements of the circuit and the various pin connections. Some characteristics of integrated circuits are that the reverse engineering process is difficult and time consuming. For example, the physical placement of many components on an integrated circuit may be independent of where the components are placed in the connection diagram. In addition, integrated circuits are often implemented in several layers joined together to establish an intended connection.

Recently, several solutions have been proposed to help the tedious reverse engineering process. Generally, a scanning electron microscope (SEM) or similar imaging device is used to irradiate a layer of an integrated circuit. Additional tools are used to identify component features and wiring interconnections with an overlay of data on the image. Alternatively, you can use the tool to convert the image into a layout.

However, performing the reverse engineering process to generate netlists and / or connection diagrams still requires specialized techniques and wastes time. Consequently, what is needed is an integrated circuit diagnostic system, method, and program product that increases the accuracy of the resulting netlist and / or connection diagram while reducing the amount of technology needed to generate netlist and / or connection diagram from the integrated circuit.

Disclosure of the Invention

The present invention provides a method, system, and program product for diagnosing an integrated circuit. In particular, the present invention captures one or more images for each relevant circuit layer of the integrated circuit. Based on the image (s), a component netlist is generated. Logical netlists are also created by applying hierarchical rules to component netlists. Component netlists or logical netlists may be compared to reference netlists to diagnose integrated circuits. The invention may also generate a connection diagram in which components are arranged in accordance with port, power, and / or component pin connection information determined from the netlist based on the component netlist or logical netlist. In addition, the wiring connections can be selectively displayed so that the wiring diagram can be displayed so that the user can intelligently arrange the circuit components.

Exemplary forms of the invention are designed to solve the problems described herein and other problems not described herein, which may be found by the skilled person.

Features of the present invention will be readily understood from the detailed description of various embodiments of the present invention in conjunction with the accompanying drawings.

1 illustrates an exemplary system for implementing various embodiments of the present invention.

2 illustrates a method according to one embodiment of the invention.

3 illustrates an exemplary method of generating a netlist in accordance with another embodiment of the present invention.

4 illustrates an exemplary method of generating a netlist in accordance with still another embodiment of the present invention.

5 shows an exemplary connection diagram display.

The drawings of the present invention are not to scale. The drawings are intended to understand typical embodiments of the invention and should not be considered as limiting the scope of the invention. In the drawings, like reference numerals refer to like elements.

For the sake of convenience, the detailed description is provided in an I. exemplary system; II. Method overview; III. Capturing image (s); IV. Generating component netlists; V. Logical Netlist Generation; VI. A netlist application; And VII. Includes parts indicated by titles containing alternatives.

The present invention provides a system, program product, and method for diagnosing an integrated circuit (IC). The present invention generates a "component netlist" and / or a "logical netlist" based on one or more images of each circuit layer of an integrated circuit. A "component netlist" includes components used in integrated circuits (ie, transistors, capacitors, resistors, ports, power rails, resistors, diodes, chips, etc.) and their interconnections. “Logical netlist” is replaced by one or more symbols (ie, AND gates, NAND operations, adders, etc.) representing one or more collections of circuit components in a component netlist that represent the function (s) implemented by each collection of circuit components. Contains the list that is

I. Example System

1 shows an integrated circuit diagnostic system 12 in accordance with the present invention. System 12 may include a central processing unit (CPU) 14, a memory 16, an input / output (I / O) interface 18, a bus 20, and an optional database 24. As shown, the user 30 interacts with the system 12 via the I / O interface 18. System 12 may be any form of general purpose / special use computerized system (eg, server, desktop computer, etc.). User 30 may be an individual using system 12 and may be any type of computerized system (eg, mobile phone) that may be used to access system 12 by, for example, a network. , Handheld computer, personal digital assistant, portable (laptop) computer, desktop computer, workstation, mainframe computer, etc.). In the latter case, the communication between the user 30 and the system 20 may be a known mechanism or a mechanism later developed for this purpose, for example one or more serial hardwired connections (eg, serial ports), or It can be via an addressable connection in a client-server (or server-server) environment that can use any combination of wired and / or wireless transmission methods. In a client-server environment, the server and client may be connected via the Internet, a wide area network (WAN), a local area network (LAN), a virtual private network (VPN), or other private network. Servers and clients may use conventional network connections such as token ring, Ethernet, WiFi, or other conventional communication standards. If the client communicates with the server via the Internet, the connection may be provided by conventional TCP / IP socket-based protocols. In this case, the client establishes a connection to the server using an Internet service provider.

System 12 may include any general purpose or special purpose system using standard operating system software, which is designed to drive the operation of particular hardware and is compatible with other system components and I / O controllers. The CPU 14 may include a single processing unit, multiple processing units operable in parallel, or may be distributed through one or more processing units on one or more locations, eg, clients and servers. The memory 16 may include any type of data storage and / or transmission medium including magnetic media, optical media, random access memory (RAM), read only memory (ROM), data cache, data objects, and the like. . In addition, like the CPU 14, the memory 16 may reside in a single physical location that includes one or more types of data storage or may be distributed through multiple physical systems in various forms.

I / O interface 18 includes, for example, I / O ports (serial, parallel, Ethernet, keyboard, mouse, etc.), Universal Serial Bus (USB) ports, expansion buses, integrated drive electronics (IDEs), network systems, modems. Users, including speakers, monitors (cathode ray tubes (CRT)), liquid crystal displays (LCDs), handheld devices, keyboards, mice, speech recognition systems, voice output systems, scanners, printers, fax machines, pagers, storage devices, 30) may include any system for exchanging information. Bus 20 provides a communication link between components within computer system 12 and may include any type of transmission link including electrical, optical, wireless, and the like. Also, although not shown, additional components may be included in system 12 such as cache memory, communication systems, system software, and the like.

The database 24 can store information necessary for realizing the present invention as will be described later. Database 24 may include one or more storage devices, such as a magnetic disk drive or an optical disk drive. The database 24 may also include data distributed over a LAN, WAN, or storage area network (SAN) (not shown), for example. Database 24 may also be configured in such a way that one skilled in the art can interpret and include one or more storage devices.

System 12 includes integrated circuit diagnostic program 32 stored in memory 16 as computer program code. The integrated circuit diagnostic program 32 implements various methods described below. Capture system 34 may capture one or more images of the integrated circuit and assign coordinate information to each image. Component system 36 generates a component netlist based on one or more captured images. Logical system 38 generates a logical netlist based on the component netlist (described below). The integrated circuit diagnostic program 32 also compares the logic and / or component netlist with one or more reference logic and / or component netlists (collectively referred to as “reference netlists”) generated from the reference circuits. ), A connection diagram system 42 for generating connection diagrams based on logic and / or component netlists, and a display system 44 for selectively displaying wiring information within the connection diagrams.

It will be appreciated that the various systems shown in integrated circuit diagnostic program 32 are included for illustrative purposes. As a result, one or more of the systems may or may not be combined into a single system. In addition, one or more of the systems may be implemented as a separate program that may be executed separately from the integrated circuit diagnostic program 32.

II. Method outline

2 illustrates an exemplary method of diagnosing an integrated circuit in accordance with one embodiment of the present invention. Integrated circuits include one or more layers and generally include one or more layers involved in performing diagnostics. In step S1, if one or more circuit layers are involved, each relevant circuit layer of the integrated circuit is delayered (ie exposed) using known techniques or techniques developed later. In step S2, one or more images of each circuit layer are captured by the capture system 34 (FIG. 1) as described in more detail below. In step S3, a component netlist is generated from the image (s). The present invention provides two alternatives described below for generating a component netlist from an image using the component system 36 (FIG. 1) described below. Using one alternative, the image (s) is converted to a layout and the information for the component netlist is extracted. Alternatively, the information for the component netlist can be obtained directly from the inspection of the image. In step S4, a logical netlist is generated by the logical system 38 (FIG. 1) based on the component netlist. Logical netlists are created by applying hierarchical rules to component netlists to replace one or more circuit elements with one or more logic functions that they implement.

As noted above, integrated circuits may include circuit elements that constitute one or more input and / or output "ports" (signals). A "port" is any type of circuit that provides an interface to additional circuitry (ie, pads, wires connected to unanalyzed portions of the circuit, etc.). Integrated circuits also often include one or more circuit elements connected to an internal power supply (V _dd ), ground (V _ss ) or other power supply. The present invention includes port and power information in the netlist.

Component netlists or logical netlists can be used in a variety of applications. For example, logical netlists or component netlists may be compared using comparison system 40 (FIG. 1). The logical netlist may be compared with other logical netlists (ie, "reference logical netlist") based on the reference circuit. Similarly, the component netlist generated from the integrated circuit can be compared to the component netlist used to generate the integrated circuit (ie, the "reference component netlist") to determine if an error has occurred in manufacturing. Similarities and differences between the two circuits (netlists) may be determined and displayed by the display system 44 (FIG. 1). In addition, the connection diagram may be generated using the connection diagram system 42 (FIG. 1), in which circuit components are arranged based on port information, power information, and / or component pin connection information. For example, the input port circuit elements can be disposed on the left side of the connection diagram, the output port circuit elements can be disposed on the right side, V _dd can be disposed on the top, and V _ss can be disposed on the bottom. The wiring in the connection diagram can be selectively displayed using the display system 44 (FIG. 1) to help the user arrange the circuit components.

III. Capturing image (s)

According to step S2, one or more images of each relevant circuit layer may be captured and stored in a memory, for example, database 24 (FIG. 1). The number of images required for each layer depends on the circuit resolution and the size of the circuit layer. Any means for capturing an image may include, for example, a scanning electron microscope (SEM), a specialized electron beam tool (electron beam induced current (EBIC) technology), optical microscopy, digital imaging, and the like. If multiple images for each circuit layer are used, a coordinate system can be used to place the images. For example, a coordinate value may be assigned to the upper left corner of each image. The image containing the upper left corner of the circuit layer has a coordinate reference of (0, 0). Coordinates may be determined based on, for example, the number of pixels displayed in an image and / or the enclosed physical area within the image.

The image may be captured such that the image partially overlaps one or more adjacent images. Superposition allows the image to completely cover the circuit layer and helps to identify the state when the circuit element is found in two adjacent images. If there is overlap, the assigned coordinate criteria of the image should take into account the overlap. For example, if the coordinate is based on the number of pixels, the coordinate reference of the offset image is obtained by subtracting the number of overlapping pixels from the total pixels. Alternatively, if sufficient accuracy can be obtained to place the image, the image can be captured so that there is no overlap.

IV. Create component netlist

In step S3, the component netlist is generated based on the image (s) of the integrated circuit. As outlined above, two alternatives may be chosen to generate a component netlist. The first alternative provides some improvements to existing techniques for generating component netlists, while the second alternative provides a more direct approach.

A. Layout-Based Generation

3 illustrates an example method of generating a component netlist. In step S301, the image (s) of the integrated circuit are converted into layouts by the component system 36 (FIG. 1). In this case, component system 36 (FIG. 1) may convert the image (s) into a layout including software such as CHIPSCANNER ^™ from Raith USA Inc. Layout is an electronic representation of the physical design of an integrated circuit. Common layout description file formats include GL1 and GDS. The layout can be read to visually display each circuit element at a particular location in the integrated circuit.

Often, if the layout generated from the image (s) includes wiring and physical layout information, other information may be lacking. For example, the port (s) and power rail (s) definitions of integrated circuits can often be missing. In addition, other information may be lacking, such as wells, differential nominal-Vt transistors, and low-Vt transistors. As a result, the layout can be edited using component system 36 (FIG. 1) to include definitions of some or all of the missing information. For example, the difference in threshold voltage between devices is generally marked with an implant mask. The implant mask may be included in layout data as a new level. In particular, as shown in step 302, port and power information may be added to the layout. This information helps to generate connection diagrams using component netlists, to compare component netlists with other component netlists, and / or to convert component netlists into logical netlists, each of which is described below.

In step 303, component information (transistor, resistor, chip, port, power rail, etc.) is extracted from the layout. In step S304, a net connection (i.e., wiring information, such as a pin-to-pin connection) is extracted from the layout. In step S305, the component information and the net connection are used to generate a component netlist.

An extraction engine may be provided as part of component system 36 (FIG. 1) to implement steps S303, S304, and S305. The extraction engine may be obtained from one or more tools for generating layouts from component netlists. These tools can be modified to extract component netlists from layouts. For example, ERIE ^™ by an international business machine is an example of a layout generation tool that can be modified to perform the function of an extraction engine. In this case, the ERIE is modified to accommodate the data defining the layer interaction. Using the data, component information and net connection are extracted. The extracted information is then combined and formatted into a document representation of the layout component and their connection (ie, component netlist).

The layout-based approach described above uses existing techniques with some refinements, so this approach may not be desirable in any case. For example, when a small integrated circuit is diagnosed, a "hands on" approach may be required. In addition, compared to a more direct approach, it may be difficult to determine an error in one or more of the steps described above. As a result, the image-based approach described below may be beneficial in any case.

B. Image-Based Generation

4 illustrates another method of generating a component netlist based on one or more circuit images. In step S311, "layer information" is identified for each image. "Layer information" may include circuit elements involved in diagnosing integrated circuits including ports, circuit components, component pins, wiring, and power rails (collectively referred to as "circuit elements"). Identifying the layer information may be performed by a computer program (i.e., part of component system 36 (FIG. 1)) and / or by the user identifying various circuit elements capable of identifying and distinguishing various circuit elements in the image.

For user identification, each circuit image can be presented to the user. Looking at the circuit image, the user can identify the circuit element. The user can define an area by delineating the area for circuit elements in the image using the interface of component system 36 (FIG. 1). Once a region is defined, a unique identifier is assigned and the type of circuit element is added. Device characteristics (ie, identifier, level, type, location, and area information) are stored in a database. This process can continue until all relevant circuit elements have been defined.

Ports may be identified and stored for circuit layers representing external interfaces to the circuit, and various components (ie, transistors, resistors, etc.) may be identified and stored manually or using software. Then, per component, the pins may be identified and stored according to information such as the type of the pin (ie, field effect transistor, source, drain or gate). Finally, the wiring can be identified and stored.

Alternatively, the collection of pins can be used to identify a component without separately identifying the component. In addition, a group of devices can be identified as a single device. For example, a group of vias or wires carrying the same signal can be identified as a single component. As discussed above, an image offset may be added to a location on the image when multiple images are used in the circuit layer. The image may remain displayed to help the user remember that the device has been identified. This process may be repeated for each desired circuit element until all relevant circuit elements in all relevant images have been identified.

In step S312, circuit elements providing a connection between two or more layers may be identified and stored as interlayer information using manual or software to determine the connection between circuit layers. "Middle layer information" includes the identification of all circuit elements that provide a connection between the via and the layer including the contact. Similar to step S311, a computer program portion of computer system 36 (FIG. 1) and / or a user may define shape characteristics representing intermediate circuit elements stored in database 24 (FIG. 1) as interlayer information. The interlayer information also identifies the two layers (ie, layer 2 and layer 3) on which the circuit elements are placed. Alternatively, the interlayer information may be defined and stored as layer information and may be distinguished by the type of circuit element (ie, via, contact, etc.) identified.

In step S313, the layer information and the middle layer information are individually or reduced after being identified using manual or software. In order to reduce layer information, circuit elements are combined into net groups. A "net group" includes a set of circuit elements determined to overlap. As a result, each net group refers to a collection of circuit elements with electrical continuity. Initially, the location and area characteristics for the circuit elements are compared using the component system 36 (FIG. 1) to determine the same type (i.e., pin / pin, wiring / wiring, etc.) or connection type (i.e., wiring / pin, wiring It is determined whether there is any overlap with the circuit elements of the (port, etc.). The circuit elements are continuous across two images, the ends of two elements of the same type are adjacent (i.e., adjacent images without overlapping data), or the two circuit elements share the same two-dimensional space (i.e., connected to a pin Superposition occurs. If an overlap is found, the two circuit elements are joined with the net group identified by the unique net identifier. If the circuit element does not belong to any netgroup, a new netgroup is created. If one device is already joined to the net group, the second device is added to the net group. If both devices belong to separate netgroups, the two netgroups are combined into one netgroup. The middle layer information is reduced in the same way.

Because of potential errors in the coordinate assignment and area definition of each circuit element, variance can be used to determine if there is an overlap. "Distribution" is an area added to a defined area to identify potential errors. For example, less than half the variance of the fundamental pitch of the circuit level may be added before determining whether to overlap one or more other areas. For integrated circuits with a minimum line width of 0.5 microns, a dispersion of 0.25 microns or less may be used. The basic pitch can be defined by the user in a particular unit of measurement (ie, micron) and can be converted to coordinates (ie, pixels) based on the image resolution used to photograph the circuit layer.

In step 314, layer information for adjacent layers is combined using intermediate or manual layer information. Similar methods used with layer information can be merged to determine overlapping elements between layers (ie, addition of variance and comparison of regions). However, overlap is found only for certain circuit elements. In this case, if a match is found, the two netgroups are combined into one netgroup. The process continues until all layers have been processed. For example, to combine the information for layers 1 and 2, the interlayer information obtained from the two layers is sequentially selected and analyzed. As discussed above, the vias can be stored and selected as intermediate circuit elements for analysis. Dispersion can be added to the defined shape of the vias. The modified shape is compared with the layer information of layer 1 and layer 2. The position of the wiring on the layer 1 connected to the via overlaps at least a partially changed shape. As a result, the vias are added to the net group for the wiring on layer one. Similar wiring is found on layer two. In this case, the net groups for the layer 2 wiring and the layer 1 wiring are combined and stored as a single net group.

After the reduction and joining step, each net group represents a complete wiring bond. That is, each net group should include a connection from component pins, ports, and / or power rails to at least one other component pin, port, and / or power rail. As a result, in step S315, the netgroup can be used to generate the component netlist manually or using software. Each net group is selected and all of the wire connections defined by the net group are added to the component netlist. Once all netgroups have been processed, a complete component netlist is created.

V. Create Logical Netlist

Referring to FIG. 2, step S4 includes generating a logical netlist based on the component netlist using the logic system 38 (FIG. 1). In one embodiment, hierarchical rules are applied to the component netlist to replace one or more circuit elements with equivalent logic components. A "hierarchy rule" defines a logical component based on one or more circuit components and their connections. Including the port and power information allows the hierarchy rules to use the net connection and component functions of the various component pins included in the component netlist to determine the function of the parts of the circuit. For example, two transistors can be connected to implement a logic NOT of an input port. In general, the pin of one transistor is connected to V _dd and the pin of the other transistor is connected to V _ss . In order to determine the logical equivalent, hierarchical configuration information is applied which recognizes the function of each transistor and the connection of many pins of each transistor. Since the power information is included in the component netlist, an appropriate pin connection can be determined. Input ports can be selected and various connections to component pins can be traced. If a circuit is found that implements a logic NOT, the two transistors are replaced with a NOT gate. Since any logic circuit can include one or more simpler logic components within the circuit, the process can continue until the most complex component is selected to replace parts of the component netlist.

A database containing common component netlist information for the various logical components can be used to determine the elements that implement the logical components in the circuit. Alternatively, the pin state can be dynamically analyzed to determine logic components implemented within the circuit. Several attempts may be made to combine basic logical components into a single, more complex logical component (ie, an adder can replace several logical components).

VI. Netlist application

Many applications are possible for diagnosing integrated circuits using component netlists and / or logical netlists. The present invention optionally provides one or more unique capabilities to some of the applications described below.

A. Netlist Comparison

The component netlist or logical netlist is compared to one or more reference netlists based on the reference circuit by comparison system 40 (FIG. 1) to determine similarities / differences between the integrated circuit and the reference circuit. The need for this comparison is, for example, when integrated circuits do not function as expected. The component netlist is generated from an integrated circuit and compared to a reference component netlist (ie, the component netlist used to generate the integrated circuit). Any difference between the two circuits potentially represents an error in integrated circuit fabrication.

Alternatively, the logical netlist is compared with one or more reference logical netlists to determine whether the two circuits are similar. This may be useful, for example, for determining if intellectual property held in at least a portion of an integrated circuit is violated. The reference logic netlist (s) may be based on reference circuitry for patent protection. The logical netlist is compared with the reference logical netlist to determine if there is any similarity between the reference circuit (s) and the integrated circuit. For example, a logical netlist can be compared to a reference netlist by selecting common input / output ports and tracking circuit paths. The threshold similarity can be specified after a match is detected. Part of the matching circuit may be displayed with the name provided in the reference logical netlist by displaying the netlist entry and / or by displaying the connection diagram based on the matched circuit.

B. Create Connection Diagram

Often, connection diagrams based on component netlists and / or logical netlists are required. The problem with generating connection diagrams from integrated circuits is that the circuit components are arranged in such a way that the lines where the connections intersect form an almost incomprehensible network. As a result, the location information for the integrated circuit may limit its use, requiring substantial manual editing by the user to rearrange the circuit components into critical connections representing the integrated circuit.

To assist the user, circuit components may be placed based on port information, power information, and / or component pin connection information. This information is included in the component / logical netlist generated from the edited layout or layer information. As components are placed in the connection diagram, port, power, and / or component pin connection information is systematically referenced. For example, a component connected to the input port may be disposed on the left side of the connection diagram and a component connected to the power rail may be disposed on the top of the connection diagram. Also, since the component pin connections follow the previously placed component, the components can be placed sequentially from top to bottom and from left to right. For example, the relative voltage potential of the component pin is dynamically determined and the component is placed in the connection diagram based on the relative potential. This also helps to reduce intersecting lines and to create conventional connection diagrams with a reduced user interface.

C. Wiring Diagram Display

As described above, as described above, when the wiring diagram is initially displayed, lines representing connections between circuit components may intersect with each other, adding confusion to the displayed circuit. To help the user identify the connection path, the connection diagram can be displayed without connection wiring. The user can optionally display the wiring information by specifying a component (when all wire connections to the component are displayed) or by specifying a pin on the component (when wire connections to the selected pin are displayed). For example, a stub may be displayed at the end of each component pin / port. The user can select a stub and the wiring for the selected stub can be displayed. In this way, the user can rearrange the circuit components based on the limited wiring information displayed until the desired arrangement is obtained. Toggle settings alternately display all wiring connections or no-wiring connections / limited wiring connections so that progress can be easily determined.

5 shows an exemplary wiring diagram display 50 according to one embodiment of the invention. The connection diagram display 50 includes a controller 70 for allowing a user to select a method of displaying wiring information of a circuit. For example, the user may select a controller 72 displaying all wiring information, a controller 74 displaying only wiring information of a selected component, or a controller 76 displaying only wiring information of a selected pin. The controller 74 is displayed in bold to indicate the currently selected option.

The circuit includes a pair of input ports 52, 54 and output port 56. Transistor pairs 58 and 60 are configured to invert (perform a logical NOT) the signal provided at input port 52. Various circuit elements are replaced with their logic equivalent, NOR component 62. NOR component 62 performs logical NOR operations on input and output port 54 of transistor pairs 58 and 60. An output of the NOR component 62 is provided to the output port 56. Transistor 58 is shown in bold to indicate that it is the selected component. As a result, only the wiring information for that pin is displayed. The remaining wiring information is shown in dashed lines but may not be displayed based on the current selection. Each pin is shown as a stub 68. As a result, if the user wants to display wiring information for a pin, the user can select a stub 68 that represents the pin.

As described in the previous section, various components are arranged according to port and power information when the connection diagram is generated. For example, V _ss 64 is shown at the top of the connection diagram, V _dd 66 is disposed at the bottom, input ports 52 and 54 are disposed on the left side, and output port 56 is disposed on the right side. do. In addition, transistors 58 and 60 are disposed from top to bottom in accordance with respective connections to V _ss 64 and V _dd 66. In addition, transistors 58 and 60 and NOR component 62 are disposed from left to right in accordance with respective connections to input ports 52 and 54 and output ports 56.

The connection diagram display 50 is understood to illustrate the capabilities described herein. The wiring diagram display 50 is not intended to fully describe the wiring diagram display or all operations that may be performed by the user. In addition, various other user interfaces for displaying and selecting selections are possible and covered by the present invention.

VII. Alternatives

Although various methods are described as occurring in a particular sequence, independent steps may be performed in a sequence different from or simultaneously with the order described herein. It is also possible to repeat one or more of the steps necessary to increase the accuracy of the resulting netless / wiring diagram and to fine-tune the information. In addition, although identification and diagnostics of all components on all layers of the integrated circuit are described, a subset of components and / or layers can be selected and analyzed if desired.

The invention can be realized in hardware, software or a combination of hardware and software. Any kind of computer / server system (s) or other apparatus adapted to carry out the methods described herein are suitable. A general combination of hardware and software may be a general purpose computer system having a computer program that, when loaded and executed, controls the system 12 and / or user 30 system to execute each of the methods described herein. Alternatively, a particular user computer may be used that includes specialized hardware to perform one or more of the functional tasks of the present invention. The invention may also be embedded in a computer program product, which includes all of the features that can implement each of the methods described herein, and when loaded into a computer system can perform their methods. A computer program, software program, program, or software herein may be embodied by a system having information processing capabilities either directly or (a) in translation into another language, code, notation, and / or (b) in the playback of different material types. An expression, code or notation in any language of the instruction set intended to be performed after either or both.

The foregoing descriptions of various embodiments of the present invention are illustrative. Accordingly, the present invention should not be limited to the precise forms disclosed, and many variations and modifications are possible. It is apparent to those skilled in the art that such changes and modifications fall within the scope of the invention as defined in the appended claims.

The present invention is useful for integrated circuits, in particular for generating netlists and / or connection diagrams based on integrated circuits.

Claims (25)

A method of diagnosing an integrated circuit comprising one or more circuit layers, the method comprising: Capturing one or more images for each of the one or more circuit layers; Generating a component netlist based on the one or more images; And Creating a logical netless based on the component netlist by applying hierarchical composition rules How to include. The method of claim 1, Converting the one or more images to a layout; Defining port information and power information in the layout; Extracting component information from the layout; And Extracting a net connection from the layout More, And the component netlist is based on the extracted component information and net access information. The method of claim 1, further comprising defining layer information for the one or more circuit layers using the one or more images, wherein the component netless is based on the layer information. The method of claim 3, wherein the defining of the layer information comprises: Identifying circuit elements for each of the one or more images for the one or more circuit layers; Determining a first circuit element that overlaps the second circuit element; And Reducing the first circuit element and the second circuit element into one net group How to include. The method of claim 4, wherein variance is used in the determining step. The method of claim 3, wherein the integrated circuit comprises a plurality of layers, Delayering each of the plurality of layers; And Steps to Define Mezzanine Information More, The component netlist is also based on the middle layer information. The method of claim 6, wherein the generating of the component netless comprises: Selecting an intermediate circuit element from the intermediate layer information; Determining a first circuit element on a first adjacent layer that overlaps the intermediate layer circuit element; Determining a second circuit element on a second adjacent layer that overlaps the intermediate layer element; And Combining the first circuit element and the second circuit element How to include. 2. The method of claim 1, further comprising generating a schematic diagram based on the logical netlist. 9. The method of claim 8, wherein a component of the circuit is disposed in the connection diagram based on one or more of port information, power information, and component pin connection information. The method of claim 8, further comprising displaying the connection diagram without wiring information. 11. The method of claim 10, further comprising displaying wiring information of the selected component. The method of claim 1, Providing a reference logic netlist based on the reference circuit; Comparing the logical netlist with the reference logical netlist; And Displaying a match between the logical netlist and the reference logical netlist. How to include more. A method of diagnosing an integrated circuit comprising one or more circuit layers, the method comprising: Capturing one or more images of each of the one or more circuit layers; And Generating a connection diagram based on the one or more images Including, Placing circuit components in the connection diagram based on one or more of port information, power information, and component pin connection information. The method of claim 13, Converting the one or more images to a layout; Defining port information and power information in the layout; Generating a component netlist based on the layout using an extraction engine; And Generating a logical netlist based on the component netlist More, The connection diagram is based on the logical netlist. The method of claim 13, Identifying layer information based on the one or more images; Reducing the layer information into a plurality of net groups; Combining the plurality of net groups for each of the one or more circuit layers; Generating a component netlist based on the net group; And Generating a logical netlist based on the component netlist More, The connection diagram is based on the logical netlist. The method of claim 13, further comprising displaying the connection diagram without wiring information. 17. The method of claim 16, further comprising displaying wiring information of the selected circuit component. An integrated circuit diagnostic system, A capture system to capture one or more images for each circuit layer of the integrated circuit; A component system for generating a component netlist based on the one or more images; And Logical system that generates a logical netlist based on the component netlist by applying hierarchical rules and replaces one or more circuit elements in the component netlist with equivalent logical components. Integrated circuit diagnostic system comprising a. 19. The integrated circuit diagnostic system of claim 18, further comprising a comparison system for comparing at least one of the logical netlist and the component netlist with a reference netlist based on a reference circuit. 19. The integrated circuit diagnostic system of claim 18, further comprising a connection diagram system for generating a connection diagram based on at least one of the logical netlist and the component netlist. 21. The integrated circuit diagnostic system of claim 20, further comprising a display system for selectively displaying wiring information in the connection diagram. A computer program product comprising a computer usable medium having computer readable program code implemented for diagnosing an integrated circuit, the computer program product comprising: Program code configured to generate a component netlist based on one or more images of each circuit layer of the integrated circuit; And And program code configured to generate a logical netlist based on the component netlist by applying hierarchical rules and to replace one or more circuit elements in the component netlist with equivalent logical components. 23. The computer program product of claim 22, further comprising program code configured to compare at least one of the logical netlist and the component netlist with a reference netlist based on a reference circuit. 23. The computer program product of claim 22, further comprising program code configured to generate a connection diagram based on at least one of the logical netlist and the component netlist. 25. The computer program product of claim 24, further comprising program code configured to selectively display wiring information in the connection diagram.