KR20050094304A - Interleaver and interleaving method in telecommunication system - Google Patents

Abstract

The present invention is to facilitate the implementation of the block interleaver used in the mobile communication system, the parameter value which is a problem to solve the implementation difficulties caused by the divisor of the interleaver implementation is not a power of two. By simplifying the implementation of the interleaver, we propose a mathematical expression that allows the power of 2 to be used.

Description

Interleaver and interleaving method of communication system {INTERLEAVER AND INTERLEAVING METHOD IN TELECOMMUNICATION SYSTEM}

The present invention relates to interleaving of a mobile communication system, and more particularly, to a block interleaver and an interleaving method that are easy to implement.

In general, the interleaver is used to distribute burst errors due to fading occurring in a radio channel. If the error is concentrated, the error correction coding function is disabled because it exceeds the error recovery capability using the error correction coding. In such a case, the efficiency of error correction coding can be increased by dispersing the concentrated error using an interleaving technique.

The interleaver can be classified into two types, a block interleaver and a convolution interleaver. Consider the bit reversed interleaver, which is a kind of block interleaver. An example of a bit reverse interleaver is a subblock channel interleaver used in IS-2000 Release C, that is, 1x EV-DV.

1 is a diagram illustrating a transmitting system for a packet data channel (PDCH) of a 1x EV-DV system using a block interleaver as a subblock channel interleaver.

As shown in FIG. 1, in a 1xEV-DV system, a 16-bit cyclic redundancy check (CRC) bit addition 102 and a 6-bit tail bit addition 104 for a packet to be transmitted before transmitting a PDCH. , Turbo encoding 106 by the 1/5 rate turbo encoder, interleaving by the channel interleaver 108, and the like. Among these processes, CRC encoding, turbo encoding, channel interleaving, and the like correspond to channel encoding.

CRC encoding is the process of strengthening the error that may occur during transmission by adding CRC bits to the original data. The CRC encoding for the PDCH of the 1x EV-DV system, shown in FIG. 1, is achieved by adding 16 bits of CRC bits to the original packet. That is, a packet having CRC encoding has a size in which 16 bits are added to the original packet size. Prior to turbo encoding a packet to which a CRC bit has been added, a six-bit turbo encoder tail bit is added. As a result, a packet having a size of 22 bits added to the original packet is input to the turbo encoder 106.

Turbo encoding also adds bits to the original data to make it more robust to errors that may occur during transmission. Since the turbo encoder 106 shown in FIG. 1 has a rate of 1/5, when 1 bit is input, 5 bits are output. Since the operation of the turbo encoder is not directly related to the present invention, a detailed description thereof will be omitted.

Interleaving is used to distribute burst errors due to fading occurring in the radio channel, as described above. If the error is concentrated, the error correction coding function is disabled because it exceeds the error recovery capability using the error correction coding. In such a case, the interleaving technique increases the efficiency of error correction coding by dispersing the concentrated error. In general, interleaving is to rearrange and transmit a transmission signal on a time axis, and then rearrange the transmission signal back to its original order, thereby distributing intensive errors during transmission.

Interleaving methods include block interleaving and convolution interleaving. In general, a CDMA system uses a block interleaving method as a channel interleaving method.

In the block interleaving method, a certain data block is designated and interleaved, data is written in the data block in the horizontal direction, and the output is in the vertical direction. On the contrary, the receiving side records the data in the vertical direction and outputs it in the horizontal direction to restore the data to its original state.

In the block interleaving method, a predetermined equation is used to generate an interleaver address when writing data at the transmitting side and outputting data at the receiving side. The equation is as follows.

Meanwhile, k in Equation 1 is a variable representing the number of symbols for the address generated by Equation 1, and m and J are parameter values determined according to the size of a packet input to the interleaver. In the conventional 1xEV-DV system, parameter values according to packet sizes input to the interleaver are determined as shown in Table 2.

2 is a diagram illustrating parameters of a conventional subblock interleaver according to the size of an input packet.

Of FIG. 2 Is a value representing the size of a packet input to the interleaver, m and J are parameter values used in Equation 1 above. As shown in FIG. 2, six packet sizes of 408, 792, 1560, 2328, 3096 and 3864 are used in the 1xEV-DV system. However, when the packet size is 2328, unlike the case where the packet sizes are 408, 792, 1560, 3096, and 3864, the J "value, which is one of the parameter values, has a value of 3. The packet size is 408, It is the result compared with having the power of 2 as J "value in the case of 792, 1560, 3096, and 3864 as 2 or 4.

Meanwhile, looking at Equation 1 for generating the interleaver address, it can be seen that the J value always enters a divisor in Equation 1. However, as shown in FIG. 2, when the packet size input to the encoder is 2328, J is 3. That is, the value of k is divided by three. Dividing a value by a value other than a power of two in the logic must be a significant burden in adjusting the size or timing of the logic. In other words, if J is 4, simply divide the dividend 2 times to the right, and if J is 2, simply perform the bitwise shift 1 bit to the right, whereas J is 3 There is no bit shift alone, so we need to use additional division logic. This causes problems such as complicated circuits and increased size in implementing an interleaver in a mobile communication system.

Accordingly, an object of the present invention to solve such a problem is to provide a block interleaver and an interleaving method that can be implemented only by bit shift.

To this end, the present invention proposes a new equation for calculating an address of an interleaver so that a power of 2 may be used instead of a power of 2 in calculating an interleaver address. do.

The present invention relates to a method of block interleaving of a packet data channel (PDCH) of a CDMA Code Division Multiple Access 1x Evaluation-Data and Voice (hereinafter, referred to as "1xEV-DV") system. Instead of the block interleaver used in the 1xEV-DV communication system proposed by the group, we propose a method to implement the interleaver operation more efficiently.

The present invention for this purpose consists of an interleaver and a method of interleaving using a new equation for generating interleaver address by making the value of J which is a divisor among the parameters used to calculate the address of the interleaver to a power of 2. This allows interleaving without the use of division logic.

Such an interleaver proposed by the present invention is a block interleaver for generating an interleaver address using m and J values, which are parameter values determined by an N value that is an input packet size, wherein the N value represents the J value. In case of a value that is determined to be a power of 2, an interleaver address is generated according to the first interleaving rule, and when the value of N is such that the value of J is determined to be a non-power of 2 second interleaving rule. Is an interleaver for generating an interleaving address.

In addition, the interleaving method proposed by the present invention is an interleaving method using a block interleaver for generating an interleaver address using m and J values, which are parameter values determined by an N value that is an input packet size. A first step of determining whether the size N value of the input packet is a value that makes the J value a power of 2 or a value that does not make the J value a power of 2; When the value is a power of 2, the interleaver address is determined by the first interleaving rule using the second process of determining the m and J values by the first interleaving rule and the m and J values determined by the second process. A third step of generating, a fourth step of determining the m and J values by a second interleaving rule when the value of N is not a value of the value of J as a power of 2, and in the fourth stepBy the second interleaving rule, using the m and J values are specified interleaving comprises a fifth step of generating the interleaver address.

In particular, the second interleaving rule is an interleaving rule using a new parameter value determination rule for converting a J value to a power of 2 and a new equation for generating an interleaver address using the parameter value determined accordingly. The interleaver proposed in the present invention performs interleaving according to a first interleaving rule or a second interleaving rule according to the size of an input packet.

Hereinafter, the present invention will be described using an interleaver applied to a 1xEV-DV system as an example. In the 1xEV-DV system, when the input packet size is 2328, the J value becomes 3. Hereinafter, the present invention will be described in detail with reference to a process of deriving a formula for calculating an interleaver address value by making J a value of 2 rather than 3, which is one of powers of two.

3 is a diagram illustrating a configuration of a subblock interleaver.

The subblock interleaver shown in FIG. 3 corresponds to the channel interleaver 108 of FIG. Symbols output from the turbo encoder 106 of FIG. 1 are input to each subblock of the subblock interleaver shown in FIG. 3. The symbols output from the turbo encoder 106 are interleaved by an interleaving rule. The interleaving rule is as follows.

① The first step is symbol separation.

The first symbol of the turbo encoded symbols is the S subblock 300 of FIG. 3, the second symbol is the P0 subblock 302, the third symbol is the P1 subblock 304, and the fourth symbol is the P0 'subblock ( 306), the fifth symbol is stored in the P1 'subblock 308, and the sixth symbol is again stored in the S subblock 300 in order.

② The second step is subblock interleaving.

The interleaved symbol is an address calculated by the method according to the following steps 1 to 5, that is, Ai (i = 0 to I) the i th symbol is read sequentially.

Each subblock 300 to 308 is interleaved by an interleaving rule according to steps 1 to 5 below.

1. Determine the subblock interleaver parameters m and J using FIG.

2. Initialize i and k to zero.

3. Use Equation 1 to generate the output address.

4. If created in step 3 end Less than = And increase i and k by 1, respectively. Otherwise Discard and increase k only.

5. All Repeat steps 3 and 4 until you get the interleaver output for.

③ The third stage is the symbol group stage.

As shown in FIG. 3, the output of the subblock interleaver is the output of the P0 subblock 302 and the P0 'subblock 304 following the output of the interleaved S subblock 300 interleaver. P0, P0 ', ..., P0, P0' are combined and output, and the outputs of the next P1 and P1 'subblocks are combined in the order of P1, P1', P1, P1 ', ..., P1, P1'. To print.

A process of calculating a mathematical equation for enabling the use of J ", which is one of the parameter values used in the subblock interleaver, as a power of 2, 2 will be described.

To help understand, the general block interleaver is described first.

4 is a diagram illustrating a symbol arrangement of a general block interleaver.

According to the general block interleaver principle, m and J As shown in Fig. 4 = × J becomes. In such a general block interleaver, symbols are sequentially input and output as shown in FIG. 4.

However, in the case of PDCH, the number of data coming into the input of the interleaver Because it is less than the common interleaver address generation formula, "if generated end Less than = And increase i and k by 1, respectively. Otherwise Throw away and increase only k. " . In other words, = ( × J)-(not filled region) has been added. If this is applied to the interleaver whose size of the input packet is 2328, it is as shown in Figs. 5a and 5b.

The following figure illustrates the 2328 packet size.

FIG. 5A is a diagram illustrating a symbol input to each subblock interleaver when the parameter J value is 3. FIG.

As shown in FIG. 5A, when the parameter J value is 3, the input symbols are recorded in three rows.

5B is a diagram showing an interleaver output when the parameter J value is three.

The symbols shown in FIG. 5B are output according to the address value calculated by Equation 1.

As shown in FIGS. 5A and 5B, in the input and output of each symbol, when the parameter values m and J are changed to m = 11 and J = 2 for not fi = 2328, respectively, as shown in FIGS. 6A and 6B below. There is a lled item and the not filled item is not read by step 4 of the interleaving rule. In this case, since J is 3, the division logic should be used in the logic to perform the operations of [k / J] and k mod J. However, if you set the J value to a power of two, you can disable the division logic. In other words, For parameter 2328, the parameter values m and J are changed to m = 11 and J = 2, respectively, as shown in FIGS. 6A and 6B.

FIG. 6A is a diagram showing a symbol input to each subblock interleaver when the parameter J value is 2, and FIG. 6B is a diagram showing an interleaver output when the parameter J value is 2. FIG.

As shown in Figs. 6A and 6B, the number of addresses to be discarded is increased while the resulting address values are the same. When analyzing the address of the sub-block to be output in order to make the formula for generating the interleaver address according to this as shown in Figure 7 below.

7 is a diagram illustrating rows and columns of a subblock according to an output index and an output address thereof.

That is, to produce a row of subblocks Term Using the BRO term representing the columns of the subblock To create it. therefore = 2328, m = 11, instead of J = 3 In order to use = 2328, m = 11, and J = 2, Equation 2 below is used instead of Equation 1 in step 2 of the interleaving rule.

That is, the present invention uses the interleaver address generation method according to the following interleaving rules. At this time, the parameter value according to the packet size also changes.

8 is a diagram illustrating subblock interleaver parameters according to the present invention.

1. Determine the subblock interleaver parameters m, J using FIG.

2. Initialize i and k to zero.

3. If the size of the input packet is 2328, an output address is generated using the following equation.

4. Created end If less than, the address of the i th bit is = And increase i and k by 1, respectively. Otherwise Discard and increase k only.

5. All Repeat steps 3 and 4 until you get the interleaver output for.

In this way, by calculating and using the new equation 2, the parameter J value used as a divisor in the interleaver address value calculation for all packets having various sizes input to the interleaver can be used as 2, which is a power of 2. . Therefore, the interleaver can be implemented using only bit shift without using separate division logic.

Meanwhile, in the above description of the present invention, only Equation 2 for changing the parameter J value to 2 may be used. However, the parameter J value may be replaced with another power of two. Here, a separate description thereof will be omitted.

In practice, the size of the circuit using divide logic is about 50,000 synopsis gates in the implementation of the system, and about 6000 synopsis gates are used in the circuit without division logic. In addition, in terms of timing, the division logic does not occur in the present invention which does not use the division logic in which division of up to 11 nanoseconds of vibration occurs. Therefore, by applying the present invention, it is possible to implement a block interleaver and its interleaver method using only bit shifts without using division logic. In addition, the size of the block interleaver may be reduced.

1A and 1B illustrate a 1x EV-DV system using a subblock channel interleaver.

2 is a diagram showing parameters of a conventional subblock interleaver according to the size of an input packet.

3 is a diagram illustrating a configuration of a subblock interleaver.

4 is a diagram illustrating a symbol arrangement of a general block interleaver.

FIG. 5A is a diagram showing a symbol input to each subblock interleaver when the parameter J value is 3. FIG.

Fig. 5B shows the interleaver output when the parameter J value is three.

FIG. 6A is a diagram showing a symbol input to each subblock interleaver when the parameter J value is 3. FIG.

6B is a diagram showing an interleaver output when the parameter J value is three.

7 shows the rows and columns of a subblock according to the output index and the corresponding output address.

8 is a diagram according to the present invention, showing parameters of a subblock interleaver according to the size of an input packet.

Claims (7)

A block interleaver for generating an interleaver address using m and J values, which are parameter values determined by an N value of an input packet, When the N value is a value for determining the J value as a power of 2, an interleaver address is generated according to a first interleaving rule, and the N value is determined to be a value other than a power of 2 Interleaver to generate an interleaving address according to a second interleaving rule. The interleaver of claim 1, wherein the second interleaving rule converts the J value to a power of two. The method of claim 2, The first interleaving rule is a rule for generating an interleaver address using Equation 3 below, and the second interleaving rule is a rule for generating an interleaver address using Equation 4 below. 4. The interleaver of claim 3, wherein N values to which the first interleaving rule is applied are 408, 792, 1560, 3096, and 3864, and N values to which the second interleaving rule is applied are 2328. An interleaving method using a block interleaver for generating an interleaver address using m and J values, which are parameter values determined by an N value, the size of an input packet, A first step of judging whether the size N value of the input packet is a value that makes the J value a power of 2 or a value that does not make the J value a power of 2; A second step of determining the m and J values by a first interleaving rule when the value of N is a value of the value of J as a power of 2; A third process of generating an interleaver address by a first interleaving rule using m and J values determined in the second process; A fourth step of determining the m and J values by a second interleaving rule when the N value is not a value that makes the J value a power of 2; And a fifth process of generating an interleaver address by a second interleaving rule using m and J values determined in the fourth process. 6. The method of claim 5 wherein the second interleaving rule is an interleaving rule that converts the J value to a power of two. The method of claim 5, In the third process, the interleaver address is generated using Equation 5 below, and in the fifth process, the interleaver address is generated using Equation 6 below.