KR20050089611A - High efficiency bypass switching power amplification apparatus with multiple power modes by using selective bias control - Google Patents

Abstract

The present invention relates to a power amplification device mounted in a wireless communication terminal, and in particular, is configured to include a voltage control circuit for controlling the power stage and the driving stage, operating in multiple modes according to the size of the output power, maximizing additional efficiency The present invention relates to a high efficiency bypass switching multi-mode power amplifier device.

The present invention has proposed a method for further increasing the added efficiency that the conventional bypass switching multi-mode power amplifying apparatus has when the output power is low. Due to the present invention, an additional voltage control circuit can be implemented very simply, can be implemented in a very small size, and can be integrated in a monolithic microwave integrated circuit (MMIC). It is easy to implement because it has no impact on operation in power mode. That is, the present invention can greatly increase the additional efficiency of the bypass switching multi-mode power amplifier in the second power mode without additional cost and effort, and the call of the terminal greatly affected by the additional efficiency in the second power mode. Since it shows a great effect on time, it is possible to extend the talk time of the terminal.

Description

High Efficiency Bypass Switching Power Amplification Apparatus with Multiple Power Modes By using Selective Bias Control}

The present invention relates to a power amplification device mounted in a wireless communication terminal, and in particular, is configured to include a voltage control circuit for controlling the power stage and the driving stage, operating in multiple modes according to the size of the output power, maximizing additional efficiency The present invention relates to a high efficiency bypass switching multi-mode power amplifier device.

Recently, as the terminal used in the wireless communication service becomes smaller and lighter, much research has been conducted to enable a long talk time with a small battery. Even within a terminal, a power amplification device that amplifies a signal to be transmitted to a base station or a repeater consumes a significant amount of the total power consumed by the system. In particular, in the case of CDMA terminals, the power amplification device must be able to produce the maximum output required by the system, so a large amplifier is used accordingly, but most of the time the power amplification device is used to transmit low output power. do. Therefore, when transmitting not only high output power but also low output power, the power amplification device operates in a state of high DC power consumption, and thus, the additional efficiency in the low output power state is very low, thereby limiting talk time of the terminal. It becomes a factor.

For this reason, a lot of research has been focused on increasing the efficiency when the RF power amplification device operates at a low output power as well as a high output power, a representative method is a bypass switching multi-mode power amplification device.

The above-described bypass switching multi-mode power amplification apparatus is configured to operate the power stage desired to be switched according to the situation. The bypass switching circuit operates by dividing the operation mode into several types according to the output power. If you need low output power, adjust the path to output by bypassing the power stage you want to switch, and adjust the path to output through the power stage when high output power is needed.

By using a multi-mode power amplification device that selectively switches modes according to the magnitude of the output power, DC power consumption can be significantly reduced during signal transmission at low output power levels that influence battery life.

1 is a general block diagram of a conventional bypass switching multi-mode power amplification apparatus. When operating at high output power, the bypass circuit is cut off and the signal is output using the power stage 220. At this time, the first impedance matching and bypass circuit unit 230 and the second impedance matching and bypass circuit unit 240 block the signal from passing through the impedance converter 270 and the signal enters the power stage 220. Impedance matching function so that the amplified signal in the power stage 220 is the impedance matched with the output in the third impedance matching and bypass circuit unit 250 and the fourth impedance matching and bypass circuit unit 260 and At the same time, it serves to prevent the signal from leaking to the impedance converter 270. When operating at low output power, a bypass circuit is opened and a signal from the driving stage 200 is output directly without passing through the power stage 220. At this time, the power of the power stage 220 is cut off, and the first impedance matching and bypass circuit unit 230 and the second impedance matching and bypass circuit unit 240 transmit a signal to the impedance converter 270. Impedance matching is performed, and the signal entering the third impedance matching and bypass circuit unit 250 and the fourth impedance matching and bypass circuit unit 260 through the impedance converter 270 is output to the power stage 220 without leakage. It is set to be negative.

The present invention has been devised to further increase the high added efficiency that the conventionally disclosed bypass switching multi-mode power amplification device has shown at low output for the purpose of maximizing the efficiency of the power amplification device.

The bypass switching multi-mode power amplification device was invented to satisfy the continuous demand for extending the talk time of the terminal, thereby increasing the additional efficiency at low output power, but the standby current of the conventional bypass switching multi-mode power amplification device is It has a relatively large value. Therefore, there is a limit to increase in addition efficiency at low output power. This requires a bypass switching multi-mode power amplifier with higher added efficiency by reducing quiescent current while maintaining the performance of the power amplifier.

The present invention is to further increase the additional efficiency in the case of low output power of the conventional bypass switching multi-mode power amplification device, the additional efficiency in the case of low output power of the multi-mode power amplification device is high By solving the problem that is greatly reduced by the standby current, it is intended to implement to increase the additional efficiency by minimizing the DC power consumption in the case of low output power.

A high efficiency bypass switching multi-mode power amplifying apparatus according to the present invention is a bypass switching multi-mode power amplifying apparatus including a driving stage for amplifying an input signal power, wherein the input signal power amplified by the driving stage is re-amplified. An output power stage; A first impedance matching and bypass circuit unit and a second impedance matching and bypass circuit connected between the driving stage and the power stage to perform an impedance matching function so as to transmit the input signal power amplified by the driving stage to the power stage at the maximum. A pass circuit portion; A voltage control circuit unit connected to the driving stage and the power stage and configured to apply different voltages to the first power mode and the second power mode divided according to the magnitude of the output power; A third impedance matching and bypass circuit portion and a fourth impedance matching and bypass circuit portion connected between the power stage and the output terminal to perform an impedance matching function so that the signal power re-amplified by the power stage can be outputted to the maximum; ; And receiving the input signal power amplified by the driving stage through the first impedance matching and bypass circuit unit and the second impedance matching and bypass circuit unit, and performing a third impedance matching and bypass circuit unit and a fourth impedance matching and bypass. It may be configured to include an impedance converter that outputs to the circuit portion.

Preferably, the first impedance matching and bypass circuit unit and the second impedance matching and bypass circuit unit, in the first power mode, transfer the input signal amplified by the driving stage to the power stage, but the impedance The signal leakage to the converter may be prevented, and in the second power mode, the input signal amplified by the driving stage may be transmitted to the impedance converter, but the signal leakage to the power stage may be prevented.

Preferably, the third impedance matching and bypass circuit portion and the fourth impedance matching and bypass circuit portion receive power from the power stage in the first power mode, and receive power from the impedance converter in the second power mode. It can be implemented to receive.

Preferably, the voltage control circuit unit may be implemented to include a power stage control circuit unit for controlling the voltage applied to the power stage and a driving stage control circuit unit for controlling the voltage applied to the driving stage.

Preferably, the power stage control circuit portion and the driving stage control circuit portion may operate by receiving the same digital signal input.

Preferably, the power stage control circuit unit may be implemented to supply power to the power stage in the first power mode, and to cut off the power supplied to the power stage in the second power mode.

Preferably, the driving stage control circuit unit controls the supply voltage to increase the standby current of the driving stage in the first power mode, and reduces the supply voltage to reduce the standby current of the driving stage in the second power mode. It can be implemented to control.

Preferably, the power stage control circuit unit may be implemented in any one form of a circuit of a region indicated by a dotted line in FIGS. 5 (a) to 5 (d).

Preferably, the driving stage control circuit unit may be implemented in any one form of a circuit of a region indicated by a dotted line in FIGS. 6 (a) to 6 (d).

Preferably, the first power mode and the second power mode may be implemented to be determined according to a control voltage signal of the voltage control circuit unit, which is a digital signal.

Preferably, the first power mode is when the output power is high, and the second power mode is when the output power is low.

Alternatively, the high efficiency bypass switching multi-mode power amplification apparatus according to the present invention may include a first switching stage and a second driving stage for amplifying the input signal power through an input impedance matching circuit. And a second driving stage for amplifying the signal power amplified by the first driving stage: the first driving stage so as to transmit the maximum input signal power amplified by the first driving stage to the second driving stage; An impedance matching unit connected between the second driving terminals to perform an impedance matching function; A power stage for reamplifying and outputting the input signal power amplified by the second driving stage; A first impedance matching and bypass circuit unit and a second circuit connected between the second driving terminal and the power terminal to perform an impedance matching function so as to transmit the input signal power amplified by the second driving terminal to the power stage to the maximum; Impedance matching and bypass circuitry; A voltage control circuit unit connected to the first driving stage, the second driving stage, and the power stage and applying different voltages to the first power mode and the second power mode divided according to the magnitude of the output power; A third impedance matching and bypass circuit portion and a fourth impedance matching and bypass circuit portion connected between the power stage and the output terminal to perform an impedance matching function so that the signal power re-amplified by the power stage can be outputted to the maximum; ; And receiving the input signal power amplified by the second driving stage through the first impedance matching and bypass circuit section and the second impedance matching and bypass circuit section, and matching the third impedance matching and bypass circuit section to the fourth impedance matching section. It may be configured to include an impedance converter for output to the bypass circuit portion.

Preferably, the first impedance matching and bypass circuit portion and the second impedance matching and bypass circuit portion transfer the input signal amplified by the second driving stage to the power stage in the first power mode. It may be configured to prevent signal leakage to an impedance converter, and in the case of the second power mode, to transmit an input signal amplified by the second driving stage to the impedance converter, but to prevent signal leakage to the power stage.

Preferably, the third impedance matching and bypass circuit portion and the fourth impedance matching and bypass circuit portion receive power from the power stage in the first power mode, and receive power from the impedance converter in the second power mode. It may be configured to receive.

Preferably, the input signal power amplified by the first and second drive stages may be configured to bypass the power stage without using a switch circuit.

Preferably, the voltage control circuit unit and the power stage control circuit unit for controlling the voltage applied to the power stage; It may be configured to include a drive stage control circuit for controlling the voltage applied to the first and second driving stage.

Preferably, the power stage control circuit portion and the driving stage control circuit portion may be configured to operate by receiving the same digital signal input.

Preferably, the power stage control circuit unit may be configured to supply power to the power stage in the first power mode, and to cut off power supplied to the power stage in the second power mode.

Preferably, the driving stage control circuit unit controls the supply voltage to increase the standby current of the first driving stage in the first power mode, and decreases the standby current of the first driving stage in the second power mode. Can be configured to control the supply voltage.

Preferably, the driving stage control circuit unit controls the supply voltage to increase the standby current of the second driving stage in the first power mode, and decreases the standby current of the second driving stage in the second power mode. Can be configured to control the supply voltage.

Preferably, the driving stage control circuit unit controls the supply voltage to reduce the standby current of the first driving stage in the first power mode, and increases the standby current of the first driving stage in the second power mode. Can be configured to control the supply voltage.

Preferably, the driving stage control circuit unit controls the supply voltage to reduce the standby current of the second driving stage in the first power mode, and increases the standby current of the second driving stage in the second power mode. Can be configured to control the supply voltage.

Preferably, the power stage control circuit unit may be implemented in any one form of a circuit of a region indicated by a dotted line in FIGS. 5 (a) to 5 (d).

Preferably, the driving stage control circuit unit may be implemented in any one form of a circuit of a region indicated by a dotted line in FIGS. 6 (a) to 6 (d).

Preferably, the first power mode and the second power mode may be determined according to a control voltage signal of the voltage control circuit unit, which is a digital signal.

Preferably, the first power mode is when the output power is high, and the second power mode is when the output power is low.

Preferably, the high efficiency bypass switching multi-mode power amplifying apparatus according to the present invention may be implemented to include any N stage driving stage and any M stage power stage.

Hereinafter, an embodiment of the high efficiency multi-mode power amplifying apparatus according to the present invention together with the accompanying drawings will be described in more detail.

Figure 2 shows the configuration of a high efficiency bypass switching multi-mode power amplification device implemented in two stages according to an embodiment of the present invention. The high efficiency bypass switching multi-mode power amplification device illustrated in FIG. 2 is operated by being divided into a first power mode and a second power mode according to the magnitude of the output power, wherein the first power mode is a high output power. The second power mode means low output power. The two-stage high efficiency bypass switching multi-mode power amplification device includes an input matching unit (80); A driving stage (100) for amplifying the input signal transmitted through the input matching unit (80); The first impedance matching and bypass circuit unit 130 and the second impedance matching and bypass circuit unit for transmitting the signal amplified by the driving stage 100 to the power stage 120 or the impedance converter 170 according to the power mode. 140; A power stage 120 for amplifying the signal of the driving stage 100 with a large power in a first power mode; The third impedance matching and bypass circuit unit 150 and the fourth impedance matching and bypass circuit unit 160 for transmitting the signal transmitted through the power stage 120 or the impedance converter 170 to the output terminal 240 without loss. ); When the signal transmitted from the driving stage 100 in the second power mode exits to the output terminal 240 through the third impedance matching and bypass circuit unit 150 and the fourth impedance matching and bypass circuit unit 160. Impedance converter 170 for matching the impedance to prevent a reduction in the added efficiency due to the; It receives a signal for determining the output power mode given by the system to control the power supply of the power stage 120 and comprises a voltage control circuit 95 for controlling the standby current of the drive stage 100 according to the power mode. 2 is different from the conventional bypass switching multi-mode power amplifying apparatus, in which the voltage control circuit 95 is connected to the driving stage 100 as well as the power stage 120, thereby bypassing the multi-mode power amplifying apparatus. Is to control the operation of.

Figure 3 shows the configuration of a high efficiency bypass switching multi-mode power amplification device implemented in three stages according to an embodiment of the present invention. The high efficiency bypass switching multi-mode power amplifier shown in FIG. 3 operates in a first power mode and a second power mode according to the magnitude of the output power, and the first power mode is a high output power. The second power mode means low output power. The three-stage high efficiency bypass switching multi-mode power amplification apparatus includes an input matching unit (80); A first driving stage (100) for amplifying the input signal transmitted through the input matching unit (80); An impedance matching unit 85 transferring the signal amplified by the first driving stage 100 to the second driving stage 105; A second driving stage 105 for amplifying the signal transmitted through the impedance matching unit 85 again; The first impedance matching and bypass circuit unit 130 and the second impedance matching and bypass transferring the signal amplified by the second driving stage 105 to the power stage 120 or the impedance converter 170 according to the power mode. A pass circuit unit 140; A power stage 120 for amplifying the signal of the second driving stage 105 with a large power in a first power mode; The third impedance matching and bypass circuit unit 150 and the fourth impedance matching and bypass circuit unit 160 for transmitting the signal transmitted through the power stage 120 or the impedance converter 170 to the output terminal 240 without loss. ); In the second power mode, the signal transmitted from the second driving stage 105 passes through the third impedance matching and bypass circuit unit 150 and the fourth impedance matching and bypass circuit unit 160 to the output terminal 240. An impedance converter 170 for matching impedance to prevent a decrease in additional efficiency due to mismatches; Controlling the power supply of the power stage 120 by receiving a signal for determining the output power mode given by the system, and controlling the standby current of the first and second driving stages 100 and 105 according to the power mode. The circuit part 95 is comprised. Since the structure of FIG. 3 differs from the structure of FIG. 2, the voltage control circuit 95 is applied not only to the power stage 120 but also to the first driving stage 100 and the second driving stage 105. Connected to control the operation of the bypass switching multi-mode power amplification device.

Figure 4 (a) shows the configuration of the voltage control circuit portion of the conventional bypass switching multiple power amplifier.

Figure 4 (b) shows the configuration of the voltage control circuit portion used for high efficiency bypass switching multiple power mode operation according to an embodiment of the present invention. The voltage control circuit unit is configured to include a power stage control circuit unit for controlling the voltage applied to the power stage and a driving stage control circuit unit for controlling the voltage applied to the driving stage, wherein the control voltage signal given by the system is in the form of a digital signal. The power stage control circuit unit 90 and the driving stage control circuit unit 96 are respectively entered.

When operating in the first power mode, the power stage control circuitry 90 connected to the power stage 120 to supply power to the power stage 120, so as to obtain a high output power from the power stage 120, The driving stage control circuit unit 96 connected to the driving stage 100 increases the standby current of the driving stage 100 to control characteristics such as linearity and gain required in the first power mode.

When operating in the second power mode, the power stage control circuit unit 90 connected to the power stage 120 cuts off the power of the power stage 120 to prevent DC power consumption of the power stage 120, and the driving stage ( Drive stage control circuitry 96 coupled to 100 reduces the quiescent current of drive stage 100 to minimize DC power consumption in the second power mode.

4 (c) shows a circuit configuration of the voltage control circuit unit 95 according to the embodiment of the present invention. In general, when the control voltage signal is at a low voltage, such as 0V, it is in the first power mode, and at a high voltage, such as 3V, it is in the second power mode. That is, the power mode is determined according to the control voltage signal of the voltage control circuit part which is a digital signal. Based on these digital signals, the power stage control circuit section 90 and the drive stage control circuit section 96 are each simply implemented using one transistor. The power stage control circuit 90, which is basically required for the bypass switching multi-mode power amplifier, is connected to the bias circuit of the power stage 120. Thus, when operating in the first power mode, the transistor 91 of the bias circuit operates and has a power stage standby current capable of producing high output power, and when operating in the second power mode, the power stage control circuit unit By 90, the voltage of the connection node 71 drops to almost 0V, so that the transistor 91 of the bias circuit does not operate, so that the power supply of the power stage is cut off.

When the driving stage control circuit unit 96 operates in the first power mode, the driving stage control circuit unit 96 is turned off to control the standby current of the driving stage to generate high output power. In operation, the drive stage control circuitry 96 operates to reduce the bias current of the drive stage, thereby reducing the standby current of the drive stage.

5A to 5D show various circuit configurations for constructing the power stage control circuit section constituting the voltage control circuit section 95.

6 (a) to 6 (d) show various circuit configurations for constituting the drive stage control circuit section 96 constituting the voltage control circuit section 95 together with the power stage control circuit.

The driving stage control circuit unit of FIG. 6 (a) is configured by connecting a resistor to both the collector and the emitter of the transistor, and the driving stage control circuit unit of FIG. 6 (b) is configured by connecting a resistor to only the emitter of the transistor. .

In addition, the driving stage control circuit unit implemented in FIG. 6 (c) is configured by connecting a resistor only to the collector of the transistor, and the driving stage voltage control circuit unit implemented in FIG. 6 (d) is configured by using a diode in the collector of the transistor. When a current flows through the diode, a constant voltage is applied across the diode, which has the advantage of reducing the magnitude of the resistance according to the diode being subjected to a large resistance, usually a few kiloohms.

5 to 6 are only some examples of possible circuit configurations, and the power stage control circuit portion and the drive stage control circuit portion according to the present invention are not limited to the above FIGS. 5 to 6.

7 is a graph illustrating the current characteristics of the high efficiency bypass switching multi-mode power amplification device implemented according to an embodiment of the present invention.

In the first power mode, there is no difference from the characteristics of the conventional bypass switching multi-mode power amplifier, but in the second power mode in which the standby current of the driving stage is reduced, the current consumption is reduced as the output power decreases. It can be seen that the power consumption of the mode power amplification device is further reduced.

8 is a graph illustrating the additional efficiency characteristics of the high efficiency bypass switching multi-mode power amplification device implemented according to an embodiment of the present invention.

In the first power mode, the additional efficiency characteristic of the conventional bypass switching multi-mode power amplifier is not different from that of the conventional power supply. However, in the second power mode in which the standby current of the driving stage is reduced, the additional efficiency characteristic is reduced as the output power decreases. It shows a significant increase over the added efficiency characteristic of the pass switching multi-mode power amplifier. In addition, since the improvement of the additional efficiency characteristic in the second power mode is greatly influenced by the value of the standby current of the bypass switching multi-mode power amplifier, a further additional efficiency characteristic can be obtained by further lowering the value of the standby current. .

9 is a graph illustrating an ACPR characteristic of a high efficiency bypass switching multi-mode power amplification device implemented according to an embodiment of the present invention.

In the CDMA mobile communication, the minimum linearity required by the system must be satisfied. Since the power amplifying device has the greatest influence on the linearity required by the system, the power amplifying device is required to have a good linearity. ACPR (Adjacent Channel Power Ratio) is used as a parameter representing the linearity, and a power amplification device having a good ACPR characteristic means that the linearity is excellent.

Because of the ACPR criteria required for power amplification devices, there is a limit to increasing the added efficiency of a general power amplification device, and almost all power amplification devices have a similar ACPR at high output power. Similarly, the present invention shows the same ACPR characteristics as the conventional bypass switching power amplifier in the first power mode.

On the other hand, in the second power mode, since the ACPR value of the power amplification device has a larger value than the required value, the additional efficiency in the second power mode may be increased by using this margin. In the second power mode, as shown in FIG. 7, the conventional bypass switching multi-mode power amplification device has a large difference compared to the required ACPR value, shown by the horizontal dotted line. However, if the quiescent current in the second power mode is reduced as in the present invention, even if the linearity is slightly deteriorated, the required ACPR can be satisfied, so that desired characteristics can be simultaneously obtained for linearity and added efficiency.

10 is a graph illustrating gain characteristics of a high efficiency bypass switching multi-mode power amplification device implemented according to an embodiment of the present invention.

Since the high efficiency bypass switching multi-mode power amplification device implemented according to an embodiment of the present invention reduces the standby current in the second power mode, the gain characteristic of the power amplification device has the characteristics as shown in FIG. 10. That is, in the first power mode, the gain characteristics are the same as those of the conventional bypass switching multi-mode power amplifier, but in the second power mode, as the output power increases due to the decrease in the standby current, as shown in FIG. The gain change characteristic is shown. However, since the gain change A can be adjusted to an acceptable level in the system, the gain change A can be adjusted according to the relationship between the decrease in the quiescent current and the gain change A.

11 illustrates a structure in which a high efficiency multi-mode power amplifying apparatus using a power mode switching structure according to an embodiment of the present invention comprises a driving stage of arbitrary N stages and a power stage of an arbitrary M stage. 2 and the three-stage, the application in Figure 3 can be applied to the high efficiency bypass switching multi-mode power amplification device consisting of the driving stage of the N stage and the power stage of the M stage. Of course.

In order to explain the invention, embodiments of the invention have been described above. However, the present invention is not limited to the contents of the drawings and the described description, and various forms of modifications and variations can be made without departing from the spirit of the present invention, which will be apparent to those skilled in the art. It is true.

The present invention has proposed a method for further increasing the added efficiency that the conventional bypass switching multi-mode power amplifying apparatus has when the output power is low. Due to the present invention, an additional voltage control circuit can be implemented very simply, can be implemented in a very small size, and can be integrated in a monolithic microwave integrated circuit (MMIC). It is easy to implement because it has no impact on operation in power mode. That is, the present invention can greatly increase the additional efficiency of the bypass switching multi-mode power amplifier in the second power mode without additional cost and effort, and the call of the terminal greatly affected by the additional efficiency in the second power mode. Since it shows a great effect on time, it is possible to extend the talk time of the terminal.

Figure 1 shows the configuration of a conventional bypass switching multi-mode power amplifier.

Figure 2 shows the configuration of a high efficiency bypass switching multi-mode power amplification device implemented in two stages according to an embodiment of the present invention.

Figure 3 shows the configuration of a high efficiency bypass switching multi-mode power amplification device implemented in three stages according to an embodiment of the present invention.

Figure 4 (a) conceptually shows the configuration of the voltage control circuit portion of the conventional bypass switching multi-mode power amplifier.

Figure 4 (b) conceptually shows the configuration of the voltage control circuit portion of the high efficiency bypass switching multi-mode power amplifying apparatus according to an embodiment of the present invention.

Figure 4 (c) shows the circuit configuration of the voltage control circuit portion of the high efficiency bypass switching multi-mode power amplifying apparatus according to an embodiment of the present invention.

5 (a) to 5 (d) show various circuit configurations of the power stage control circuit unit according to an embodiment of the present invention.

6 (a) to 6 (d) show various circuit configurations of the driving stage control circuit unit according to an embodiment of the present invention.

7 is a graph illustrating the current characteristics of the high efficiency bypass switching multi-mode power amplification device implemented according to an embodiment of the present invention.

8 is a graph illustrating the additional efficiency characteristics of the high efficiency bypass switching multi-mode power amplification device implemented according to an embodiment of the present invention.

9 is a graph illustrating an ACPR characteristic of a high efficiency bypass switching multi-mode power amplification device implemented according to an embodiment of the present invention.

10 is a graph illustrating gain characteristics of a high efficiency bypass switching multi-mode power amplification device implemented according to an embodiment of the present invention.

FIG. 11 is a block diagram illustrating a high efficiency bypass switching multi-mode power amplification device implemented as an (N + M) stage according to an embodiment of the present invention. The structure is shown.

Claims (29)

In the bypass switching multi-mode power amplification apparatus comprising a drive stage for amplifying the input signal power via an input impedance matching circuit, A power stage for reamplifying and outputting the input signal power amplified by the driving stage; A first impedance matching and bypass circuit unit and a second impedance matching and bypass circuit connected between the driving stage and the power stage to perform an impedance matching function so as to transmit the input signal power amplified by the driving stage to the power stage at the maximum. A pass circuit portion; A voltage control circuit unit connected to the driving stage and the power stage and configured to apply different voltages to the first power mode and the second power mode divided according to the magnitude of the output power; A third impedance matching and bypass circuit portion and a fourth impedance matching and bypass circuit portion connected between the power stage and the output terminal to perform an impedance matching function so that the signal power re-amplified by the power stage can be outputted to the maximum; ; And The input signal power amplified by the driving stage is received through the first impedance matching and bypass circuit section and the second impedance matching and bypass circuit section to receive a third impedance matching and bypass circuit section and a fourth impedance matching and bypass circuit section. High efficiency bypass switching multi-mode power amplification apparatus comprising an impedance converter for outputting. According to claim 1, In the case of the first power mode, the first impedance matching and bypass circuit unit and the second impedance matching and bypass circuit unit transmit an input signal amplified by the driving stage to the power stage but leak the signal to the impedance converter. In the case of the second power mode, the high efficiency bypass switching multi-mode power amplification device, characterized in that for transmitting the input signal amplified by the drive stage to the impedance converter to prevent signal leakage to the power stage. . According to claim 1, The third impedance matching and bypass circuit unit and the fourth impedance matching and bypass circuit unit may receive power from the power stage in the first power mode, and power from the impedance converter in the second power mode. High efficiency bypass switching multi-mode power amplifier. According to claim 1, And the input signal power amplified by the drive stage bypasses the power stage without using a switch circuit. According to claim 1, The voltage control circuit unit includes a power stage control circuit unit for controlling a voltage applied to the power stage and a driving stage control circuit unit for controlling a voltage applied to the driving stage. . The method of claim 5, And the power stage control circuit and the driving stage control circuit are operated by receiving the same digital signal input. The method of claim 5, The power stage control circuit unit supplies power to the power stage in the first power mode, and cuts off the power supplied to the power stage in the second power mode. . The method of claim 5, The driving stage control circuit unit controls the supply voltage to increase the standby current of the driving stage in the first power mode, and controls the supply voltage to reduce the standby current of the driving stage in the second power mode. High efficiency bypass switching multi-mode power amplifier. The method of claim 5, The driving stage control circuit unit controls the supply voltage to reduce the standby current of the driving stage in the first power mode, and controls the supply voltage to increase the standby current of the driving stage in the second power mode. High efficiency bypass switching multi-mode power amplifier. The method of claim 5, The power stage control circuit unit is a high efficiency bypass switching multi-mode power amplification apparatus, characterized in that implemented in any one form of the circuit of the region shown in dotted lines in Figs. The method of claim 5, The driving stage control circuit unit is a high efficiency bypass switching multi-mode power amplification device, characterized in that implemented in any one form of the circuit of the region shown in dotted lines in Figs. 6 (a) to 6 (d). The method according to any one of claims 1 to 11, And the first power mode and the second power mode are determined according to a control voltage signal of the voltage control circuit part as a digital signal. The method according to any one of claims 1 to 11, And wherein the first power mode is a case where the output power is high and the second power mode is a case where the output power is low. In the bypass switching multi-mode power amplifying apparatus comprising a first driving stage and a second driving stage for amplifying the input signal power through an input impedance matching circuit, A second driving stage for amplifying the signal power amplified by the first driving stage: An impedance matching unit connected between the first driving stage and the second driving stage so as to transmit the input signal power amplified by the first driving stage to the second driving stage to perform an impedance matching function; A power stage for reamplifying and outputting the input signal power amplified by the second driving stage; A first impedance matching and bypass circuit unit and a second circuit connected between the second driving terminal and the power terminal to perform an impedance matching function so as to transmit the input signal power amplified by the second driving terminal to the power stage to the maximum; Impedance matching and bypass circuitry; A voltage control circuit unit connected to the first driving stage, the second driving stage, and the power stage and applying different voltages to the first power mode and the second power mode divided according to the magnitude of the output power; A third impedance matching and bypass circuit portion and a fourth impedance matching and bypass circuit portion connected between the power stage and the output terminal to perform an impedance matching function so that the signal power re-amplified by the power stage can be outputted to the maximum; ; And The input signal power amplified by the second driving stage is received through the first impedance matching and bypass circuit section and the second impedance matching and bypass circuit section to receive a third impedance matching and bypass circuit section and a fourth impedance matching and bypass section. A high efficiency bypass switching multi-mode power amplification apparatus comprising an impedance converter outputting to a pass circuit section. The method of claim 14, In the first power mode, the first impedance matching and bypass circuit unit and the second impedance matching and bypass circuit unit may transfer an input signal amplified by the second driving stage to the power stage, but to the impedance converter. High efficiency bypass switching multiplexing to prevent signal leakage, and in the case of the second power mode to transfer the input signal amplified by the second drive stage to the impedance converter, but prevents signal leakage to the power stage Mode power amplification device. The method of claim 14, The third impedance matching and bypass circuit unit and the fourth impedance matching and bypass circuit unit may receive power from the power stage in the first power mode, and power from the impedance converter in the second power mode. High efficiency bypass switching multi-mode power amplifier. The method of claim 14, The high efficiency bypass switching multi-mode power amplification apparatus, characterized in that the input signal power amplified by the first drive stage and the second drive stage bypasses the power stage without using a switch circuit. The method of claim 14, The voltage control circuit unit includes a power stage control circuit unit for controlling a voltage applied to the power stage; A high efficiency bypass switching multi-mode power amplifying apparatus, comprising: a driving stage control circuit for controlling a voltage applied to the first driving stage and the second driving stage. The method of claim 18, And the power stage control circuit and the driving stage control circuit are operated by receiving the same digital signal input. The method of claim 18, The power stage control circuit unit supplies power to the power stage in the first power mode, and cuts off the power supplied to the power stage in the second power mode. . The method of claim 18, The driving stage control circuitry controls the supply voltage to increase the standby current of the first driving stage in the first power mode, and reduces the supply voltage to reduce the standby current of the first driving stage in the second power mode. High efficiency bypass switching multi-mode power amplification device, characterized in that for controlling. The method of claim 18, The driving stage control circuit unit controls the supply voltage to increase the standby current of the second driving stage in the first power mode, and reduces the supply voltage to reduce the standby current of the second driving stage in the second power mode. High efficiency bypass switching multi-mode power amplification device, characterized in that for controlling. The method of claim 18, The driving stage control circuit unit controls the supply voltage to reduce the standby current of the first driving stage in the first power mode, and increases the standby voltage of the first driving stage in the second power mode. High efficiency bypass switching multi-mode power amplification device, characterized in that for controlling. The method of claim 18, The driving stage control circuit unit controls the supply voltage to reduce the standby current of the second driving stage in the first power mode, and increases the standby voltage of the second driving stage in the second power mode. High efficiency bypass switching multi-mode power amplification device, characterized in that for controlling. The method of claim 18, The power stage control circuit unit is a high efficiency bypass switching multi-mode power amplification apparatus, characterized in that implemented in any one form of the circuit of the region shown in dotted lines in Figs. The method of claim 18, The driving stage control circuit unit is a high efficiency bypass switching multi-mode power amplification device, characterized in that implemented in any one form of the circuit of the region shown in dotted lines in Figs. 6 (a) to 6 (d). The method according to any one of claims 14 to 26, And the first power mode and the second power mode are determined according to a control voltage signal of the voltage control circuit part as a digital signal. The method according to any one of claims 14 to 26, And wherein the first power mode is a case where the output power is high and the second power mode is a case where the output power is low. The method according to claim 1 or 14, A high efficiency bypass switching multi-mode power amplification apparatus, which may be implemented to include any N stage driving stages and any M stage power stages.