KR20050086638A - Method and device for fine synchronization of a digital telecommunication receiver - Google Patents

Abstract

A method for the synchronization of a digital telecommunication receiver comprises the steps of: - storing a plurality of consecutive samples E-l, E, M, L, L+1 of an incoming spread spectrum signal in a delay line 56; - determining by interpolation between consecutive samples of the incoming spread spectrum signal, by means of a first digitally controlled interpolator 26, an interpolated early sample (e) anticipating an optimal sampling time instant; - determining by interpolation between consecutive samples of the incoming spread spectrum signal, by means of a second digitally controlled interpolator 24, an interpolated middle sample (m) corresponding to the optimal sampling time instant; - determining by interpolation between consecutive samples of the incoming spread spectrum signal, by means of a third digitally controlled interpolator 28, an interpolated late sample (1) delayed with respect to the optimal sampling time instant; - calculating an error signal Sigma as the difference between the energy of the symbols computed from the interpolated early sample (e) and the interpolated late (1) sample; - extracting the sign of the error signal Sigma - accumulating the sign of the error signal Sigma for the generation of control signals SE, SM, SL for controlling the interpolation phases of the digitally controlled interpolators used for determining the interpolated early (e), middle (m) and late (l) samples. The accumulated value has a positive saturation value of +4 and a negative saturation value of 4.

Description

METHOD AND DEVICE FOR Fine Synchronization Of A Digital Telecommunication Receiver

The present invention relates to a communication system, and more particularly to a fine synchronization method of a digital communication system. The invention also relates to a digital receiver for use in a Code Division Multiple Access (CDMA) system.

CDMA access technology is currently finding widespread use in third generation mobile communication systems (e.g., UMTS, CDMA2000) due to greater spectral efficiency compared to other access technologies.

In a CDMA system, a data sequence is spread by a pseudo noise code (hereinafter referred to as a "PN code") having a wide spectrum. The efficiency of these systems mainly depends on the receiver's ability to continuously maintain accurate phase synchronization between the received PN code and the locally generated PN code.

In fact, without accurate phase synchronization between the received PN code and the locally generated PN code, the performance loss of the receiver is several dB even for mismatches of half the chip period.

The phase synchronization process is mainly performed in two stages of code acquisition and code tracking. Code acquisition is an initial retrieval process that brings the locally generated code phase into the chip duration (T _C = 1 / F _C ) of the code inflowing. Code tracking is the process of achieving and maintaining fine alignment of chip boundaries between incoming code and locally generated code.

In particular, the present invention is generally associated with a code tracking portion of a receiver that is implemented in the form of a rake receiver.

For digital receivers, the key component is the analog-to-digital converter (ADC). In some applications, the sampling clock rate may in some cases not be synchronized with the incoming signal. For example, one of these applications is a CDMA base station receiver, where the sum of several signals asynchronously mixed together is received and digitized using one analog-to-digital converter. In these cases, since the sampling clock phase cannot be changed, fine time synchronization (ie, code tracking) between each user's received PN code and locally generated PN code must be achieved through a digital method.

The code tracking operation is performed by a synchronization unit. Several types of code tracking loops have been widely applied in practical applications, and the most popular solution is the so-called Early-Late Synchronizer.

The synchronizer, as shown in Fig. 1, receives the baseband signal y (t) as input from a receive front end that is oversampled at frequency f _s = N · F _C and has at least two samples (N> 2) per chip. Receive and provide the signal to a finger of a rake receiver having one sample per chip (ie, the optimal sample). Each finger of the rake receiver requires its own synchronizer because the time offset values of the other multipath components demodulated by the other fingers of the rake receiver are usually not equal.

Fine time synchronization is achieved by performing some sort of interpolation between the received samples to obtain an accurate value, or at least to approximate the received signal corresponding to the optimal sampling instant t _opt . This technique is well known, for example, in March 1993, F.M. FM Gardner's paper, " Interpolation in digital modems-Part I: Fundamentals ". IEEE Trans. Communications, vol. 41, pp. 502-508, or L. L. Erup, F. M. Gardner's article " Interpolation in digital modems-Part II: Implementation and Performance ".

The optimal sampling instant t _opt (t) varies over time due to the time variability of the radio channel and corresponds to the instant when the amplitude of the received signal is maximum and at the same time the intersymbol interference (ISI) is minimal. By sampling the received signal corresponding to the optimal sampling time, it is possible to maximize the signal-to-noise ratio (SNR) at the output of the receiver and thus minimize the bit error rate (BER). The optimal sampling instant can be observed as the maximum opening point in the eye diagram, as shown in FIG.

In the following, the principle of the synchronization device based on the known technology will be described. This description is based on the case of real signal y (t), but the extension to complex signal y (t) is also directly.

A block diagram of the synchronization device 1 described in the prior art is shown in FIG. The scheme considered is operated using a feedback loop. The time continuous signal y (t) is received at the input of the analog-to-digital converter 2. Signal y (t) is a series of pulses with period T _C , for example formed by a pair of root raised cosine (RRC) filters

Where u _k = {-1, + 1} is a sequence of transmitted chips, and h (t) is

Impulse response of an equivalent raised cosine (RC) with the above representation.

The unidirectional bandwidth of the signal y (t) is

Where α is the roll-off of the RRC forming filter.

The ADC converter 2 takes a sample of y (t) at the same time interval t _s corresponding to the ADC sampling frequency f _s = 1 / t _s . Sampling of the analog baseband signal may be performed at different sampling rates. However, the Nyquist criterion requires a minimum ADC sampling rate of twice the one-way signal bandwidth, i.e., f _s ≧ 2 · B.

At the output of the ADC converter 2, the signal sample y (n · t _s ) = y (n) is an interpolator that calculates the interpolated value y _I (m · t _s ) = y _I (m) at the time interval t _I. Provided in (4). The purpose of the interpolator is to increase the time resolution after ADC conversion, wherein the time interval t _I of the sample at the output of the interpolator is smaller than the time interval t _s of the sample at the output of the ADC. Generally,

Where K is an integer greater than one.

If the sample y (n) at the output of the ADC does not match the optimal time, the synchronizer first selects the optimal sampling moment. Is estimated and then the value of y (t) corresponding to the instant is calculated or approximated. And then the above value Is provided at the output of the synchronizer for subsequent signal processing.

The principle of time synchronization via digital interpolation is illustrated for the case of linear interpolation with K = 4 in FIG. 4.

In the example of FIG. 4, the signal y (t) corresponding to the optimal sampling instant t _opt is approximated to the interpolated value y _I (m + 3).

The interpolated value y _I (m + 3) is calculated as follows; First, the midpoint y _I (m + 2) between two consecutive samples y (n) and y (n + 1) at the output of the ADC is calculated:

.

Likewise, the other two interpolated values y _I (m + 1) and y _I (m + 3) are calculated as the average between one ADC sample and the interpolated value y _I (m + 2) calculated in the previous step. :

Of course, by using more complex interpolation methods (e.g. parabolic, cubic) or by increasing the interpolator resolution (i.e. by increasing K), the estimation of the received signal according to the optimal sampling moment is more accurate. can do.

The synchronization device of FIG. 3 also includes other elements necessary for the synchronization process. The data filter 5 processes the interpolated sample and selects the optimal sample for subsequent signal processing. The data filter is indicated within the feedback loop, but can also be placed outside the loop. When data filters are more complex than interpolators and relatively large sampling rates are used for interpolation, placing them outside the loop can be advantageous in terms of complexity.

The optimal sampling instant t _opt is evaluated by the time error detector block 6 and filtered by the loop filter 7. The purpose of the loop filter is to eliminate the effects of noise that can affect the optimal sampling time estimate. Finally, the loop filter output drives the controller 3, which provides a control signal to the interpolator 4.

Starting from the general structure of the synchronization device shown in FIG. 3, one can analyze the application of the special case of the digital CDMA receiver.

Known schemes for performing code tracking operations in CDMA receivers are, for example, Zone. The so-called early-rate synchronization circuit described in John G. Proakis' third edition of " Digital Communications ", Mc Graw-Hill, New York, 1995.

The application of interpolation and early-rate concepts for synchronization of CDMA receivers is known. R. De Gaudenzi, M. " A Digital Chip Timing Recovery Loop for Band-Limited Direct-Sequence Spread-Spectrum Signals ", November 1993, M. Luise. IEEE Trans. On Communications, vol. 41, No. 11, can be found in the paper.

The early-rate synchronization circuit uses the symmetry of the signal autocorrelation at the output of the receiver matching filter.

In the following, it is assumed that the signal at the input of the early-rate synchronization circuit is sampled using two samples per chip (N = 2). Then, two consecutive samples at the input of the early-rate synchronization circuit are spaced apart by T _C / 2 (T _C = 1 / F _C = chip period).

In order to introduce a suitable mathematical representation for sequences with different velocities, we denote e (k) = e (k T _C ) using the distinction time index k for the chip period. In addition, the diffusion factor is represented by SF. The period of the information symbol before the diffusion process is T _s = SF · T _C , and the distinguishing time index for this symbol is (k div SF), where A div B is the integer part of the quotient between A and B.

Each received chip may be characterized by initial, intermediate, and terminal samples defined as follows:

The initial sample is a sample that predicts the optimum sampling moment. Initial samples are denoted by e _I (k) and e _Q (k) for in-phase and in-quadrature components, respectively.

The intermediate sample is the sample corresponding to the peak of the impulse h (t) received at the optimal sample or equivalent, without time error. Intermediate samples are represented by m _I (k) and m _Q (k) for in-phase and quadrature components, respectively.

The late sample is a sample that is delayed for the optimal sampling instant. Terminal samples are denoted by l _I (k) and l _Q (k) for in-phase and quadrature components, respectively. The late sample of a given chip is also the initial sample of the next chip.

The definitions of the initial, middle and end samples are made clear in FIG. 5 for in-phase components and in case of perfect time synchronization. It can be noted from FIG. 5 that the intermediate sample is a sample with greater energy and minimum ISI. Therefore, it must be provided to the rake finger for descrambling operation and despreading operation.

In addition, from FIG. 5, it can be observed that when the impulse response of the complete system is symmetric and the system achieves perfect time synchronization, the energy of the initial and terminal samples is the same.

The two conditions of perfect time synchronization can be expressed as follows:

Perfect time synchronization ⇒ ε _m = m ² _I (k) + m ² _Q (k) = maximum

Perfect time synchronization ⇒ ε _e = e ² _I (k) + e ² _Q (k) = ε _l = l ² _I (k) + l ² _Q (k)

Where ε _e , ε _m , ε _l are the energies of the initial, middle and end samples, respectively.

If there is noise, it is usually difficult to identify the sample with the maximum energy. Instead of sampling the signal corresponding to the peak, the early-rate synchronization circuit identifies the optimal sampling instant via a second condition: the energy of the initial and terminal samples must be the same, or in other words, the difference between the two energies is zero ( ε _e -ε _l = 0). When this condition is met, the sample between the initial sample and the late sample (ie, the intermediate sample) is the best sample provided to the rake finger.

Given that the signal-to-noise ratio on the channel in the CDMA system is very low, the condition ε _e -ε _l = 0 must be verified for the symbol after despreading and consolidation operations. The average over the SF sample derives the average value of the initial and end sample energies and reduces the energy fluctuations due to noise and interference from other users.

A simplified block diagram of a prior art early-rate synchronization circuit is shown in FIG. 6 for the general case of real PN (pseudo noise) code c _c (k). However, even in the case of the complex PN code, the same configuration is effective by simply replacing the combination of the respective real multipliers with one complex multiplier.

The early-rate synchronization circuit of FIG. 6 uses two correlators: the first correlator performs despreading, consolidation and dump operations on the initial sample, while the second correlator performs the same operation on the late samples. The outputs of the two correlators are then squared to obtain the energy of the despread symbol and to modulate and phase rotate the data sequence introduced by the propagation channel. Finally, the error signal ξ is calculated by calculating the output difference of the two correlators.

After despreading, consolidating, squared and summating operations of in-phase and quadrature components, for a given time error τ = tt _opt

ξ (k div SF) = E (k div SF)-L (k div SF)

Is given by

The characteristics of the early-rate synchronization circuit in error signal ξ as a function of time error τ are shown in FIG. Due to the particular shape, the early-end characteristics are usually referred to as S curves.

From Fig. 7, when there is a time offset (τ ≠ 0), the error signal ξ at the output of the early-rate synchronization circuit is not zero, and the time positions of the initial, intermediate and terminal samples are obtained in order to obtain an optimal sampling instant (error Must be delayed or preceded).

Alternatives for finely adjusting the time position of the initial, middle and end samples without delaying or preceding the position are shown in Figures 8 and 9, in particular when the time offset τ = T _c / 4, It is constructed using a digital interpolator.

Two of these interpolators are used to calculate the initial sample E and the late sample L, while the third interpolator is used to calculate the intermediate sample M (ie, the optimal sample with the maximum energy). The initial and terminal samples are provided to the correlator for the calculation of the error signal ξ, while the intermediate samples are provided to the Rake finger for subsequent signal processing (descrambling, despreading, channel estimation and calculation, decoding, etc.).

Considering the initial sample E, the intermediate sample M, and the terminal sample L in FIG. 8, the linear interpolator has a predetermined resolution, and two consecutive samples of the initial sample E and the intermediate sample M or the intermediate sample M and the terminal sample L You can generate all samples between values. If the error signal is greater than zero, the optimal sampling instant is delayed for the intermediate sample M, so the optimal sample value can be calculated by linear interpolation between the intermediate sample M and the terminal sample L. In the same way for the case where the error signal is lower than zero, the optimal sample is calculated by linear interpolation between the initial sample E and the intermediate sample M.

As can be seen in FIG. 9, it is necessary to interpolate the initial sample E between the previous sample E-1 and the intermediate sample M in order to calculate the delay or leading shape of the initial sample E and the late sample L, which determine the error signal. In the same way, it may be necessary to interpolate the terminal sample L between the subsequent sample L + 1 and the intermediate sample M. Thus, a synchronizer based on an early-rate synchronization circuit needs to know about five consecutive samples E-1, E, M, L, L + 1 of the incoming signal mixed at intervals of T _c / 2. .

Three interpolators are used to finely adjust the time position of the initial, terminal and intermediate samples provided to the correlator and the rake finger, respectively. These interpolators are controlled by digital signals derived from the error signal ξ of the early-rate synchronization circuit. If the loop is correctly designed to get negative feedback, the system automatically minimizes the error signal by converging to a zero error condition. The minimum error condition is that the intermediate sample is the sample with the maximum energy and therefore the optimal sample.

The time positions of the three interpolated samples (initial, middle and end samples) are moved back and forth by the time factor δ when the error signal is positive or negative, respectively. The factor δ represents the temporal resolution of the interpolator and is usually T _c / 8.

Interpolation of intermediate samples with time resolution δ = T _c / 8 is usually sufficient to ignore the degradation of system performance for an ideal interpolator with infinite resolution. However, interpolators with a resolution of T _c / 8 are quite complex circuits that negatively affect the silicon area requirements on the chip.

Early and late samples are provided to the correlator to calculate the error signal ξ. The time difference Δ between the initial and terminal samples is defined as early-late spacing . Conventional implementations of early-rate synchronization circuits typically use a fixed initial-end interval that is usually equal to the chip period T _C.

Applicant has addressed the problem of reducing the overall complexity and silicon requirements of the synchronizer in a digital receiver for use in a CDMA system.

The Applicant has = a resolution of the digital receiver δ T _c / 8 the inner group mainly resolution is δ = T _c / 8 of mathematical operations required to perform a linear interpolation, that is, the summation, multiplication and division, and 3, a constant factor of 2 Is a fairly complex circuit due to the fact that it is a complex operation. The complexity of a single interpolator has a negative effect on the chip area, especially for base station receivers that require many such interpolators to process signals of multiple users.

Indeed, each Rake finger of the digital receiver requires six interpolators, i.e., initial, intermediate and terminal interpolators for all of the signal components I and Q. Also, when considering a UMTS base station with 64 different rake receivers, each of which is an N _f = 8 finger, as a possible example, it is evident from these numbers that the use of a reduced interpolator is a notable advantage.

In view of the above, it is an object of the present invention to provide a method and apparatus for fine synchronization of a digital receiver with reduced complexity. Due to the reduced complexity, the area of the silicon chip in which the system is integrated can be reduced.

As claimed in the claims, these and other objects are also achieved by the methods and apparatus implemented according to the invention.

1 is a block diagram of a prior art module of a rake receiver;

2 shows an eye diagram showing the optimal sampling time;

3 is a block diagram of a synchronization device of the prior art;

4 is a graph illustrating time synchronization by signal interpolation;

5 is a graph showing initial, middle and end samples on a received signal;

6 is a simplified block diagram of an Early-Late synchronizer;

7 is a graph of an error signal in an early-rate synchronization circuit;

8 and 9 show known principles of a digital early-rate synchronization circuit using interpolation;

10 is a complete block diagram of a digital early-rate synchronization circuit with a feedback loop in accordance with the present invention;

11 is a digitally controlled interpolator used in the synchronization circuit of FIG. 10;

12 shows the initial-end interval as a function of time error τ according to the present invention;

13 and 14 are tables showing the mathematical operations required to perform linear interpolation according to the present invention;

15 is a block diagram of the complete structure of the interpolator according to the present invention; And

FIG. 16 is a table illustrating values of a control signal of the interpolator of FIG. 15.

Applicants can use the variable time distances between the initial and terminal samples to significantly simplify the structure of the corresponding interpolator. To this end, the interpolation structure of the device provides a variable initial-end period as a function of time error τ.

The method and apparatus according to the invention simplify the interpolation of the initial and terminal samples of each rake finger, thus reducing the complexity of the overall system.

The apparatus according to the invention is described in more detail in the case of a UMTS receiver operating in a Universal Mobile Telecommunicaitons System (UMTS), in particular in a Frequency Division Duplex (FDD) mode.

A complete early-rate synchronization circuit 18 is shown in FIG. 10, which can be used in a digital communication receiver to maintain fine alignment between an incoming spread spectrum signal and locally generated code. Is shown.

Apparatus 18 includes a delay line 56 for storing a plurality of consecutive samples E-1, E, M, L, L + 1 of the incoming spread spectrum signal; A first digitally controlled interpolator 26 for determining an interpolated initial sample e that predicts an optimal sampling time by interpolation between successive samples; A second digitally controlled interpolator (24) for determining an interpolated intermediate sample (m) corresponding to the optimal sampling time by interpolation between successive samples; A third digitally controlled interpolator (28) for determining an interpolated terminal sample (1) delayed for said optimal sampling time by interpolation between successive samples; Perform the same operation on the first correlator 32 performing the despreading operation, the integration operation and the dump operation on the interpolated initial sample e, and the interpolated terminal sample l. A second correlator 30; A low pass filter 22 for averaging the error signal ξ for predetermined symbols; A circuit (23) for extracting a sign of the error signal ξ; And internal registers for generating control signals S _E , S _M , and S _L for controlling the interpolation phases of the first, second and third digitally controlled interpolators 26, 24, and 28. And a control signal generator 66 for accumulating the sign of the error signal ξ, and the outputs of the two correlators obtain the energy of the despread symbol and modulate the data sequence introduced by the propagation channel. Squared to eliminate phase rotation, the error signal ξ is calculated by finally taking the two correlator output differences.

The time distance between the interpolated initial sample (e) and the late sample (1) varies with respect to the control signals (S _E , S _M , and S _L ), as described in detail below.

The early-rate synchronization circuit 18 is a closed loop control system, in which the bandwidth of the closed loop control system is relatively narrow compared to the chip rate F _C. The low pass filter 22 used to average the error signal ξ for certain symbols determines the loop bandwidth. To maintain accurate sign synchronization, the loop bandwidth must be large enough to track the instantaneous delay of the correlation function, but narrow enough not to be affected by noise and interference.

Thus, the system automatically minimizes the error signal by converging to a condition where the error is zero. The minimum error condition means that the intermediate sample is the sample with the maximum energy and therefore the optimal sample.

Each digital control interpolator 24, 26 and 28 is a device, such as the device shown in FIG. 11, receiving three input signals, denoted by y _E , y _M , y _L , and a control signal denoted by SEL. The output of interpolator y _OUT is a function of four inputs, y _OUT = f (y _E , y _M , y _L , SEL).

The inputs y _E , y _M and y _L are supplied with three consecutive samples (samples stored in the delay line 56) of the interpolated digital signal y (t). The time position, or interpolation phase, of the interpolated sample can be selected via the control signal SEL described in detail below.

The intermediate sample is provided to the rake finger for other baseband processing and should be chosen with sufficient accuracy so as not to reduce the receiver's performance in terms of bit error rate (BER).

According to the invention, the temporal resolution of the first and third digitally controlled interpolators 26 and 28 is lower than the temporal resolution of the second digitally controlled interpolator 24.

In particular, successive input samples E-1, E, M, L, L + 1 are spaced apart by T _C / (2 · n), T _C is the period of the fundamental waveform, and n = 1, 2, 3, … Assuming that is an integer, the time resolution used to determine the interpolated initial sample (e) and the late sample (l) by interpolation is T _C / (4 · n), while the intermediate interpolated sample (m) is determined. The temporal resolution used to do this is T _C / (8 · n).

In the embodiment shown in FIG. 10, since the input samples are time spaced T _C / 2, the early and late interpolators 26 and 28 have a time resolution of T _C / 4 while the intermediate interpolator 24 is Has a time resolution of T _C / 8.

Figure 12 shows five consecutive received signal samples (E-1, E, M, L, L + 1) 56 spaced apart by T _C / 2 on the time axis, and nine other time errors τ (τ =). 9 different interpolation patterns from -T _C / 2 to τ = T _C / 2). The interpolated initial sample is shown in FIG. 12 as the square symbol 50, the interpolated intermediate sample as the diamond symbol 54, and the interpolated terminal sample as the asymbol 52.

As can be seen in FIG. 12, the initial-end interval Δ may vary and, alternatively, take two values T _C or 3 · T _C / 4 as a function of time error τ.

In particular, the initial-end interval Δ is equal to T _C when time error τ is zero or an even multiple of T _C / 8 (corresponding to an even value of control signal S _M ):

Δ = τ, τ = ± 2 · n · T _C / 8 and n = 0,1,2,... If

The initial-end interval Δ is equal to 3 · T _C / 4 when the odd multiple of T _C / 8 (corresponding to the odd value of the control signal S _M ):

Δ = 3 T _C / 4, tau = ± (2 n +1) T _C / 8 and n = 0,1,2,. If

The interpolated intermediate sample 54, whose resolution is calculated as T _C / 8, is always taken as an intermediate point between the initial sample 50 and the terminal sample 52 to ensure error signal balancing.

The output value y _OUT = f (y _E , y _M , y _L , SEL) of the digitally controlled interpolator 24 having a time resolution of T _C / 8 is listed in the table of FIG. 13.

The table in FIG. 14 shows the output values y _OUT = f (y _E , y _M , y _L , SEL) of the digitally controlled interpolators 26, 28 with time resolution δ = T _C / 4.

As shown in FIG. 14, the mathematical operation required to perform linear interpolation with resolution δ = T _C / 4 is only division and sum of two (ie right shift), so the hardware complexity of such linear interpolation is resolution δ Much lower than the interpolator with = T _C / 8.

Figure 15 shows the complete structure of the initial-middle-end interpolator for one signal component. While the structure is shown for the in-phase component I of the signal, the same structure is also valid for the quadrature Q component.

The block generating the control signal for interpolation is shown as block 66 in FIGS. 10 and 15.

The control signal generator 66 receives as input the sign of the error signal ξ calculated according to the following rule,

The control signals S _E , S _M , and S _L for each of the three interpolators of the initial, middle and terminal samples are provided as outputs. The control signals S _E , S _M , and S _L generated by block 66 are the same for both in-phase component and quadrature component interpolator.

The control signal S _M of the interpolator 24 operating on the intermediate sample has a saturation for a value greater than 4 or less than -4 in order to generate the control signal according to the table of FIG. 13. This is obtained by accumulating the code of the error signal. The algorithm used for the generation of signal S _M is as follows:

S _M (-1) = 0

S _M (n) = S _M (n-1) + sign (ξ)

If [S _M (n)> 4], then S _M (n) = 4

If [S _M (n) <4], S _M (n) =-4.

The values of control signals S _E and S _L for each of the initial and terminal interpolators can be derived as a function of control signal S _M of FIG. 11 and from the table of FIG. 14. In particular, the values of the control signals S _E , S _M , and S _L as a function of the time offset τ are given in the table of FIG. 16.

The representations of the control signals S _E , S _M , and S _L can be calculated as a function of the signal S _M :

Here, the function ┗ · ┛ approximates the independent variable to the nearest lower integer.

Further complexity can be reduced by using one time multiplexing interpolator for the calculation of the interpolated initial sample and the interpolated late sample. Using one correlator, multiplexing is possible because the initial sample and the late sample are calculated at different time intervals: the initial sample is calculated during the first half of each DPCCH bit, and the late sample is calculated during the second half.

The apparatus described above includes storing a plurality of consecutive samples E-1, E, M, L, L + 1 of the spread spectrum signal entering the delay line 56; Determining an interpolated initial sample (e) that predicts an optimal sampling time by interpolation between successive samples of the incoming spread spectrum signal by a first digitally controlled interpolator (26); Determining an interpolated intermediate sample (m) corresponding to the optimal sampling time by interpolation between successive samples of the incoming spread spectrum signal by a second digitally controlled interpolator (24); Determining, by interpolation between successive samples of the incoming spread spectrum signal by a third digitally controlled interpolator (28), an interpolated terminal sample (1) delayed for the optimal sampling time; Calculating an error signal ξ by the difference between the energy of the symbol calculated from the interpolated initial sample (e) and the interpolated late sample (l); Extracting the error signal ξ; And generation of control signals S _E , S _M , and S _L for determining the interpolation phase of the digitally controlled interpolator used to calculate the interpolated initial sample (e), intermediate sample (m) and terminal sample (l). Enabling fine synchronization of the digital communication receiver by a method for maintaining a fine alignment between the incoming spread spectrum signal and the locally generated code, which comprises accumulating the code of the error signal ξ for the sake of brevity. The accumulated value has a positive saturation of +4 and a negative saturation of -4.

The phase or time position of the initial and terminal interpolators 26 and 28 may be varied as the time distance between the interpolated initial sample (e) and the terminal sample (l), as described above with reference to FIG. In a manner controlled by the control signals S _E and S _L.

In particular, the time distance between the interpolated initial sample (e) and the terminal sample (l) is a T _C value which is a period of the fundamental waveform when the first control signal (S _M ) is an even value, or the first control signal (S). _{When M} ) is an odd value, the value alternates with 3 · T _C / 4.

Due to the variable spacing between the initial and terminal samples, the temporal resolution of each interpolator 26, 28 may be lower than the temporal resolution of interpolator 24 used to determine the interpolated intermediate sample m. .

In the above embodiment, the temporal resolution of interpolators 26, 28 is half the temporal resolution of interpolator 24, in particular, the temporal resolution of interpolators 26, 28 is T _C / 4, The temporal resolution of 24 is T _C / 8.

In general, the relationship between the interpolator's time resolution is as follows, assuming that the samples of the incoming spread spectrum signal are spaced T _C / (2 · n) time, T _C is the period of the fundamental waveform, and n is an integer. :

T _C / (4 · n) is the time resolution of interpolators 26 and 28; And

T _C / (8 · n) is the temporal resolution of the interpolator 24.

According to the drawing of FIG. 12, the time distance between the interpolated initial sample e and the terminal sample l alternates the T _C value or the 3 · T _C / 4 value according to the values of the control signals S _E and S _L. .

Claims (21)

A fine synchronization method of a digital communication receiver comprising a code tracking process for maintaining fine alignment between an incoming spread spectrum signal and a locally generated code, Storing a plurality of consecutive samples (E-1, E, M, L, L + 1) of the spread spectrum signal entering the delay line 56; Interpolated initial samples predicting an optimal sampling time instant by interpolation between successive samples of the incoming spread spectrum signal by a first digitally controlled interpolator 26. determining (e); Determining an interpolated intermediate sample (m) corresponding to the optimal sampling time by interpolation between successive samples of the incoming spread spectrum signal by a second digitally controlled interpolator (24); Determining, by interpolation between successive samples of the incoming spread spectrum signal by a third digitally controlled interpolator (28), an interpolated terminal sample (1) delayed for the optimal sampling time; A fine synchronization method of a digital communication receiver comprising calculating an error signal (ξ) with a difference between energy of a symbol calculated from the interpolated initial sample (e) and the interpolated late sample (l). Extracting a sign of the error signal (ξ); And Accumulating the sign of the error signal (ξ) for generation of control signals S _E , S _M , and S _L for controlling the interplation phase of the digitally controlled interpolator; , The time distance between the interpolated initial sample (e) and the late sample (l) changes in relation to the first control signal (S _M ), and determines the interpolated initial sample (e) and the late sample (l) by interpolation. And the time resolution used to determine is lower than the time resolution used to determine the interpolated intermediate sample (m) by interpolation. The method of claim 1, Accumulating the code of the error signal (ξ), wherein the accumulated value defines a positive saturation value of +4 and a negative saturation value of -4. The method according to claim 1 or 2, The time distance between the initial sample (e) and the terminal sample (l) is a T _C value that is a period of the fundamental waveform when the first control signal (S _M ) is an even value, or the first control signal (S _M ). A fine synchronization method for a digital communication receiver having alternating values of 3 · T _C / 4 when is an odd value. The method of claim 2, A second control signal (S _E ) for controlling the first digitally controlled interpolator (26) is generated as a function of the first control signal (S _M ) according to the following equation; Here, the function ┗ · ┛ is a fine synchronization method of the digital communication receiver approximating the independent variable to the nearest lower integer. The method of claim 2, A third control signal S _L for controlling the third digital control interpolator 28 is generated as a function of the first control signal S _M according to the following equation; Here, the function ┗ · ┛ is a fine synchronization method of the digital communication receiver approximating the independent variable to the nearest lower integer. The method of claim 1, The time resolution used to determine the interpolated initial sample (e) and the late sample (l) by interpolation is half of the time resolution used to determine the interpolated intermediate sample (m) by interpolation. Fine sync method. The method of claim 6, The plurality of consecutive samples (E-1, E, M, L, L + 1) are time spaced by T _C / (2 · n), where T _C is the period of the fundamental waveform, n is an integer, The time resolution used to determine the interpolated initial sample (e) and the late sample (l) by interpolation is T _C / (4 · n), which is used to determine the interpolated intermediate sample (m) by interpolation. Time synchronization is T _C / (8 · n). The method of claim 6, The plurality of consecutive samples (E-1, E, M, L, L + 1) are time spaced by T _C / 2, where T _C is the period of the fundamental waveform, and the interpolated initial sample (interpolated by interpolation) e) and the time resolution used to determine the terminal sample (l) is T _C / 4, and the time resolution used to determine the interpolated intermediate sample (m) by interpolation is T _C / 8. Fine sync method. A digital communication receiver having a device for maintaining a fine alignment between an incoming spread spectrum signal and a locally generated code, the digital communication receiver comprising: A delay line 56 for storing a plurality of consecutive samples E-1, E, M, L, L + 1 of the incoming spread spectrum signal; A first digitally controlled interpolator (26) for determining an interpolated initial sample (e) that predicts an optimal sampling time by interpolation between successive samples stored in the delay line (56); A second digitally controlled interpolator (24) for determining an interpolated intermediate sample (m) corresponding to the optimal sampling time by interpolation between successive samples stored in the delay line (56); A third digitally controlled interpolator (28) for determining the interpolated terminal sample (1) delayed for the optimal sampling time by interpolation between successive samples stored in the delay line (56); And A digital communication receiver having at least one correlator (30, 32, 22) for calculating an error signal (ξ) as a difference between the energy of the symbol calculated from the interpolated initial sample (e) and the late sample (l) as, A circuit (23) for extracting the sign of the error signal (ξ); And The error signal in the register for generation of control signals S _E , S _M , and S _L for controlling the interpolation phases of the first, second and third digitally controlled interpolators 26, 24 and 28. further comprising a control signal generator 66 for accumulating the code of ξ, The time distance between the interpolated initial sample (e) and the terminal sample (l) is changed with respect to the first control signal (S _M ), and the time resolution of the first and third digital control interpolators (26 and 28) is And a lower than the time resolution of the second digitally controlled interpolator (24). The method of claim 9, And said register in which the sign of said error signal is stored has a positive saturation value of +4 and a negative saturation value of -4. The method according to claim 9 or 10, The time distance between the interpolated initial sample (e) and the terminal sample (l) may be a T _C value that is a period of a fundamental waveform when the first control signal S _M is an even value, or the first control signal ( A digital communication receiver having alternating values of 3 · T _C / 4 when S _M ) is an odd value. The method of claim 10, A second control signal (S _E ) for controlling the first digitally controlled interpolator (26) is generated as a function of the first control signal (S _M ) according to the following equation; Here, the function ┗ · ┛ is a digital communication receiver approximating the independent variable to the nearest lower integer. The method of claim 10, A third control signal S _L for controlling the third digital control interpolator 28 is generated as a function of the first control signal S _M according to the following equation; Here, the function ┗ · ┛ is a digital communication receiver approximating the independent variable to the nearest lower integer. The method of claim 9, And the time resolution used to determine the interpolated initial sample (e) and the late sample (l) by interpolation is half the time resolution used to determine the interpolated intermediate sample (m) by interpolation. The method of claim 14, The plurality of consecutive samples (E-1, E, M, L, L + 1) are time spaced by T _C / (2 · n), where T _C is the period of the fundamental waveform, n is an integer, The time resolution used to determine the interpolated initial sample (e) and the late sample (l) by interpolation is T _C / (4 · n) and the time used to determine the intermediate sample (m) by interpolation. A digital communication receiver whose resolution is T _C / (8 · n). The method of claim 14, The plurality of consecutive samples (E-1, E, M, L, L + 1) are time spaced by T _C / 2, where T _C is the period of the fundamental waveform, and the interpolated initial sample (interpolated by interpolation) e) and the time resolution used to determine the late sample (l) is T _C / 4, and the time resolution used to determine the interpolated intermediate sample (m) by interpolation is T _C / 8. The method according to claim 9 or 10, The delay line (56) stores five consecutive samples (E-1, E, M, L, L + 1) of the incoming spread spectrum signal. The method of claim 17, The first digital control interpolator 26 controlled by the second digital control signal S _E receives the first three samples E-1, E, M stored in the delay line 56 at its input. And generate the interpolated initial sample (e) as a function of the second digital control signal (S _E ) and the first three samples (E-1, E, M). The method of claim 17, The second digital control interpolator 24 controlled by the first digital control signal S _M receives three intermediate samples E, M, L stored in the delay line 56 at an input, And generating said interpolated intermediate sample (m) as a function of said first digital control signal (S _M ) and said three intermediate samples (E, M, L). The method of claim 17, The third digital control interpolator 28 controlled by the third digital control signal S _L receives the last three terminal samples M, L, L + 1 stored in the delay line 56 at the input. Receiving and generating the interpolated terminal sample (l) as a function of the third digital control signal (S _L ) and the last three intermediate samples (M, L, L + 1). The method of claim 9, The first and third digitally controlled interpolators 26 and 28 are implemented as one time multiplexed digitally controlled interpolator, and the interpolated initial sample (e) and terminal sample (l) are calculated at different time intervals. Digital communication receiver.